Problem of RTL transition.

	1. First get current predicate.
	2. Its all variables become terminal or register.
		If variable's value is transfer to futer, it is register.
		Otherwise it is only a terminal.

	3.	So it is necessary to make variable table.
	4. Trace all ( non assigned ) computation.
		Then we get net-time queue for one alternatives.
	5. How to designate, state?
		Sort up predicat and store into some database,
		B-tree will be ok.
	6. add empty or not empty for sub-intervals.
		main interval never terminate. it is an error.

Restriction of Tokio in translating to hardware.

	1. Only First time execution generates true parallel state machine.

                 -------------->
                 |------------->

        2. In the 1th to nth clock, State is binary for each parallel state.

		a,b,a ----> (a & a ),b

		ex. parallel quick sort

		a -> a,a --> a,a,a,a ----> a,a,a,a,a,a,a,a

		( hard ware restriction ).

        3. Hardware had his own restriction. It makes this algorithm
		terminate.

		i.e. in order to terminate expasion, we have
			to implement hardware restreiction.

				( = smae thing in PITL )

		Over expresivness is necssary.