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1 ;; GCC machine description for IA-64 synchronization instructions.
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111
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2 ;; Copyright (C) 2005-2017 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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111
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20 ;; Conversion to C++11 memory model based on
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21 ;; http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
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22
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0
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23 (define_mode_iterator IMODE [QI HI SI DI])
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24 (define_mode_iterator I124MODE [QI HI SI])
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25 (define_mode_iterator I48MODE [SI DI])
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26 (define_mode_attr modesuffix [(QI "1") (HI "2") (SI "4") (DI "8")])
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27
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28 (define_code_iterator FETCHOP [plus minus ior xor and])
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29 (define_code_attr fetchop_name
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111
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30 [(plus "add") (minus "sub") (ior "or") (xor "xor") (and "and")])
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31
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32 (define_expand "mem_thread_fence"
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33 [(match_operand:SI 0 "const_int_operand" "")] ;; model
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34 ""
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35 {
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36 if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0]))))
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37 emit_insn (gen_memory_barrier ());
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38 DONE;
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39 })
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0
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40
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41 (define_expand "memory_barrier"
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42 [(set (match_dup 0)
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43 (unspec:BLK [(match_dup 0)] UNSPEC_MF))]
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44 ""
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45 {
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46 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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47 MEM_VOLATILE_P (operands[0]) = 1;
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48 })
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49
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50 (define_insn "*memory_barrier"
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51 [(set (match_operand:BLK 0 "" "")
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52 (unspec:BLK [(match_dup 0)] UNSPEC_MF))]
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53 ""
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54 "mf"
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55 [(set_attr "itanium_class" "syst_m")])
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56
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111
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57 (define_expand "atomic_load<mode>"
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58 [(match_operand:IMODE 0 "gr_register_operand" "") ;; output
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59 (match_operand:IMODE 1 "memory_operand" "") ;; memory
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60 (match_operand:SI 2 "const_int_operand" "")] ;; model
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61 ""
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62 {
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63 enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
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64
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65 /* Unless the memory model is relaxed, we want to emit ld.acq, which
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66 will happen automatically for volatile memories. */
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67 gcc_assert (is_mm_relaxed (model) || MEM_VOLATILE_P (operands[1]));
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68 emit_move_insn (operands[0], operands[1]);
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69 DONE;
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70 })
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71
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72 (define_expand "atomic_store<mode>"
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73 [(match_operand:IMODE 0 "memory_operand" "") ;; memory
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74 (match_operand:IMODE 1 "gr_reg_or_0_operand" "") ;; input
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75 (match_operand:SI 2 "const_int_operand" "")] ;; model
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76 ""
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77 {
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78 enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
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79
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80 /* Unless the memory model is relaxed, we want to emit st.rel, which
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81 will happen automatically for volatile memories. */
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82 gcc_assert (is_mm_relaxed (model) || MEM_VOLATILE_P (operands[0]));
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83 emit_move_insn (operands[0], operands[1]);
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84
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85 /* Sequentially consistent stores need a subsequent MF. See
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86 http://www.decadent.org.uk/pipermail/cpp-threads/2008-December/001952.html
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87 for a discussion of why a MF is needed here, but not for atomic_load. */
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88 if (is_mm_seq_cst (model))
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89 emit_insn (gen_memory_barrier ());
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90 DONE;
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91 })
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92
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93 (define_expand "atomic_compare_and_swap<mode>"
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94 [(match_operand:DI 0 "gr_register_operand" "") ;; bool out
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95 (match_operand:IMODE 1 "gr_register_operand" "") ;; val out
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96 (match_operand:IMODE 2 "not_postinc_memory_operand" "") ;; memory
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97 (match_operand:IMODE 3 "gr_register_operand" "") ;; expected
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98 (match_operand:IMODE 4 "gr_reg_or_0_operand" "") ;; desired
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99 (match_operand:SI 5 "const_int_operand" "") ;; is_weak
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100 (match_operand:SI 6 "const_int_operand" "") ;; succ model
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101 (match_operand:SI 7 "const_int_operand" "")] ;; fail model
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102 ""
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103 {
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104 /* No need to distinquish __sync from __atomic, so get base value. */
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105 enum memmodel model = memmodel_base (INTVAL (operands[6]));
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106 rtx ccv = gen_rtx_REG (DImode, AR_CCV_REGNUM);
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107 rtx dval, eval;
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108
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109 eval = gen_reg_rtx (DImode);
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110 convert_move (eval, operands[3], 1);
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111 emit_move_insn (ccv, eval);
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112
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113 if (<MODE>mode == DImode)
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114 dval = operands[1];
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115 else
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116 dval = gen_reg_rtx (DImode);
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117
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118 switch (model)
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119 {
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120 case MEMMODEL_RELAXED:
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121 case MEMMODEL_ACQUIRE:
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122 case MEMMODEL_CONSUME:
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123 emit_insn (gen_cmpxchg_acq_<mode> (dval, operands[2], ccv, operands[4]));
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124 break;
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125 case MEMMODEL_RELEASE:
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126 emit_insn (gen_cmpxchg_rel_<mode> (dval, operands[2], ccv, operands[4]));
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127 break;
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128 case MEMMODEL_ACQ_REL:
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129 case MEMMODEL_SEQ_CST:
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130 emit_insn (gen_cmpxchg_rel_<mode> (dval, operands[2], ccv, operands[4]));
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131 emit_insn (gen_memory_barrier ());
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132 break;
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133 default:
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134 gcc_unreachable ();
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135 }
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136
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137 if (<MODE>mode != DImode)
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138 emit_move_insn (operands[1], gen_lowpart (<MODE>mode, dval));
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139
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140 emit_insn (gen_cstoredi4 (operands[0], gen_rtx_EQ (DImode, dval, eval),
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141 dval, eval));
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142 DONE;
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143 })
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144
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145 (define_insn "cmpxchg_acq_<mode>"
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146 [(set (match_operand:DI 0 "gr_register_operand" "=r")
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147 (zero_extend:DI
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148 (match_operand:I124MODE 1 "not_postinc_memory_operand" "+S")))
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149 (set (match_dup 1)
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150 (unspec:I124MODE
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151 [(match_dup 1)
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152 (match_operand:DI 2 "ar_ccv_reg_operand" "")
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153 (match_operand:I124MODE 3 "gr_reg_or_0_operand" "rO")]
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154 UNSPEC_CMPXCHG_ACQ))]
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155 ""
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156 "cmpxchg<modesuffix>.acq %0 = %1, %r3, %2"
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157 [(set_attr "itanium_class" "sem")])
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158
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159 (define_insn "cmpxchg_rel_<mode>"
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160 [(set (match_operand:DI 0 "gr_register_operand" "=r")
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161 (zero_extend:DI
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162 (match_operand:I124MODE 1 "not_postinc_memory_operand" "+S")))
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163 (set (match_dup 1)
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164 (unspec:I124MODE
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165 [(match_dup 1)
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166 (match_operand:DI 2 "ar_ccv_reg_operand" "")
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167 (match_operand:I124MODE 3 "gr_reg_or_0_operand" "rO")]
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168 UNSPEC_CMPXCHG_REL))]
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169 ""
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170 "cmpxchg<modesuffix>.rel %0 = %1, %r3, %2"
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171 [(set_attr "itanium_class" "sem")])
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172
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173 (define_insn "cmpxchg_acq_di"
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174 [(set (match_operand:DI 0 "gr_register_operand" "=r")
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175 (match_operand:DI 1 "not_postinc_memory_operand" "+S"))
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176 (set (match_dup 1)
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177 (unspec:DI [(match_dup 1)
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178 (match_operand:DI 2 "ar_ccv_reg_operand" "")
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179 (match_operand:DI 3 "gr_reg_or_0_operand" "rO")]
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180 UNSPEC_CMPXCHG_ACQ))]
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181 ""
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182 "cmpxchg8.acq %0 = %1, %r3, %2"
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183 [(set_attr "itanium_class" "sem")])
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184
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185 (define_insn "cmpxchg_rel_di"
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186 [(set (match_operand:DI 0 "gr_register_operand" "=r")
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187 (match_operand:DI 1 "not_postinc_memory_operand" "+S"))
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188 (set (match_dup 1)
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189 (unspec:DI [(match_dup 1)
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190 (match_operand:DI 2 "ar_ccv_reg_operand" "")
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191 (match_operand:DI 3 "gr_reg_or_0_operand" "rO")]
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192 UNSPEC_CMPXCHG_REL))]
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193 ""
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194 "cmpxchg8.rel %0 = %1, %r3, %2"
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195 [(set_attr "itanium_class" "sem")])
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196
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197 (define_expand "atomic_exchange<mode>"
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198 [(match_operand:IMODE 0 "gr_register_operand" "") ;; output
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199 (match_operand:IMODE 1 "not_postinc_memory_operand" "") ;; memory
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200 (match_operand:IMODE 2 "gr_reg_or_0_operand" "") ;; input
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201 (match_operand:SI 3 "const_int_operand" "")] ;; succ model
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202 ""
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203 {
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204 /* No need to distinquish __sync from __atomic, so get base value. */
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205 enum memmodel model = memmodel_base (INTVAL (operands[3]));
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206
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207 switch (model)
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208 {
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209 case MEMMODEL_RELAXED:
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210 case MEMMODEL_ACQUIRE:
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211 case MEMMODEL_CONSUME:
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212 break;
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213 case MEMMODEL_RELEASE:
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214 case MEMMODEL_ACQ_REL:
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215 case MEMMODEL_SEQ_CST:
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216 emit_insn (gen_memory_barrier ());
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217 break;
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218 default:
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219 gcc_unreachable ();
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220 }
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221 emit_insn (gen_xchg_acq_<mode> (operands[0], operands[1], operands[2]));
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222 DONE;
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223 })
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224
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225 ;; Note that XCHG is always memory model acquire.
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226 (define_insn "xchg_acq_<mode>"
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227 [(set (match_operand:IMODE 0 "gr_register_operand" "=r")
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228 (match_operand:IMODE 1 "not_postinc_memory_operand" "+S"))
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229 (set (match_dup 1)
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230 (match_operand:IMODE 2 "gr_reg_or_0_operand" "rO"))]
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231 ""
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232 "xchg<modesuffix> %0 = %1, %r2"
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233 [(set_attr "itanium_class" "sem")])
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234
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235 (define_expand "atomic_<fetchop_name><mode>"
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236 [(set (match_operand:IMODE 0 "memory_operand" "")
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237 (FETCHOP:IMODE (match_dup 0)
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238 (match_operand:IMODE 1 "nonmemory_operand" "")))
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239 (use (match_operand:SI 2 "const_int_operand" ""))]
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240 ""
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241 {
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242 ia64_expand_atomic_op (<CODE>, operands[0], operands[1], NULL, NULL,
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243 (enum memmodel) INTVAL (operands[2]));
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244 DONE;
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245 })
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246
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247 (define_expand "atomic_nand<mode>"
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248 [(set (match_operand:IMODE 0 "memory_operand" "")
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249 (not:IMODE
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250 (and:IMODE (match_dup 0)
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251 (match_operand:IMODE 1 "nonmemory_operand" ""))))
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252 (use (match_operand:SI 2 "const_int_operand" ""))]
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253 ""
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254 {
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255 ia64_expand_atomic_op (NOT, operands[0], operands[1], NULL, NULL,
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256 (enum memmodel) INTVAL (operands[2]));
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257 DONE;
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258 })
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259
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260 (define_expand "atomic_fetch_<fetchop_name><mode>"
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261 [(set (match_operand:IMODE 0 "gr_register_operand" "")
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262 (FETCHOP:IMODE
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263 (match_operand:IMODE 1 "memory_operand" "")
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264 (match_operand:IMODE 2 "nonmemory_operand" "")))
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265 (use (match_operand:SI 3 "const_int_operand" ""))]
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266 ""
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267 {
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268 ia64_expand_atomic_op (<CODE>, operands[1], operands[2], operands[0], NULL,
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269 (enum memmodel) INTVAL (operands[3]));
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270 DONE;
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271 })
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272
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273 (define_expand "atomic_fetch_nand<mode>"
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274 [(set (match_operand:IMODE 0 "gr_register_operand" "")
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275 (not:IMODE
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276 (and:IMODE (match_operand:IMODE 1 "memory_operand" "")
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277 (match_operand:IMODE 2 "nonmemory_operand" ""))))
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278 (use (match_operand:SI 3 "const_int_operand" ""))]
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279 ""
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280 {
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281 ia64_expand_atomic_op (NOT, operands[1], operands[2], operands[0], NULL,
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282 (enum memmodel) INTVAL (operands[3]));
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283 DONE;
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284 })
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285
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286 (define_expand "atomic_<fetchop_name>_fetch<mode>"
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287 [(set (match_operand:IMODE 0 "gr_register_operand" "")
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288 (FETCHOP:IMODE
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289 (match_operand:IMODE 1 "memory_operand" "")
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290 (match_operand:IMODE 2 "nonmemory_operand" "")))
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291 (use (match_operand:SI 3 "const_int_operand" ""))]
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292 ""
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293 {
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294 ia64_expand_atomic_op (<CODE>, operands[1], operands[2], NULL, operands[0],
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295 (enum memmodel) INTVAL (operands[3]));
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296 DONE;
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297 })
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298
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299 (define_expand "atomic_nand_fetch<mode>"
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300 [(set (match_operand:IMODE 0 "gr_register_operand" "")
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301 (not:IMODE
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302 (and:IMODE (match_operand:IMODE 1 "memory_operand" "")
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303 (match_operand:IMODE 2 "nonmemory_operand" ""))))
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304 (use (match_operand:SI 3 "const_int_operand" ""))]
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305 ""
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306 {
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307 ia64_expand_atomic_op (NOT, operands[1], operands[2], NULL, operands[0],
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308 (enum memmodel) INTVAL (operands[3]));
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309 DONE;
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310 })
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311
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0
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312 (define_insn "fetchadd_acq_<mode>"
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313 [(set (match_operand:I48MODE 0 "gr_register_operand" "=r")
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314 (match_operand:I48MODE 1 "not_postinc_memory_operand" "+S"))
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315 (set (match_dup 1)
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316 (unspec:I48MODE [(match_dup 1)
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317 (match_operand:I48MODE 2 "fetchadd_operand" "n")]
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318 UNSPEC_FETCHADD_ACQ))]
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319 ""
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320 "fetchadd<modesuffix>.acq %0 = %1, %2"
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321 [(set_attr "itanium_class" "sem")])
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322
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111
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323 (define_insn "fetchadd_rel_<mode>"
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324 [(set (match_operand:I48MODE 0 "gr_register_operand" "=r")
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325 (match_operand:I48MODE 1 "not_postinc_memory_operand" "+S"))
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326 (set (match_dup 1)
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327 (unspec:I48MODE [(match_dup 1)
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328 (match_operand:I48MODE 2 "fetchadd_operand" "n")]
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329 UNSPEC_FETCHADD_REL))]
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0
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330 ""
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111
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331 "fetchadd<modesuffix>.rel %0 = %1, %2"
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0
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332 [(set_attr "itanium_class" "sem")])
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