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1 ;; Machine Description for Renesas RL78 processors
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145
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2 ;; Copyright (C) 2011-2020 Free Software Foundation, Inc.
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111
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3 ;; Contributed by Red Hat.
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4
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify
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8 ;; it under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful,
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13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 ;; GNU General Public License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_constants
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22 [
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23 (AX_REG 0)
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24 (X_REG 0)
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25 (A_REG 1)
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26 (BC_REG 2)
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27 (C_REG 2)
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28 (B_REG 3)
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29 (DE_REG 4)
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30 (E_REG 4)
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31 (D_REG 5)
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32 (HL_REG 6)
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33 (L_REG 6)
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34 (H_REG 7)
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35
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36 (FP_REG 22)
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37 (SP_REG 32)
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38 (CC_REG 34)
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39 (ES_REG 35)
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40 (CS_REG 36)
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41
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42 (UNS_PROLOG 1)
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43 (UNS_EPILOG 1)
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44 (UNS_RETI 2)
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45 (UNS_RETB 3)
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46
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47 (UNS_SET_RB 10)
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48 (UNS_ES_ADDR 11)
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49
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50 (UNS_TRAMPOLINE_INIT 20)
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51 (UNS_TRAMPOLINE_UNINIT 21)
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52 (UNS_NONLOCAL_GOTO 22)
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53
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54 ])
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55
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56 (define_insn "nop"
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57 [(const_int 0)]
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58 ""
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59 "nop"
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60 )
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61
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62 (define_mode_iterator QHI [QI HI])
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63
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64 (include "predicates.md")
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65 (include "constraints.md")
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66 (include "rl78-expand.md")
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67 (include "rl78-virt.md")
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68 (include "rl78-real.md")
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69
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70 (define_attr "is_g13_muldiv_insn" "yes,no" (const_string "no"))
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71
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72 ;; Function Prologue/Epilogue Instructions
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73
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74 (define_expand "prologue"
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75 [(const_int 0)]
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76 ""
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77 "rl78_expand_prologue (); DONE;"
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78 )
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79
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80 (define_expand "epilogue"
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81 [(const_int 0)]
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82 ""
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83 "rl78_expand_epilogue (); DONE;"
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84 )
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85
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86 (define_expand "sibcall_epilogue"
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87 [(return)]
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88 ""
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89 "FAIL;"
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90 )
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91
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92 (define_insn "rl78_return"
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93 [(return)]
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94 ""
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95 "ret"
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96 )
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97
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98 (define_insn "interrupt_return"
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99 [(unspec_volatile [(return)] UNS_RETI) ]
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100 ""
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101 "reti"
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102 )
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103
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104 (define_insn "brk_interrupt_return"
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105 [(unspec_volatile [(return)] UNS_RETB) ]
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106 ""
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107 "retb"
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108 )
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109
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110 (define_expand "eh_return"
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111 [(match_operand:HI 0 "")]
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112 ""
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113 "rl78_expand_eh_epilogue (operands[0]);
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114 emit_barrier ();
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115 DONE;"
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116 )
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117
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118 ;; These are used only by prologue/epilogue so it's "safe" to pass
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119 ;; virtual registers.
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120 (define_insn "push"
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121 [(set (reg:HI SP_REG)
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122 (plus:HI (reg:HI SP_REG)
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123 (const_int -2)))
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124 (set (mem:HI (reg:HI SP_REG))
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125 (match_operand:HI 0 "register_operand" "ABDT,vZint"))]
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126 ""
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127 "@
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128 push\t%v0
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129 push\t%v0 ; %0"
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130 )
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131
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132 (define_insn "pop"
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133 [(set (match_operand:HI 0 "register_operand" "=ABDT,vZint")
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134 (mem:HI (reg:HI SP_REG)))
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135 (set (reg:HI SP_REG)
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136 (plus:HI (reg:HI SP_REG)
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137 (const_int 2)))]
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138 ""
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139 "@
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140 pop\t%v0
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141 pop\t%v0 ; %0"
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142 )
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143
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144 (define_insn "sel_rb"
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145 [(unspec_volatile [(match_operand 0 "immediate_operand" "")] UNS_SET_RB)]
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146 "!TARGET_G10"
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147 "sel\trb%u0"
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148 )
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149
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150 (define_insn "trampoline_init"
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151 [(set (match_operand 0 "register_operand" "=Z08W")
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152 (unspec_volatile [(match_operand 1 "register_operand" "Z08W")
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153 (match_operand 2 "register_operand" "Z10W")
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154 ] UNS_TRAMPOLINE_INIT))
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155 ]
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156 ""
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157 "call !!___trampoline_init ; %0 <= %1 %2"
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158 )
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159
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160 (define_insn "trampoline_uninit"
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161 [(unspec_volatile [(const_int 0)] UNS_TRAMPOLINE_UNINIT)
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162 ]
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163 ""
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164 "call !!___trampoline_uninit"
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165 )
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166
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167 ;; GCC restores $fp *before* using it to access values on the *old*
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168 ;; frame. So, we do it ourselves, to ensure this is not the case.
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169 ;; Note that while %1 is usually a label_ref, we allow for a
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170 ;; non-immediate as well.
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171 (define_expand "nonlocal_goto"
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172 [(set (pc)
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173 (unspec_volatile [(match_operand 0 "") ;; fp (ignore)
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174 (match_operand 1 "") ;; target
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175 (match_operand 2 "") ;; sp
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176 (match_operand 3 "") ;; ?
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177 ] UNS_NONLOCAL_GOTO))
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178 ]
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179 ""
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180 "emit_jump_insn (gen_nonlocal_goto_insn (operands[0], operands[1], operands[2], operands[3]));
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181 emit_barrier ();
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182 DONE;"
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183 )
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184
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185 (define_insn "nonlocal_goto_insn"
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186 [(set (pc)
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187 (unspec_volatile [(match_operand 0 "" "") ;; fp (ignore)
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188 (match_operand 1 "" "vi") ;; target
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189 (match_operand 2 "" "vi") ;; sp
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190 (match_operand 3 "" "vi") ;; ?
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191 ] UNS_NONLOCAL_GOTO))
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192 ]
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193 ""
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194 "; nonlocal goto
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195 movw ax, %3
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196 movw r22, ax
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197 movw ax, %2
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198 movw sp, ax
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199 movw ax, %1
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200 br ax
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201 "
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202 )
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203
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204 (define_expand "es_addr"
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205 [(unspec:SI [(reg:QI ES_REG)
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206 (match_operand:HI 0 "")
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207 ] UNS_ES_ADDR)]
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208 ""
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209 ""
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210 )
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211
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212 ;;======================================================================
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213 ;;
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214 ;; "macro" insns - cases where inline chunks of code are more
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215 ;; efficient than anything else.
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216
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217 (define_expand "addsi3"
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218 [(set (match_operand:SI 0 "nonimmediate_operand" "=&vm")
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219 (plus:SI (match_operand:SI 1 "general_operand" "vim")
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220 (match_operand 2 "general_operand" "vim")))
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221 ]
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222 ""
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223 "emit_insn (gen_addsi3_internal_virt (operands[0], operands[1], operands[2]));
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224 DONE;"
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225 )
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226
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227 (define_expand "adddi3"
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228 [(set (match_operand:DI 0 "nonimmediate_operand" "")
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229 (plus:DI (match_operand:DI 1 "general_operand" "")
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230 (match_operand:DI 2 "general_operand" "")))
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231 ]
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232 ""
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233 "rl78_emit_libcall (\"__adddi3\", PLUS, DImode, DImode, 3, operands);
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234 DONE;"
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235 )
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236
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237 (define_insn "addsi3_internal_virt"
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238 [(set (match_operand:SI 0 "nonimmediate_operand" "=v,&vm, vm")
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239 (plus:SI (match_operand:SI 1 "general_operand" "0, vim, vim")
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240 (match_operand 2 "general_operand" "vim,vim,vim")))
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241 (clobber (reg:HI AX_REG))
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242 (clobber (reg:HI BC_REG))
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243 ]
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244 "rl78_virt_insns_ok ()"
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245 ""
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246 [(set_attr "valloc" "macax")]
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247 )
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248
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249 (define_insn "addsi3_internal_real"
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250 [(set (match_operand:SI 0 "nonimmediate_operand" "=v,&vU, vU")
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251 (plus:SI (match_operand:SI 1 "general_operand" "+0, viU, viU")
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252 (match_operand 2 "general_operand" "viWabWhlWh1,viWabWhlWh1,viWabWhlWh1")))
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253 (clobber (reg:HI AX_REG))
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254 (clobber (reg:HI BC_REG))
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255 ]
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256 "rl78_real_insns_ok ()"
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257 { return rl78_addsi3_internal (operands, which_alternative); }
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258 [(set_attr "valloc" "macax")]
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259 )
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260
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261 (define_expand "subsi3"
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262 [(set (match_operand:SI 0 "nonimmediate_operand")
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263 (minus:SI (match_operand:SI 1 "general_operand")
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264 (match_operand 2 "general_operand")))
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265 ]
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266 ""
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267 "emit_insn (gen_subsi3_internal_virt (operands[0], operands[1], operands[2]));
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268 DONE;"
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269 )
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270
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271 (define_expand "subdi3"
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272 [(set (match_operand:DI 0 "nonimmediate_operand" "")
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273 (minus:DI (match_operand:DI 1 "general_operand" "")
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274 (match_operand:DI 2 "general_operand" "")))
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275 ]
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276 ""
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277 "rl78_emit_libcall (\"__subdi3\", MINUS, DImode, DImode, 3, operands);
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278 DONE;"
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279 )
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280
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281 (define_insn "subsi3_internal_virt"
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282 [(set (match_operand:SI 0 "nonimmediate_operand" "=v,&vm, vm")
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283 (minus:SI (match_operand:SI 1 "general_operand" "0, vim, vim")
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284 (match_operand 2 "general_operand" "vim,vim,vim")))
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285 (clobber (reg:HI AX_REG))
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286 (clobber (reg:HI BC_REG))
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287 ]
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288 "rl78_virt_insns_ok ()"
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289 ""
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290 [(set_attr "valloc" "macax")]
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291 )
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292
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293 (define_insn "subsi3_internal_real"
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294 [(set (match_operand:SI 0 "nonimmediate_operand" "=v,&vU, vU")
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295 (minus:SI (match_operand:SI 1 "general_operand" "+0, viU, viU")
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296 (match_operand 2 "general_operand" "viWabWhlWh1,viWabWhlWh1,viWabWhlWh1")))
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297 (clobber (reg:HI AX_REG))
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298 (clobber (reg:HI BC_REG))
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299 ]
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300 "rl78_real_insns_ok ()"
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301 "@
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302 movw ax,%h1 \;subw ax,%h2 \;movw %h0, ax \;movw ax,%H1 \;sknc \;decw ax \;subw ax,%H2 \;movw %H0,ax
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303 movw ax,%h1 \;subw ax,%h2 \;movw %h0, ax \;movw ax,%H1 \;sknc \;decw ax \;subw ax,%H2 \;movw %H0,ax
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304 movw ax,%h1 \;subw ax,%h2 \;movw bc, ax \;movw ax,%H1 \;sknc \;decw ax \;subw ax,%H2 \;movw %H0,ax \;movw ax,bc \;movw %h0, ax"
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305 [(set_attr "valloc" "macax")]
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306 )
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307
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308 (define_expand "mulqi3"
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309 [(parallel
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310 [(set (match_operand:QI 0 "register_operand")
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311 (mult:QI (match_operand:QI 1 "general_operand")
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312 (match_operand:QI 2 "nonmemory_operand")))
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313 (clobber (reg:HI AX_REG))
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314 ])
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315 ]
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316 "" ; mulu supported by all targets
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317 ""
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318 )
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319
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320 (define_expand "mulhi3"
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321 [(set (match_operand:HI 0 "register_operand")
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322 (mult:HI (match_operand:HI 1 "general_operand")
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323 (match_operand:HI 2 "nonmemory_operand")))
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324 ]
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325 "! RL78_MUL_NONE"
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326 {
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327 if (RL78_MUL_G14)
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328 emit_insn (gen_mulhi3_g14 (operands[0], operands[1], operands[2]));
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329 else /* RL78_MUL_G13 */
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330 emit_insn (gen_mulhi3_g13 (operands[0], operands[1], operands[2]));
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331 DONE;
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332 }
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333 )
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334
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335 (define_expand "mulsi3"
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336 [(set (match_operand:SI 0 "register_operand")
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337 (mult:SI (match_operand:SI 1 "general_operand")
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338 (match_operand:SI 2 "nonmemory_operand")))
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339 ]
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340 "! RL78_MUL_NONE"
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341 {
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342 if (RL78_MUL_G14)
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343 emit_insn (gen_mulsi3_g14 (operands[0], operands[1], operands[2]));
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344 else /* RL78_MUL_G13 */
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345 emit_insn (gen_mulsi3_g13 (operands[0], operands[1], operands[2]));
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346 DONE;
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347 }
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348 )
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349
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350 (define_insn "*mulqi3_rl78"
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351 [(set (match_operand:QI 0 "register_operand" "=&v")
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352 (mult:QI (match_operand:QI 1 "general_operand" "viU")
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353 (match_operand:QI 2 "general_operand" "vi")))
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354 (clobber (reg:HI AX_REG))
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355 ]
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356 "" ; mulu supported by all targets
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357 "; mulqi macro %0 = %1 * %2
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358 mov a, %h1
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359 mov x, a
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360 mov a, %h2
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361 mulu x ; ax = a * x
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362 mov a, x
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363 mov %h0, a
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364 ; end of mulqi macro"
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365 [(set_attr "valloc" "macax")]
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366 )
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367
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368 (define_insn "mulhi3_g14"
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369 [(set (match_operand:HI 0 "register_operand" "=&v")
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370 (mult:HI (match_operand:HI 1 "general_operand" "viU")
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371 (match_operand:HI 2 "general_operand" "vi")))
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372 (clobber (reg:HI AX_REG))
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373 (clobber (reg:HI BC_REG))
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374 ]
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375 "RL78_MUL_G14"
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376 "; G14 mulhi macro %0 = %1 * %2
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377 movw ax, %h1
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378 movw bc, %h2
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379 mulhu ; bcax = bc * ax
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380 movw %h0, ax
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381 ; end of mulhi macro"
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382 [(set_attr "valloc" "macax")]
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383 )
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384
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385 (define_insn "mulhi3_g13"
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386 [(set (match_operand:HI 0 "register_operand" "=&v")
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387 (mult:HI (match_operand:HI 1 "general_operand" "viU")
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388 (match_operand:HI 2 "general_operand" "vi")))
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389 (clobber (reg:HI AX_REG))
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390 ]
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391 "RL78_MUL_G13"
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|
|
392 "; G13 mulhi macro %0 = %1 * %2
|
|
|
393 mov a, #0x00
|
|
|
394 mov !0xf00e8, a ; MDUC
|
|
|
395 movw ax, %h1
|
|
|
396 movw 0xffff0, ax ; MDAL
|
|
|
397 movw ax, %h2
|
|
|
398 movw 0xffff2, ax ; MDAH
|
|
|
399 nop ; mdb = mdal * mdah
|
|
|
400 movw ax, 0xffff6 ; MDBL
|
|
|
401 movw %h0, ax
|
|
|
402 ; end of mulhi macro"
|
|
|
403 [(set_attr "valloc" "macax")
|
|
|
404 (set_attr "is_g13_muldiv_insn" "yes")]
|
|
|
405 )
|
|
|
406
|
|
|
407 ;; 0xFFFF0 is MACR(L). 0xFFFF2 is MACR(H) but we don't care about it
|
|
|
408 ;; because we're only using the lower 16 bits (which is the upper 16
|
|
|
409 ;; bits of the result).
|
|
|
410 (define_insn "mulsi3_g14"
|
|
|
411 [(set (match_operand:SI 0 "register_operand" "=&v")
|
|
|
412 (mult:SI (match_operand:SI 1 "general_operand" "viU")
|
|
|
413 (match_operand:SI 2 "general_operand" "vi")))
|
|
|
414 (clobber (reg:HI AX_REG))
|
|
|
415 (clobber (reg:HI BC_REG))
|
|
|
416 ]
|
|
|
417 "RL78_MUL_G14"
|
|
|
418 "; G14 mulsi macro %0 = %1 * %2
|
|
|
419 movw ax, %h1
|
|
|
420 movw bc, %h2
|
|
|
421 MULHU ; bcax = bc * ax
|
|
|
422 movw %h0, ax
|
|
|
423 movw ax, bc
|
|
|
424 movw 0xffff0, ax
|
|
|
425 movw ax, %H1
|
|
|
426 movw bc, %h2
|
|
|
427 MACHU ; MACR += bc * ax
|
|
|
428 movw ax, %h1
|
|
|
429 movw bc, %H2
|
|
|
430 MACHU ; MACR += bc * ax
|
|
|
431 movw ax, 0xffff0
|
|
|
432 movw %H0, ax
|
|
|
433 ; end of mulsi macro"
|
|
|
434 [(set_attr "valloc" "macax")]
|
|
|
435 )
|
|
|
436
|
|
|
437 ;; 0xFFFF0 is MDAL. 0xFFFF2 is MDAH.
|
|
|
438 ;; 0xFFFF6 is MDBL. 0xFFFF4 is MDBH.
|
|
|
439 ;; 0xF00E0 is MDCL. 0xF00E2 is MDCH.
|
|
|
440 ;; 0xF00E8 is MDUC.
|
|
|
441 ;; Warning: this matches the silicon not the documentation.
|
|
|
442 (define_insn "mulsi3_g13"
|
|
|
443 [(set (match_operand:SI 0 "register_operand" "=&v")
|
|
|
444 (mult:SI (match_operand:SI 1 "general_operand" "viU")
|
|
|
445 (match_operand:SI 2 "general_operand" "viU")))
|
|
|
446 (clobber (reg:HI AX_REG))
|
|
|
447 (clobber (reg:HI BC_REG))
|
|
|
448 ]
|
|
|
449 "RL78_MUL_G13"
|
|
|
450 "; G13 mulsi macro %0 = %1 * %2
|
|
|
451 mov a, #0x00
|
|
|
452 mov !0xf00e8, a ; MDUC
|
|
|
453 movw ax, %h1
|
|
|
454 movw 0xffff0, ax ; MDAL
|
|
|
455 movw ax, %h2
|
|
|
456 movw 0xffff2, ax ; MDAH
|
|
|
457 nop ; mdb = mdal * mdah
|
|
|
458 movw ax, 0xffff6 ; MDBL
|
|
|
459 movw %h0, ax
|
|
|
460
|
|
|
461 mov a, #0x40
|
|
|
462 mov !0xf00e8, a ; MDUC
|
|
|
463 movw ax, 0xffff4 ; MDBH
|
|
|
464 movw !0xf00e0, ax ; MDCL
|
|
|
465 movw ax, #0
|
|
|
466 movw !0xf00e2, ax ; MDCL
|
|
|
467 movw ax, %H1
|
|
|
468 movw 0xffff0, ax ; MDAL
|
|
|
469 movw ax, %h2
|
|
|
470 movw 0xffff2, ax ; MDAH
|
|
|
471 nop ; mdc += mdal * mdah
|
|
|
472
|
|
|
473 mov a, #0x40
|
|
|
474 mov !0xf00e8, a ; MDUC
|
|
|
475 movw ax, %h1
|
|
|
476 movw 0xffff0, ax ; MDAL
|
|
|
477 movw ax, %H2
|
|
|
478 movw 0xffff2, ax ; MDAH
|
|
|
479 nop ; mdc += mdal * mdah
|
|
|
480 nop ; Additional nop for MAC
|
|
|
481 movw ax, !0xf00e0 ; MDCL
|
|
|
482 movw %H0, ax
|
|
|
483 ; end of mulsi macro"
|
|
|
484 [(set_attr "valloc" "macax")
|
|
|
485 (set_attr "is_g13_muldiv_insn" "yes")]
|
|
|
486 )
|
|
|
487
|
|
|
488 (define_expand "udivmodhi4"
|
|
|
489 [(parallel
|
|
|
490 [(set (match_operand:HI 0 "register_operand")
|
|
|
491 (udiv:HI (match_operand:HI 1 "register_operand")
|
|
|
492 (match_operand:HI 2 "register_operand")))
|
|
|
493 (set (match_operand:HI 3 "register_operand")
|
|
|
494 (umod:HI (match_dup 1) (match_dup 2)))
|
|
|
495 (clobber (reg:HI AX_REG))
|
|
|
496 (clobber (reg:HI DE_REG))
|
|
|
497 ])
|
|
|
498 ]
|
|
|
499 "RL78_MUL_G14"
|
|
|
500 ""
|
|
|
501 )
|
|
|
502
|
|
|
503 (define_insn "*udivmodhi4_g14"
|
|
|
504 [(set (match_operand:HI 0 "register_operand" "=v")
|
|
|
505 (udiv:HI (match_operand:HI 1 "register_operand" "v")
|
|
|
506 (match_operand:HI 2 "register_operand" "v")))
|
|
|
507 (set (match_operand:HI 3 "register_operand" "=v")
|
|
|
508 (umod:HI (match_dup 1) (match_dup 2)))
|
|
|
509 (clobber (reg:HI AX_REG))
|
|
|
510 (clobber (reg:HI DE_REG))
|
|
|
511 ]
|
|
|
512 "RL78_MUL_G14"
|
|
|
513 {
|
|
|
514 if (find_reg_note (insn, REG_UNUSED, operands[3]))
|
|
|
515 return "; G14 udivhi macro %0 = %1 / %2 \n\
|
|
|
516 movw ax, %h1 \n\
|
|
|
517 movw de, %h2 \n\
|
|
|
518 push psw ; Save the current interrupt status \n\
|
|
|
519 di ; Disable interrupts. See Renesas Technical update TN-RL*-A025B/E \n\
|
|
|
520 divhu ; ax = ax / de \n\
|
|
|
521 pop psw ; Restore saved interrupt status \n\
|
|
|
522 movw %h0, ax \n\
|
|
|
523 ; end of udivhi macro";
|
|
|
524 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
|
|
|
525 return "; G14 umodhi macro %3 = %1 %% %2 \n\
|
|
|
526 movw ax, %h1 \n\
|
|
|
527 movw de, %h2 \n\
|
|
|
528 push psw ; Save the current interrupt status \n\
|
|
|
529 di ; Disable interrupts. See Renesas Technical update TN-RL*-A025B/E \n\
|
|
|
530 divhu ; de = ax %% de \n\
|
|
|
531 pop psw ; Restore saved interrupt status \n\
|
|
|
532 movw ax, de \n\
|
|
|
533 movw %h3, ax \n\
|
|
|
534 ; end of umodhi macro";
|
|
|
535 else
|
|
|
536 return "; G14 udivmodhi macro %0 = %1 / %2 and %3 = %1 %% %2 \n\
|
|
|
537 movw ax, %h1 \n\
|
|
|
538 movw de, %h2 \n\
|
|
|
539 push psw ; Save the current interrupt status \n\
|
|
|
540 di ; Disable interrupts. See Renesas Technical update TN-RL*-A025B/E \n\
|
|
|
541 divhu ; ax = ax / de, de = ax %% de \n\
|
|
|
542 pop psw ; Restore saved interrupt status \n\
|
|
|
543 movw %h0, ax \n\
|
|
|
544 movw ax, de \n\
|
|
|
545 movw %h3, ax \n\
|
|
|
546 ; end of udivmodhi macro";
|
|
|
547 }
|
|
|
548 [(set_attr "valloc" "divhi")]
|
|
|
549 )
|
|
|
550
|
|
|
551 (define_expand "udivmodsi4"
|
|
|
552 [(parallel
|
|
|
553 [(set (match_operand:SI 0 "register_operand")
|
|
|
554 (udiv:SI (match_operand:SI 1 "register_operand")
|
|
|
555 (match_operand:SI 2 "register_operand")))
|
|
|
556 (set (match_operand:SI 3 "register_operand")
|
|
|
557 (umod:SI (match_dup 1) (match_dup 2)))
|
|
|
558 ])
|
|
|
559 ]
|
|
|
560 "! RL78_MUL_NONE && ! optimize_size"
|
|
|
561 {
|
|
|
562 if (RL78_MUL_G14)
|
|
|
563 emit_insn (gen_udivmodsi4_g14 (operands[0], operands[1], operands[2], operands[3]));
|
|
|
564 else /* RL78_MUL_G13 */
|
|
|
565 emit_insn (gen_udivmodsi4_g13 (operands[0], operands[1], operands[2], operands[3]));
|
|
|
566 DONE;
|
|
|
567 }
|
|
|
568 )
|
|
|
569
|
|
|
570 (define_insn "udivmodsi4_g14"
|
|
|
571 [(set (match_operand:SI 0 "register_operand" "=v")
|
|
|
572 (udiv:SI (match_operand:SI 1 "register_operand" "v")
|
|
|
573 (match_operand:SI 2 "register_operand" "v")))
|
|
|
574 (set (match_operand:SI 3 "register_operand" "=v")
|
|
|
575 (umod:SI (match_dup 1) (match_dup 2)))
|
|
|
576 (clobber (reg:HI AX_REG))
|
|
|
577 (clobber (reg:HI BC_REG))
|
|
|
578 (clobber (reg:HI DE_REG))
|
|
|
579 (clobber (reg:HI HL_REG))
|
|
|
580 ]
|
|
|
581 "RL78_MUL_G14"
|
|
|
582 {
|
|
|
583 if (find_reg_note (insn, REG_UNUSED, operands[3]))
|
|
|
584 return "; G14 udivsi macro %0 = %1 / %2 \n\
|
|
|
585 movw ax, %h1 \n\
|
|
|
586 movw bc, %H1 \n\
|
|
|
587 movw de, %h2 \n\
|
|
|
588 movw hl, %H2 \n\
|
|
|
589 push psw ; Save the current interrupt status \n\
|
|
|
590 di ; Disable interrupts. See Renesas Technical update TN-RL*-A025B/E \n\
|
|
|
591 divwu ; bcax = bcax / hlde \n\
|
|
|
592 pop psw ; Restore saved interrupt status \n\
|
|
|
593 movw %h0, ax \n\
|
|
|
594 movw ax, bc \n\
|
|
|
595 movw %H0, ax \n\
|
|
|
596 ; end of udivsi macro";
|
|
|
597 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
|
|
|
598 return "; G14 umodsi macro %3 = %1 %% %2 \n\
|
|
|
599 movw ax, %h1 \n\
|
|
|
600 movw bc, %H1 \n\
|
|
|
601 movw de, %h2 \n\
|
|
|
602 movw hl, %H2 \n\
|
|
|
603 push psw ; Save the current interrupt status \n\
|
|
|
604 di ; Disable interrupts. See Renesas Technical update TN-RL*-A025B/E \n\
|
|
|
605 divwu ; hlde = bcax %% hlde \n\
|
|
|
606 pop psw ; Restore saved interrupt status \n\
|
|
|
607 movw ax, de \n\
|
|
|
608 movw %h3, ax \n\
|
|
|
609 movw ax, hl \n\
|
|
|
610 movw %H3, ax \n\
|
|
|
611 ; end of umodsi macro";
|
|
|
612 else
|
|
|
613 return "; G14 udivmodsi macro %0 = %1 / %2 and %3 = %1 %% %2 \n\
|
|
|
614 movw ax, %h1 \n\
|
|
|
615 movw bc, %H1 \n\
|
|
|
616 movw de, %h2 \n\
|
|
|
617 movw hl, %H2 \n\
|
|
|
618 push psw ; Save the current interrupt status \n\
|
|
|
619 di ; Disable interrupts. See Renesas Technical update TN-RL*-A025B/E \n\
|
|
|
620 divwu ; bcax = bcax / hlde, hlde = bcax %% hlde \n\
|
|
|
621 pop psw ; Restore saved interrupt status \n\
|
|
|
622 movw %h0, ax \n\
|
|
|
623 movw ax, bc \n\
|
|
|
624 movw %H0, ax \n\
|
|
|
625 movw ax, de \n\
|
|
|
626 movw %h3, ax \n\
|
|
|
627 movw ax, hl \n\
|
|
|
628 movw %H3, ax \n\
|
|
|
629 ; end of udivmodsi macro";
|
|
|
630 }
|
|
|
631 [(set_attr "valloc" "divsi")]
|
|
|
632 )
|
|
|
633
|
|
|
634 ;; Warning: these values match the silicon not the documentation.
|
|
|
635 ;; 0xFFFF0 is MDAL. 0xFFFF2 is MDAH.
|
|
|
636 ;; 0xFFFF6 is MDBL. 0xFFFF4 is MDBH.
|
|
|
637 ;; 0xF00E0 is MDCL. 0xF00E2 is MDCH.
|
|
|
638 ;; 0xF00E8 is MDUC.
|
|
|
639
|
|
|
640 (define_insn "udivmodsi4_g13"
|
|
|
641 [(set (match_operand:SI 0 "register_operand" "=v")
|
|
|
642 (udiv:SI (match_operand:SI 1 "register_operand" "v")
|
|
|
643 (match_operand:SI 2 "register_operand" "v")))
|
|
|
644 (set (match_operand:SI 3 "register_operand" "=v")
|
|
|
645 (umod:SI (match_dup 1) (match_dup 2)))
|
|
|
646 (clobber (reg:HI AX_REG))
|
|
|
647 ]
|
|
|
648 "RL78_MUL_G13"
|
|
|
649 {
|
|
|
650 if (find_reg_note (insn, REG_UNUSED, operands[3]))
|
|
|
651 return "; G13 udivsi macro %0 = %1 / %2 \n\
|
|
|
652 mov a, #0xC0 ; Set DIVMODE=1 and MACMODE=1 \n\
|
|
|
653 mov !0xf00e8, a ; This preps the peripheral for division without interrupt generation \n\
|
|
|
654 movw ax, %H1 \n\
|
|
|
655 movw 0xffff2, ax ; MDAH \n\
|
|
|
656 movw ax, %h1 \n\
|
|
|
657 movw 0xffff0, ax ; MDAL \n\
|
|
|
658 movw ax, %H2 \n\
|
|
|
659 movw 0xffff4, ax ; MDBH \n\
|
|
|
660 movw ax, %h2 \n\
|
|
|
661 movw 0xffff6, ax ; MDBL \n\
|
|
|
662 mov a, #0xC1 ; Set the DIVST bit in MDUC \n\
|
|
|
663 mov !0xf00e8, a ; This starts the division op \n\
|
|
|
664 1: mov a, !0xf00e8 ; Wait 16 clocks or until DIVST is clear \n\
|
|
|
665 bt a.0, $1b \n\
|
|
|
666 movw ax, 0xffff0 ; Read the quotient \n\
|
|
|
667 movw %h0, ax \n\
|
|
|
668 movw ax, 0xffff2 \n\
|
|
|
669 movw %H0, ax \n\
|
|
|
670 ; end of udivsi macro";
|
|
|
671 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
|
|
|
672 return "; G13 umodsi macro %3 = %1 %% %2 \n\
|
|
|
673 mov a, #0xC0 ; Set DIVMODE=1 and MACMODE=1 \n\
|
|
|
674 mov !0xf00e8, a ; This preps the peripheral for division without interrupt generation \n\
|
|
|
675 movw ax, %H1 \n\
|
|
|
676 movw 0xffff2, ax ; MDAH \n\
|
|
|
677 movw ax, %h1 \n\
|
|
|
678 movw 0xffff0, ax ; MDAL \n\
|
|
|
679 movw ax, %H2 \n\
|
|
|
680 movw 0xffff4, ax ; MDBH \n\
|
|
|
681 movw ax, %h2 \n\
|
|
|
682 movw 0xffff6, ax ; MDBL \n\
|
|
|
683 mov a, #0xC1 ; Set the DIVST bit in MDUC \n\
|
|
|
684 mov !0xf00e8, a ; This starts the division op \n\
|
|
|
685 1: mov a, !0xf00e8 ; Wait 16 clocks or until DIVST is clear \n\
|
|
|
686 bt a.0, $1b \n\
|
|
|
687 movw ax, !0xf00e0 ; Read the remainder \n\
|
|
|
688 movw %h3, ax \n\
|
|
|
689 movw ax, !0xf00e2 \n\
|
|
|
690 movw %H3, ax \n\
|
|
|
691 ; end of umodsi macro";
|
|
|
692 else
|
|
|
693 return "; G13 udivmodsi macro %0 = %1 / %2 and %3 = %1 %% %2 \n\
|
|
|
694 mov a, #0xC0 ; Set DIVMODE=1 and MACMODE=1 \n\
|
|
|
695 mov !0xf00e8, a ; This preps the peripheral for division without interrupt generation \n\
|
|
|
696 movw ax, %H1 \n\
|
|
|
697 movw 0xffff2, ax ; MDAH \n\
|
|
|
698 movw ax, %h1 \n\
|
|
|
699 movw 0xffff0, ax ; MDAL \n\
|
|
|
700 movw ax, %H2 \n\
|
|
|
701 movw 0xffff4, ax ; MDBH \n\
|
|
|
702 movw ax, %h2 \n\
|
|
|
703 movw 0xffff6, ax ; MDBL \n\
|
|
|
704 mov a, #0xC1 ; Set the DIVST bit in MDUC \n\
|
|
|
705 mov !0xf00e8, a ; This starts the division op \n\
|
|
|
706 1: mov a, !0xf00e8 ; Wait 16 clocks or until DIVST is clear \n\
|
|
|
707 bt a.0, $1b \n\
|
|
|
708 movw ax, 0xffff0 ; Read the quotient \n\
|
|
|
709 movw %h0, ax \n\
|
|
|
710 movw ax, 0xffff2 \n\
|
|
|
711 movw %H0, ax \n\
|
|
|
712 movw ax, !0xf00e0 ; Read the remainder \n\
|
|
|
713 movw %h3, ax \n\
|
|
|
714 movw ax, !0xf00e2 \n\
|
|
|
715 movw %H3, ax \n\
|
|
|
716 ; end of udivmodsi macro";
|
|
|
717 }
|
|
|
718 [(set_attr "valloc" "macax")
|
|
|
719 (set_attr "is_g13_muldiv_insn" "yes")]
|
|
|
720 )
|
|
131
|
721
|
|
|
722 (define_expand "movdi"
|
|
|
723 [(set (match_operand:DI 0 "nonimmediate_operand" "")
|
|
|
724 (match_operand:DI 1 "general_operand" ""))]
|
|
|
725 ""
|
|
|
726 "rl78_split_movdi(operands, DImode);
|
|
|
727 DONE;"
|
|
|
728 )
|
|
|
729
|
|
|
730 (define_expand "movdf"
|
|
|
731 [(set (match_operand:DF 0 "nonimmediate_operand" "")
|
|
|
732 (match_operand:DF 1 "general_operand" ""))]
|
|
|
733 ""
|
|
|
734 "rl78_split_movdi(operands, DFmode);
|
|
|
735 DONE;"
|
|
|
736 )
|
|
|
737
|
|
|
738 (define_expand "umindi3"
|
|
|
739 [(set (match_operand:DI 0 "nonimmediate_operand" "")
|
|
|
740 (umin:DI (match_operand:DI 1 "general_operand" "")
|
|
|
741 (match_operand:DI 2 "general_operand" "")))
|
|
|
742 ]
|
|
|
743 "optimize_size"
|
|
|
744 "rl78_emit_libcall (\"__umindi3\", UMIN, DImode, DImode, 3, operands);
|
|
|
745 DONE;"
|
|
|
746 )
|
|
|
747
|
|
|
748 (define_expand "umaxdi3"
|
|
|
749 [(set (match_operand:DI 0 "nonimmediate_operand" "")
|
|
|
750 (umax:DI (match_operand:DI 1 "general_operand" "")
|
|
|
751 (match_operand:DI 2 "general_operand" "")))
|
|
|
752 ]
|
|
|
753 "optimize_size"
|
|
|
754 "rl78_emit_libcall (\"__umaxdi3\", UMAX, DImode, DImode, 3, operands);
|
|
|
755 DONE;"
|
|
|
756 )
|
|
|
757
|
|
|
758 (define_expand "smindi3"
|
|
|
759 [(set (match_operand:DI 0 "nonimmediate_operand" "")
|
|
|
760 (smin:DI (match_operand:DI 1 "general_operand" "")
|
|
|
761 (match_operand:DI 2 "general_operand" "")))
|
|
|
762 ]
|
|
|
763 "optimize_size"
|
|
|
764 "rl78_emit_libcall (\"__smindi3\", SMIN, DImode, DImode, 3, operands);
|
|
|
765 DONE;"
|
|
|
766 )
|
|
|
767
|
|
|
768 (define_expand "smaxdi3"
|
|
|
769 [(set (match_operand:DI 0 "nonimmediate_operand" "")
|
|
|
770 (smax:DI (match_operand:DI 1 "general_operand" "")
|
|
|
771 (match_operand:DI 2 "general_operand" "")))
|
|
|
772 ]
|
|
|
773 "optimize_size"
|
|
|
774 "rl78_emit_libcall (\"__smaxdi3\", SMAX, DImode, DImode, 3, operands);
|
|
|
775 DONE;"
|
|
|
776 )
|
|
|
777
|
|
|
778 (define_expand "anddi3"
|
|
|
779 [(set (match_operand:DI 0 "nonimmediate_operand" "")
|
|
|
780 (and:DI (match_operand:DI 1 "general_operand" "")
|
|
|
781 (match_operand:DI 2 "general_operand" "")))
|
|
|
782 ]
|
|
|
783 "optimize_size"
|
|
|
784 "rl78_emit_libcall (\"__anddi3\", AND, DImode, DImode, 3, operands);
|
|
|
785 DONE;"
|
|
|
786 )
|
