|
111
|
1 /* { dg-do compile { target powerpc*-*-* ia64-*-* i?86-*-* x86_64-*-* } } */
|
|
|
2 /* { dg-options "-O2 -fselective-scheduling -fmodulo-sched" } */
|
|
|
3
|
|
|
4 enum rtx_code
|
|
|
5 {
|
|
|
6 INSN, ADDR_VEC, ADDR_DIFF_VEC, CALL_INSN, CODE_LABEL, BARRIER, NOTE
|
|
|
7 };
|
|
|
8 typedef union rtunion_def
|
|
|
9 {
|
|
|
10 int rtint;
|
|
|
11 char *rtstr;
|
|
|
12 struct rtx_def *rtx;
|
|
|
13 struct rtvec_def *rtvec;
|
|
|
14 }
|
|
|
15 rtunion;
|
|
|
16 typedef struct rtx_def
|
|
|
17 {
|
|
|
18 unsigned short code;
|
|
|
19 rtunion fld[1];
|
|
|
20 }
|
|
|
21 *rtx;
|
|
|
22 typedef struct rtvec_def
|
|
|
23 {
|
|
|
24 unsigned num_elem;
|
|
|
25 rtunion elem[1];
|
|
|
26 }
|
|
|
27 *rtvec;
|
|
|
28 extern rtx emit_barrier (void);
|
|
|
29 extern rtx emit_note (char *);
|
|
|
30
|
|
|
31 static void
|
|
|
32 copy_loop_body (rtx *map)
|
|
|
33 {
|
|
|
34 int i;
|
|
|
35 rtx insn, copy;
|
|
|
36 rtx pat = copy->fld[3].rtx;
|
|
|
37
|
|
|
38 switch (insn->code)
|
|
|
39 {
|
|
|
40 case INSN:
|
|
|
41 if (insn->fld[7].rtx)
|
|
|
42 {
|
|
|
43 }
|
|
|
44 else if (pat->code == ADDR_VEC || pat->code == ADDR_DIFF_VEC)
|
|
|
45 {
|
|
|
46 int diff_vec_p = pat->code == ADDR_DIFF_VEC;
|
|
|
47 int len = pat->fld[diff_vec_p].rtvec->num_elem;
|
|
|
48 for (i = 0; i < len; i++)
|
|
|
49 pat->fld[diff_vec_p].rtvec->elem[i].rtx->fld[5].rtint++;
|
|
|
50 }
|
|
|
51 case CALL_INSN:
|
|
|
52 for (i = 0; i < 64; i++)
|
|
|
53 map[i] = 0;
|
|
|
54 case CODE_LABEL:
|
|
|
55 case BARRIER:
|
|
|
56 copy = emit_barrier ();
|
|
|
57 case NOTE:
|
|
|
58 copy = emit_note ("x");
|
|
|
59 }
|
|
|
60 }
|
|
|
61 void
|
|
|
62 unroll_loop (int insn_count, rtx *map)
|
|
|
63 {
|
|
|
64 if (insn_count > 50)
|
|
|
65 copy_loop_body (map);
|
|
|
66 }
|
|
|
67
|
