Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/i386/i386.h @ 25:2476ed92181e
modified machine description of i386 for support indirect sibcall attributed fastcall.
author | kent <kent@cr.ie.u-ryukyu.ac.jp> |
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date | Tue, 27 Oct 2009 16:04:06 +0900 |
parents | 58ad6c70ea60 |
children | 77e2b8dfacca |
rev | line source |
---|---|
0 | 1 /* Definitions of target machine for GCC for IA-32. |
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, | |
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 | |
4 Free Software Foundation, Inc. | |
5 | |
6 This file is part of GCC. | |
7 | |
8 GCC is free software; you can redistribute it and/or modify | |
9 it under the terms of the GNU General Public License as published by | |
10 the Free Software Foundation; either version 3, or (at your option) | |
11 any later version. | |
12 | |
13 GCC is distributed in the hope that it will be useful, | |
14 but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 GNU General Public License for more details. | |
17 | |
18 Under Section 7 of GPL version 3, you are granted additional | |
19 permissions described in the GCC Runtime Library Exception, version | |
20 3.1, as published by the Free Software Foundation. | |
21 | |
22 You should have received a copy of the GNU General Public License and | |
23 a copy of the GCC Runtime Library Exception along with this program; | |
24 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
25 <http://www.gnu.org/licenses/>. */ | |
26 | |
27 /* The purpose of this file is to define the characteristics of the i386, | |
28 independent of assembler syntax or operating system. | |
29 | |
30 Three other files build on this one to describe a specific assembler syntax: | |
31 bsd386.h, att386.h, and sun386.h. | |
32 | |
33 The actual tm.h file for a particular system should include | |
34 this file, and then the file for the appropriate assembler syntax. | |
35 | |
36 Many macros that specify assembler syntax are omitted entirely from | |
37 this file because they really belong in the files for particular | |
38 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, | |
39 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many | |
40 that start with ASM_ or end in ASM_OP. */ | |
41 | |
42 /* Redefines for option macros. */ | |
43 | |
44 #define TARGET_64BIT OPTION_ISA_64BIT | |
45 #define TARGET_MMX OPTION_ISA_MMX | |
46 #define TARGET_3DNOW OPTION_ISA_3DNOW | |
47 #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A | |
48 #define TARGET_SSE OPTION_ISA_SSE | |
49 #define TARGET_SSE2 OPTION_ISA_SSE2 | |
50 #define TARGET_SSE3 OPTION_ISA_SSE3 | |
51 #define TARGET_SSSE3 OPTION_ISA_SSSE3 | |
52 #define TARGET_SSE4_1 OPTION_ISA_SSE4_1 | |
53 #define TARGET_SSE4_2 OPTION_ISA_SSE4_2 | |
54 #define TARGET_AVX OPTION_ISA_AVX | |
55 #define TARGET_FMA OPTION_ISA_FMA | |
56 #define TARGET_SSE4A OPTION_ISA_SSE4A | |
57 #define TARGET_SSE5 OPTION_ISA_SSE5 | |
58 #define TARGET_ROUND OPTION_ISA_ROUND | |
59 #define TARGET_ABM OPTION_ISA_ABM | |
60 #define TARGET_POPCNT OPTION_ISA_POPCNT | |
61 #define TARGET_SAHF OPTION_ISA_SAHF | |
62 #define TARGET_AES OPTION_ISA_AES | |
63 #define TARGET_PCLMUL OPTION_ISA_PCLMUL | |
64 #define TARGET_CMPXCHG16B OPTION_ISA_CX16 | |
65 | |
66 | |
67 /* SSE5 and SSE4.1 define the same round instructions */ | |
68 #define OPTION_MASK_ISA_ROUND (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE5) | |
69 #define OPTION_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0) | |
70 | |
71 #include "config/vxworks-dummy.h" | |
72 | |
73 /* Algorithm to expand string function with. */ | |
74 enum stringop_alg | |
75 { | |
76 no_stringop, | |
77 libcall, | |
78 rep_prefix_1_byte, | |
79 rep_prefix_4_byte, | |
80 rep_prefix_8_byte, | |
81 loop_1_byte, | |
82 loop, | |
83 unrolled_loop | |
84 }; | |
85 | |
86 #define NAX_STRINGOP_ALGS 4 | |
87 | |
88 /* Specify what algorithm to use for stringops on known size. | |
89 When size is unknown, the UNKNOWN_SIZE alg is used. When size is | |
90 known at compile time or estimated via feedback, the SIZE array | |
91 is walked in order until MAX is greater then the estimate (or -1 | |
92 means infinity). Corresponding ALG is used then. | |
93 For example initializer: | |
94 {{256, loop}, {-1, rep_prefix_4_byte}} | |
95 will use loop for blocks smaller or equal to 256 bytes, rep prefix will | |
96 be used otherwise. */ | |
97 struct stringop_algs | |
98 { | |
99 const enum stringop_alg unknown_size; | |
100 const struct stringop_strategy { | |
101 const int max; | |
102 const enum stringop_alg alg; | |
103 } size [NAX_STRINGOP_ALGS]; | |
104 }; | |
105 | |
106 /* Define the specific costs for a given cpu */ | |
107 | |
108 struct processor_costs { | |
109 const int add; /* cost of an add instruction */ | |
110 const int lea; /* cost of a lea instruction */ | |
111 const int shift_var; /* variable shift costs */ | |
112 const int shift_const; /* constant shift costs */ | |
113 const int mult_init[5]; /* cost of starting a multiply | |
114 in QImode, HImode, SImode, DImode, TImode*/ | |
115 const int mult_bit; /* cost of multiply per each bit set */ | |
116 const int divide[5]; /* cost of a divide/mod | |
117 in QImode, HImode, SImode, DImode, TImode*/ | |
118 int movsx; /* The cost of movsx operation. */ | |
119 int movzx; /* The cost of movzx operation. */ | |
120 const int large_insn; /* insns larger than this cost more */ | |
121 const int move_ratio; /* The threshold of number of scalar | |
122 memory-to-memory move insns. */ | |
123 const int movzbl_load; /* cost of loading using movzbl */ | |
124 const int int_load[3]; /* cost of loading integer registers | |
125 in QImode, HImode and SImode relative | |
126 to reg-reg move (2). */ | |
127 const int int_store[3]; /* cost of storing integer register | |
128 in QImode, HImode and SImode */ | |
129 const int fp_move; /* cost of reg,reg fld/fst */ | |
130 const int fp_load[3]; /* cost of loading FP register | |
131 in SFmode, DFmode and XFmode */ | |
132 const int fp_store[3]; /* cost of storing FP register | |
133 in SFmode, DFmode and XFmode */ | |
134 const int mmx_move; /* cost of moving MMX register. */ | |
135 const int mmx_load[2]; /* cost of loading MMX register | |
136 in SImode and DImode */ | |
137 const int mmx_store[2]; /* cost of storing MMX register | |
138 in SImode and DImode */ | |
139 const int sse_move; /* cost of moving SSE register. */ | |
140 const int sse_load[3]; /* cost of loading SSE register | |
141 in SImode, DImode and TImode*/ | |
142 const int sse_store[3]; /* cost of storing SSE register | |
143 in SImode, DImode and TImode*/ | |
144 const int mmxsse_to_integer; /* cost of moving mmxsse register to | |
145 integer and vice versa. */ | |
146 const int l1_cache_size; /* size of l1 cache, in kilobytes. */ | |
147 const int l2_cache_size; /* size of l2 cache, in kilobytes. */ | |
148 const int prefetch_block; /* bytes moved to cache for prefetch. */ | |
149 const int simultaneous_prefetches; /* number of parallel prefetch | |
150 operations. */ | |
151 const int branch_cost; /* Default value for BRANCH_COST. */ | |
152 const int fadd; /* cost of FADD and FSUB instructions. */ | |
153 const int fmul; /* cost of FMUL instruction. */ | |
154 const int fdiv; /* cost of FDIV instruction. */ | |
155 const int fabs; /* cost of FABS instruction. */ | |
156 const int fchs; /* cost of FCHS instruction. */ | |
157 const int fsqrt; /* cost of FSQRT instruction. */ | |
158 /* Specify what algorithm | |
159 to use for stringops on unknown size. */ | |
160 struct stringop_algs memcpy[2], memset[2]; | |
161 const int scalar_stmt_cost; /* Cost of any scalar operation, excluding | |
162 load and store. */ | |
163 const int scalar_load_cost; /* Cost of scalar load. */ | |
164 const int scalar_store_cost; /* Cost of scalar store. */ | |
165 const int vec_stmt_cost; /* Cost of any vector operation, excluding | |
166 load, store, vector-to-scalar and | |
167 scalar-to-vector operation. */ | |
168 const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */ | |
169 const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */ | |
170 const int vec_align_load_cost; /* Cost of aligned vector load. */ | |
171 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ | |
172 const int vec_store_cost; /* Cost of vector store. */ | |
173 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer | |
174 cost model. */ | |
175 const int cond_not_taken_branch_cost;/* Cost of not taken branch for | |
176 vectorizer cost model. */ | |
177 }; | |
178 | |
179 extern const struct processor_costs *ix86_cost; | |
180 extern const struct processor_costs ix86_size_cost; | |
181 | |
182 #define ix86_cur_cost() \ | |
183 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) | |
184 | |
185 /* Macros used in the machine description to test the flags. */ | |
186 | |
187 /* configure can arrange to make this 2, to force a 486. */ | |
188 | |
189 #ifndef TARGET_CPU_DEFAULT | |
190 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic | |
191 #endif | |
192 | |
193 #ifndef TARGET_FPMATH_DEFAULT | |
194 #define TARGET_FPMATH_DEFAULT \ | |
195 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) | |
196 #endif | |
197 | |
198 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS | |
199 | |
200 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a | |
201 compile-time constant. */ | |
202 #ifdef IN_LIBGCC2 | |
203 #undef TARGET_64BIT | |
204 #ifdef __x86_64__ | |
205 #define TARGET_64BIT 1 | |
206 #else | |
207 #define TARGET_64BIT 0 | |
208 #endif | |
209 #else | |
210 #ifndef TARGET_BI_ARCH | |
211 #undef TARGET_64BIT | |
212 #if TARGET_64BIT_DEFAULT | |
213 #define TARGET_64BIT 1 | |
214 #else | |
215 #define TARGET_64BIT 0 | |
216 #endif | |
217 #endif | |
218 #endif | |
219 | |
220 #define HAS_LONG_COND_BRANCH 1 | |
221 #define HAS_LONG_UNCOND_BRANCH 1 | |
222 | |
223 #define TARGET_386 (ix86_tune == PROCESSOR_I386) | |
224 #define TARGET_486 (ix86_tune == PROCESSOR_I486) | |
225 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) | |
226 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) | |
227 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) | |
228 #define TARGET_K6 (ix86_tune == PROCESSOR_K6) | |
229 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) | |
230 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) | |
231 #define TARGET_K8 (ix86_tune == PROCESSOR_K8) | |
232 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) | |
233 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) | |
234 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) | |
235 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32) | |
236 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64) | |
237 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64) | |
238 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) | |
239 | |
240 /* Feature tests against the various tunings. */ | |
241 enum ix86_tune_indices { | |
242 X86_TUNE_USE_LEAVE, | |
243 X86_TUNE_PUSH_MEMORY, | |
244 X86_TUNE_ZERO_EXTEND_WITH_AND, | |
245 X86_TUNE_UNROLL_STRLEN, | |
246 X86_TUNE_DEEP_BRANCH_PREDICTION, | |
247 X86_TUNE_BRANCH_PREDICTION_HINTS, | |
248 X86_TUNE_DOUBLE_WITH_ADD, | |
249 X86_TUNE_USE_SAHF, | |
250 X86_TUNE_MOVX, | |
251 X86_TUNE_PARTIAL_REG_STALL, | |
252 X86_TUNE_PARTIAL_FLAG_REG_STALL, | |
253 X86_TUNE_USE_HIMODE_FIOP, | |
254 X86_TUNE_USE_SIMODE_FIOP, | |
255 X86_TUNE_USE_MOV0, | |
256 X86_TUNE_USE_CLTD, | |
257 X86_TUNE_USE_XCHGB, | |
258 X86_TUNE_SPLIT_LONG_MOVES, | |
259 X86_TUNE_READ_MODIFY_WRITE, | |
260 X86_TUNE_READ_MODIFY, | |
261 X86_TUNE_PROMOTE_QIMODE, | |
262 X86_TUNE_FAST_PREFIX, | |
263 X86_TUNE_SINGLE_STRINGOP, | |
264 X86_TUNE_QIMODE_MATH, | |
265 X86_TUNE_HIMODE_MATH, | |
266 X86_TUNE_PROMOTE_QI_REGS, | |
267 X86_TUNE_PROMOTE_HI_REGS, | |
268 X86_TUNE_ADD_ESP_4, | |
269 X86_TUNE_ADD_ESP_8, | |
270 X86_TUNE_SUB_ESP_4, | |
271 X86_TUNE_SUB_ESP_8, | |
272 X86_TUNE_INTEGER_DFMODE_MOVES, | |
273 X86_TUNE_PARTIAL_REG_DEPENDENCY, | |
274 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, | |
275 X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL, | |
276 X86_TUNE_SSE_SPLIT_REGS, | |
277 X86_TUNE_SSE_TYPELESS_STORES, | |
278 X86_TUNE_SSE_LOAD0_BY_PXOR, | |
279 X86_TUNE_MEMORY_MISMATCH_STALL, | |
280 X86_TUNE_PROLOGUE_USING_MOVE, | |
281 X86_TUNE_EPILOGUE_USING_MOVE, | |
282 X86_TUNE_SHIFT1, | |
283 X86_TUNE_USE_FFREEP, | |
284 X86_TUNE_INTER_UNIT_MOVES, | |
285 X86_TUNE_INTER_UNIT_CONVERSIONS, | |
286 X86_TUNE_FOUR_JUMP_LIMIT, | |
287 X86_TUNE_SCHEDULE, | |
288 X86_TUNE_USE_BT, | |
289 X86_TUNE_USE_INCDEC, | |
290 X86_TUNE_PAD_RETURNS, | |
291 X86_TUNE_EXT_80387_CONSTANTS, | |
292 X86_TUNE_SHORTEN_X87_SSE, | |
293 X86_TUNE_AVOID_VECTOR_DECODE, | |
294 X86_TUNE_PROMOTE_HIMODE_IMUL, | |
295 X86_TUNE_SLOW_IMUL_IMM32_MEM, | |
296 X86_TUNE_SLOW_IMUL_IMM8, | |
297 X86_TUNE_MOVE_M1_VIA_OR, | |
298 X86_TUNE_NOT_UNPAIRABLE, | |
299 X86_TUNE_NOT_VECTORMODE, | |
300 X86_TUNE_USE_VECTOR_FP_CONVERTS, | |
301 X86_TUNE_USE_VECTOR_CONVERTS, | |
302 X86_TUNE_FUSE_CMP_AND_BRANCH, | |
303 | |
304 X86_TUNE_LAST | |
305 }; | |
306 | |
307 extern unsigned char ix86_tune_features[X86_TUNE_LAST]; | |
308 | |
309 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] | |
310 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] | |
311 #define TARGET_ZERO_EXTEND_WITH_AND \ | |
312 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] | |
313 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] | |
314 #define TARGET_DEEP_BRANCH_PREDICTION \ | |
315 ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION] | |
316 #define TARGET_BRANCH_PREDICTION_HINTS \ | |
317 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] | |
318 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] | |
319 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] | |
320 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] | |
321 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] | |
322 #define TARGET_PARTIAL_FLAG_REG_STALL \ | |
323 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] | |
324 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] | |
325 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] | |
326 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] | |
327 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] | |
328 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] | |
329 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] | |
330 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] | |
331 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] | |
332 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] | |
333 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] | |
334 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] | |
335 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] | |
336 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] | |
337 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] | |
338 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] | |
339 #define TARGET_ADD_ESP_4 ix86_tune_features[X86_TUNE_ADD_ESP_4] | |
340 #define TARGET_ADD_ESP_8 ix86_tune_features[X86_TUNE_ADD_ESP_8] | |
341 #define TARGET_SUB_ESP_4 ix86_tune_features[X86_TUNE_SUB_ESP_4] | |
342 #define TARGET_SUB_ESP_8 ix86_tune_features[X86_TUNE_SUB_ESP_8] | |
343 #define TARGET_INTEGER_DFMODE_MOVES \ | |
344 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] | |
345 #define TARGET_PARTIAL_REG_DEPENDENCY \ | |
346 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] | |
347 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ | |
348 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] | |
349 #define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \ | |
350 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL] | |
351 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] | |
352 #define TARGET_SSE_TYPELESS_STORES \ | |
353 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] | |
354 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] | |
355 #define TARGET_MEMORY_MISMATCH_STALL \ | |
356 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] | |
357 #define TARGET_PROLOGUE_USING_MOVE \ | |
358 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] | |
359 #define TARGET_EPILOGUE_USING_MOVE \ | |
360 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] | |
361 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] | |
362 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] | |
363 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES] | |
364 #define TARGET_INTER_UNIT_CONVERSIONS\ | |
365 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] | |
366 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] | |
367 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] | |
368 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] | |
369 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] | |
370 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] | |
371 #define TARGET_EXT_80387_CONSTANTS \ | |
372 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] | |
373 #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE] | |
374 #define TARGET_AVOID_VECTOR_DECODE \ | |
375 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] | |
376 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ | |
377 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] | |
378 #define TARGET_SLOW_IMUL_IMM32_MEM \ | |
379 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] | |
380 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] | |
381 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] | |
382 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] | |
383 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] | |
384 #define TARGET_USE_VECTOR_FP_CONVERTS \ | |
385 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] | |
386 #define TARGET_USE_VECTOR_CONVERTS \ | |
387 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] | |
388 #define TARGET_FUSE_CMP_AND_BRANCH \ | |
389 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH] | |
390 | |
391 /* Feature tests against the various architecture variations. */ | |
392 enum ix86_arch_indices { | |
393 X86_ARCH_CMOVE, /* || TARGET_SSE */ | |
394 X86_ARCH_CMPXCHG, | |
395 X86_ARCH_CMPXCHG8B, | |
396 X86_ARCH_XADD, | |
397 X86_ARCH_BSWAP, | |
398 | |
399 X86_ARCH_LAST | |
400 }; | |
401 | |
402 extern unsigned char ix86_arch_features[X86_ARCH_LAST]; | |
403 | |
404 #define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE] | |
405 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] | |
406 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] | |
407 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] | |
408 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] | |
409 | |
410 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) | |
411 | |
412 extern int x86_prefetch_sse; | |
413 | |
414 #define TARGET_PREFETCH_SSE x86_prefetch_sse | |
415 | |
416 #define ASSEMBLER_DIALECT (ix86_asm_dialect) | |
417 | |
418 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) | |
419 #define TARGET_MIX_SSE_I387 \ | |
420 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) | |
421 | |
422 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) | |
423 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) | |
424 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) | |
425 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN) | |
426 | |
427 extern int ix86_isa_flags; | |
428 | |
429 #ifndef TARGET_64BIT_DEFAULT | |
430 #define TARGET_64BIT_DEFAULT 0 | |
431 #endif | |
432 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT | |
433 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 | |
434 #endif | |
435 | |
436 /* Fence to use after loop using storent. */ | |
437 | |
438 extern tree x86_mfence; | |
439 #define FENCE_FOLLOWING_MOVNT x86_mfence | |
440 | |
441 /* Once GDB has been enhanced to deal with functions without frame | |
442 pointers, we can change this to allow for elimination of | |
443 the frame pointer in leaf functions. */ | |
444 #define TARGET_DEFAULT 0 | |
445 | |
446 /* Extra bits to force. */ | |
447 #define TARGET_SUBTARGET_DEFAULT 0 | |
448 #define TARGET_SUBTARGET_ISA_DEFAULT 0 | |
449 | |
450 /* Extra bits to force on w/ 32-bit mode. */ | |
451 #define TARGET_SUBTARGET32_DEFAULT 0 | |
452 #define TARGET_SUBTARGET32_ISA_DEFAULT 0 | |
453 | |
454 /* Extra bits to force on w/ 64-bit mode. */ | |
455 #define TARGET_SUBTARGET64_DEFAULT 0 | |
456 #define TARGET_SUBTARGET64_ISA_DEFAULT 0 | |
457 | |
458 /* This is not really a target flag, but is done this way so that | |
459 it's analogous to similar code for Mach-O on PowerPC. darwin.h | |
460 redefines this to 1. */ | |
461 #define TARGET_MACHO 0 | |
462 | |
463 /* Likewise, for the Windows 64-bit ABI. */ | |
464 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) | |
465 | |
466 /* Available call abi. */ | |
467 enum calling_abi | |
468 { | |
469 SYSV_ABI = 0, | |
470 MS_ABI = 1 | |
471 }; | |
472 | |
473 /* The default abi form used by target. */ | |
474 #define DEFAULT_ABI SYSV_ABI | |
475 | |
476 /* Subtargets may reset this to 1 in order to enable 96-bit long double | |
477 with the rounding mode forced to 53 bits. */ | |
478 #define TARGET_96_ROUND_53_LONG_DOUBLE 0 | |
479 | |
480 /* Sometimes certain combinations of command options do not make | |
481 sense on a particular target machine. You can define a macro | |
482 `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
483 defined, is executed once just after all the command options have | |
484 been parsed. | |
485 | |
486 Don't use this macro to turn on various extra optimizations for | |
487 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ | |
488 | |
489 #define OVERRIDE_OPTIONS override_options (true) | |
490 | |
491 /* Define this to change the optimizations performed by default. */ | |
492 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ | |
493 optimization_options ((LEVEL), (SIZE)) | |
494 | |
495 /* -march=native handling only makes sense with compiler running on | |
496 an x86 or x86_64 chip. If changing this condition, also change | |
497 the condition in driver-i386.c. */ | |
498 #if defined(__i386__) || defined(__x86_64__) | |
499 /* In driver-i386.c. */ | |
500 extern const char *host_detect_local_cpu (int argc, const char **argv); | |
501 #define EXTRA_SPEC_FUNCTIONS \ | |
502 { "local_cpu_detect", host_detect_local_cpu }, | |
503 #define HAVE_LOCAL_CPU_DETECT | |
504 #endif | |
505 | |
506 #if TARGET_64BIT_DEFAULT | |
507 #define OPT_ARCH64 "!m32" | |
508 #define OPT_ARCH32 "m32" | |
509 #else | |
510 #define OPT_ARCH64 "m64" | |
511 #define OPT_ARCH32 "!m64" | |
512 #endif | |
513 | |
514 /* Support for configure-time defaults of some command line options. | |
515 The order here is important so that -march doesn't squash the | |
516 tune or cpu values. */ | |
517 #define OPTION_DEFAULT_SPECS \ | |
518 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ | |
519 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
520 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
521 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ | |
522 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
523 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ | |
524 {"arch", "%{!march=*:-march=%(VALUE)}"}, \ | |
525 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ | |
526 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, | |
527 | |
528 /* Specs for the compiler proper */ | |
529 | |
530 #ifndef CC1_CPU_SPEC | |
531 #define CC1_CPU_SPEC_1 "\ | |
532 %{mcpu=*:-mtune=%* \ | |
533 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n} \ | |
534 %<mcpu=* \ | |
535 %{mintel-syntax:-masm=intel \ | |
536 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ | |
537 %{mno-intel-syntax:-masm=att \ | |
538 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" | |
539 | |
540 #ifndef HAVE_LOCAL_CPU_DETECT | |
541 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 | |
542 #else | |
543 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ | |
544 "%{march=native:%<march=native %:local_cpu_detect(arch) \ | |
545 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \ | |
546 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
547 #endif | |
548 #endif | |
549 | |
550 /* Target CPU builtins. */ | |
551 #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () | |
552 | |
553 /* Target Pragmas. */ | |
554 #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () | |
555 | |
556 enum target_cpu_default | |
557 { | |
558 TARGET_CPU_DEFAULT_generic = 0, | |
559 | |
560 TARGET_CPU_DEFAULT_i386, | |
561 TARGET_CPU_DEFAULT_i486, | |
562 TARGET_CPU_DEFAULT_pentium, | |
563 TARGET_CPU_DEFAULT_pentium_mmx, | |
564 TARGET_CPU_DEFAULT_pentiumpro, | |
565 TARGET_CPU_DEFAULT_pentium2, | |
566 TARGET_CPU_DEFAULT_pentium3, | |
567 TARGET_CPU_DEFAULT_pentium4, | |
568 TARGET_CPU_DEFAULT_pentium_m, | |
569 TARGET_CPU_DEFAULT_prescott, | |
570 TARGET_CPU_DEFAULT_nocona, | |
571 TARGET_CPU_DEFAULT_core2, | |
572 | |
573 TARGET_CPU_DEFAULT_geode, | |
574 TARGET_CPU_DEFAULT_k6, | |
575 TARGET_CPU_DEFAULT_k6_2, | |
576 TARGET_CPU_DEFAULT_k6_3, | |
577 TARGET_CPU_DEFAULT_athlon, | |
578 TARGET_CPU_DEFAULT_athlon_sse, | |
579 TARGET_CPU_DEFAULT_k8, | |
580 TARGET_CPU_DEFAULT_amdfam10, | |
581 | |
582 TARGET_CPU_DEFAULT_max | |
583 }; | |
584 | |
585 #ifndef CC1_SPEC | |
586 #define CC1_SPEC "%(cc1_cpu) " | |
587 #endif | |
588 | |
589 /* This macro defines names of additional specifications to put in the | |
590 specs that can be used in various specifications like CC1_SPEC. Its | |
591 definition is an initializer with a subgrouping for each command option. | |
592 | |
593 Each subgrouping contains a string constant, that defines the | |
594 specification name, and a string constant that used by the GCC driver | |
595 program. | |
596 | |
597 Do not define this macro if it does not need to do anything. */ | |
598 | |
599 #ifndef SUBTARGET_EXTRA_SPECS | |
600 #define SUBTARGET_EXTRA_SPECS | |
601 #endif | |
602 | |
603 #define EXTRA_SPECS \ | |
604 { "cc1_cpu", CC1_CPU_SPEC }, \ | |
605 SUBTARGET_EXTRA_SPECS | |
606 | |
607 | |
608 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the | |
609 FPU, assume that the fpcw is set to extended precision; when using | |
610 only SSE, rounding is correct; when using both SSE and the FPU, | |
611 the rounding precision is indeterminate, since either may be chosen | |
612 apparently at random. */ | |
613 #define TARGET_FLT_EVAL_METHOD \ | |
614 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) | |
615 | |
616 /* target machine storage layout */ | |
617 | |
618 #define SHORT_TYPE_SIZE 16 | |
619 #define INT_TYPE_SIZE 32 | |
620 #define FLOAT_TYPE_SIZE 32 | |
621 #define LONG_TYPE_SIZE BITS_PER_WORD | |
622 #define DOUBLE_TYPE_SIZE 64 | |
623 #define LONG_LONG_TYPE_SIZE 64 | |
624 #define LONG_DOUBLE_TYPE_SIZE 80 | |
625 | |
626 #define WIDEST_HARDWARE_FP_SIZE LONG_DOUBLE_TYPE_SIZE | |
627 | |
628 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT | |
629 #define MAX_BITS_PER_WORD 64 | |
630 #else | |
631 #define MAX_BITS_PER_WORD 32 | |
632 #endif | |
633 | |
634 /* Define this if most significant byte of a word is the lowest numbered. */ | |
635 /* That is true on the 80386. */ | |
636 | |
637 #define BITS_BIG_ENDIAN 0 | |
638 | |
639 /* Define this if most significant byte of a word is the lowest numbered. */ | |
640 /* That is not true on the 80386. */ | |
641 #define BYTES_BIG_ENDIAN 0 | |
642 | |
643 /* Define this if most significant word of a multiword number is the lowest | |
644 numbered. */ | |
645 /* Not true for 80386 */ | |
646 #define WORDS_BIG_ENDIAN 0 | |
647 | |
648 /* Width of a word, in units (bytes). */ | |
649 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) | |
650 #ifdef IN_LIBGCC2 | |
651 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) | |
652 #else | |
653 #define MIN_UNITS_PER_WORD 4 | |
654 #endif | |
655 | |
656 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
657 #define PARM_BOUNDARY BITS_PER_WORD | |
658 | |
659 /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
660 #define STACK_BOUNDARY \ | |
661 (TARGET_64BIT && DEFAULT_ABI == MS_ABI ? 128 : BITS_PER_WORD) | |
662 | |
663 /* Stack boundary of the main function guaranteed by OS. */ | |
664 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) | |
665 | |
666 /* Minimum stack boundary. */ | |
667 #define MIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) | |
668 | |
669 /* Boundary (in *bits*) on which the stack pointer prefers to be | |
670 aligned; the compiler cannot rely on having this alignment. */ | |
671 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary | |
672 | |
673 /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for | |
674 both 32bit and 64bit, to support codes that need 128 bit stack | |
675 alignment for SSE instructions, but can't realign the stack. */ | |
676 #define PREFERRED_STACK_BOUNDARY_DEFAULT 128 | |
677 | |
678 /* 1 if -mstackrealign should be turned on by default. It will | |
679 generate an alternate prologue and epilogue that realigns the | |
680 runtime stack if nessary. This supports mixing codes that keep a | |
681 4-byte aligned stack, as specified by i386 psABI, with codes that | |
682 need a 16-byte aligned stack, as required by SSE instructions. If | |
683 STACK_REALIGN_DEFAULT is 1 and PREFERRED_STACK_BOUNDARY_DEFAULT is | |
684 128, stacks for all functions may be realigned. */ | |
685 #define STACK_REALIGN_DEFAULT 0 | |
686 | |
687 /* Boundary (in *bits*) on which the incoming stack is aligned. */ | |
688 #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary | |
689 | |
690 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is | |
691 mandatory for the 64-bit ABI, and may or may not be true for other | |
692 operating systems. */ | |
693 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT | |
694 | |
695 /* Minimum allocation boundary for the code of a function. */ | |
696 #define FUNCTION_BOUNDARY 8 | |
697 | |
698 /* C++ stores the virtual bit in the lowest bit of function pointers. */ | |
699 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn | |
700 | |
701 /* Alignment of field after `int : 0' in a structure. */ | |
702 | |
703 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD | |
704 | |
705 /* Minimum size in bits of the largest boundary to which any | |
706 and all fundamental data types supported by the hardware | |
707 might need to be aligned. No data type wants to be aligned | |
708 rounder than this. | |
709 | |
710 Pentium+ prefers DFmode values to be aligned to 64 bit boundary | |
711 and Pentium Pro XFmode values at 128 bit boundaries. */ | |
712 | |
713 #define BIGGEST_ALIGNMENT (TARGET_AVX ? 256: 128) | |
714 | |
715 /* Maximum stack alignment. */ | |
716 #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT | |
717 | |
718 /* Alignment value for attribute ((aligned)). It is a constant since | |
719 it is the part of the ABI. We shouldn't change it with -mavx. */ | |
720 #define ATTRIBUTE_ALIGNED_VALUE 128 | |
721 | |
722 /* Decide whether a variable of mode MODE should be 128 bit aligned. */ | |
723 #define ALIGN_MODE_128(MODE) \ | |
724 ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) | |
725 | |
726 /* The published ABIs say that doubles should be aligned on word | |
727 boundaries, so lower the alignment for structure fields unless | |
728 -malign-double is set. */ | |
729 | |
730 /* ??? Blah -- this macro is used directly by libobjc. Since it | |
731 supports no vector modes, cut out the complexity and fall back | |
732 on BIGGEST_FIELD_ALIGNMENT. */ | |
733 #ifdef IN_TARGET_LIBS | |
734 #ifdef __x86_64__ | |
735 #define BIGGEST_FIELD_ALIGNMENT 128 | |
736 #else | |
737 #define BIGGEST_FIELD_ALIGNMENT 32 | |
738 #endif | |
739 #else | |
740 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ | |
741 x86_field_alignment (FIELD, COMPUTED) | |
742 #endif | |
743 | |
744 /* If defined, a C expression to compute the alignment given to a | |
745 constant that is being placed in memory. EXP is the constant | |
746 and ALIGN is the alignment that the object would ordinarily have. | |
747 The value of this macro is used instead of that alignment to align | |
748 the object. | |
749 | |
750 If this macro is not defined, then ALIGN is used. | |
751 | |
752 The typical use of this macro is to increase alignment for string | |
753 constants to be word aligned so that `strcpy' calls that copy | |
754 constants can be done inline. */ | |
755 | |
756 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) | |
757 | |
758 /* If defined, a C expression to compute the alignment for a static | |
759 variable. TYPE is the data type, and ALIGN is the alignment that | |
760 the object would ordinarily have. The value of this macro is used | |
761 instead of that alignment to align the object. | |
762 | |
763 If this macro is not defined, then ALIGN is used. | |
764 | |
765 One use of this macro is to increase alignment of medium-size | |
766 data to make it all fit in fewer cache lines. Another is to | |
767 cause character arrays to be word-aligned so that `strcpy' calls | |
768 that copy constants to character arrays can be done inline. */ | |
769 | |
770 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) | |
771 | |
772 /* If defined, a C expression to compute the alignment for a local | |
773 variable. TYPE is the data type, and ALIGN is the alignment that | |
774 the object would ordinarily have. The value of this macro is used | |
775 instead of that alignment to align the object. | |
776 | |
777 If this macro is not defined, then ALIGN is used. | |
778 | |
779 One use of this macro is to increase alignment of medium-size | |
780 data to make it all fit in fewer cache lines. */ | |
781 | |
782 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
783 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) | |
784 | |
785 /* If defined, a C expression to compute the alignment for stack slot. | |
786 TYPE is the data type, MODE is the widest mode available, and ALIGN | |
787 is the alignment that the slot would ordinarily have. The value of | |
788 this macro is used instead of that alignment to align the slot. | |
789 | |
790 If this macro is not defined, then ALIGN is used when TYPE is NULL, | |
791 Otherwise, LOCAL_ALIGNMENT will be used. | |
792 | |
793 One use of this macro is to set alignment of stack slot to the | |
794 maximum alignment of all possible modes which the slot may have. */ | |
795 | |
796 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ | |
797 ix86_local_alignment ((TYPE), (MODE), (ALIGN)) | |
798 | |
799 /* If defined, a C expression to compute the alignment for a local | |
800 variable DECL. | |
801 | |
802 If this macro is not defined, then | |
803 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. | |
804 | |
805 One use of this macro is to increase alignment of medium-size | |
806 data to make it all fit in fewer cache lines. */ | |
807 | |
808 #define LOCAL_DECL_ALIGNMENT(DECL) \ | |
809 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) | |
810 | |
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811 /* If defined, a C expression to compute the minimum required alignment |
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812 for dynamic stack realignment purposes for EXP (a TYPE or DECL), |
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813 MODE, assuming normal alignment ALIGN. |
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814 |
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815 If this macro is not defined, then (ALIGN) will be used. */ |
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816 |
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817 #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ |
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818 ix86_minimum_alignment (EXP, MODE, ALIGN) |
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819 |
0 | 820 |
821 /* If defined, a C expression that gives the alignment boundary, in | |
822 bits, of an argument with the specified mode and type. If it is | |
823 not defined, `PARM_BOUNDARY' is used for all arguments. */ | |
824 | |
825 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ | |
826 ix86_function_arg_boundary ((MODE), (TYPE)) | |
827 | |
828 /* Set this nonzero if move instructions will actually fail to work | |
829 when given unaligned data. */ | |
830 #define STRICT_ALIGNMENT 0 | |
831 | |
832 /* If bit field type is int, don't let it cross an int, | |
833 and give entire struct the alignment of an int. */ | |
834 /* Required on the 386 since it doesn't have bit-field insns. */ | |
835 #define PCC_BITFIELD_TYPE_MATTERS 1 | |
836 | |
837 /* Standard register usage. */ | |
838 | |
839 /* This processor has special stack-like registers. See reg-stack.c | |
840 for details. */ | |
841 | |
842 #define STACK_REGS | |
843 | |
844 #define IS_STACK_MODE(MODE) \ | |
845 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \ | |
846 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \ | |
847 || (MODE) == XFmode) | |
848 | |
849 /* Number of actual hardware registers. | |
850 The hardware registers are assigned numbers for the compiler | |
851 from 0 to just below FIRST_PSEUDO_REGISTER. | |
852 All registers that the compiler knows about must be given numbers, | |
853 even those that are not normally considered general registers. | |
854 | |
855 In the 80386 we give the 8 general purpose registers the numbers 0-7. | |
856 We number the floating point registers 8-15. | |
857 Note that registers 0-7 can be accessed as a short or int, | |
858 while only 0-3 may be used with byte `mov' instructions. | |
859 | |
860 Reg 16 does not correspond to any hardware register, but instead | |
861 appears in the RTL as an argument pointer prior to reload, and is | |
862 eliminated during reloading in favor of either the stack or frame | |
863 pointer. */ | |
864 | |
865 #define FIRST_PSEUDO_REGISTER 53 | |
866 | |
867 /* Number of hardware registers that go into the DWARF-2 unwind info. | |
868 If not defined, equals FIRST_PSEUDO_REGISTER. */ | |
869 | |
870 #define DWARF_FRAME_REGISTERS 17 | |
871 | |
872 /* 1 for registers that have pervasive standard uses | |
873 and are not available for the register allocator. | |
874 On the 80386, the stack pointer is such, as is the arg pointer. | |
875 | |
876 The value is zero if the register is not fixed on either 32 or | |
877 64 bit targets, one if the register if fixed on both 32 and 64 | |
878 bit targets, two if it is only fixed on 32bit targets and three | |
879 if its only fixed on 64bit targets. | |
880 Proper values are computed in the CONDITIONAL_REGISTER_USAGE. | |
881 */ | |
882 #define FIXED_REGISTERS \ | |
883 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
884 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
885 /*arg,flags,fpsr,fpcr,frame*/ \ | |
886 1, 1, 1, 1, 1, \ | |
887 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ | |
888 0, 0, 0, 0, 0, 0, 0, 0, \ | |
889 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ | |
890 0, 0, 0, 0, 0, 0, 0, 0, \ | |
891 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
892 2, 2, 2, 2, 2, 2, 2, 2, \ | |
893 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ | |
894 2, 2, 2, 2, 2, 2, 2, 2 } | |
895 | |
896 | |
897 /* 1 for registers not available across function calls. | |
898 These must include the FIXED_REGISTERS and also any | |
899 registers that can be used without being saved. | |
900 The latter must include the registers where values are returned | |
901 and the register where structure-value addresses are passed. | |
902 Aside from that, you can include as many other registers as you like. | |
903 | |
904 The value is zero if the register is not call used on either 32 or | |
905 64 bit targets, one if the register if call used on both 32 and 64 | |
906 bit targets, two if it is only call used on 32bit targets and three | |
907 if its only call used on 64bit targets. | |
908 Proper values are computed in the CONDITIONAL_REGISTER_USAGE. | |
909 */ | |
910 #define CALL_USED_REGISTERS \ | |
911 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ | |
912 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
913 /*arg,flags,fpsr,fpcr,frame*/ \ | |
914 1, 1, 1, 1, 1, \ | |
915 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ | |
916 1, 1, 1, 1, 1, 1, 1, 1, \ | |
917 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ | |
918 1, 1, 1, 1, 1, 1, 1, 1, \ | |
919 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ | |
920 1, 1, 1, 1, 2, 2, 2, 2, \ | |
921 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ | |
922 1, 1, 1, 1, 1, 1, 1, 1 } | |
923 | |
924 /* Order in which to allocate registers. Each register must be | |
925 listed once, even those in FIXED_REGISTERS. List frame pointer | |
926 late and fixed registers last. Note that, in general, we prefer | |
927 registers listed in CALL_USED_REGISTERS, keeping the others | |
928 available for storage of persistent values. | |
929 | |
930 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, | |
931 so this is just empty initializer for array. */ | |
932 | |
933 #define REG_ALLOC_ORDER \ | |
934 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ | |
935 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ | |
936 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
937 48, 49, 50, 51, 52 } | |
938 | |
939 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order | |
940 to be rearranged based on a particular function. When using sse math, | |
941 we want to allocate SSE before x87 registers and vice versa. */ | |
942 | |
943 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () | |
944 | |
945 | |
946 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) | |
947 | |
948 /* Macro to conditionally modify fixed_regs/call_used_regs. */ | |
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949 #define CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage () |
0 | 950 |
951 /* Return number of consecutive hard regs needed starting at reg REGNO | |
952 to hold something of mode MODE. | |
953 This is ordinarily the length in words of a value of mode MODE | |
954 but can be less for certain modes in special long registers. | |
955 | |
956 Actually there are no two word move instructions for consecutive | |
957 registers. And only registers 0-3 may have mov byte instructions | |
958 applied to them. | |
959 */ | |
960 | |
961 #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
962 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ | |
963 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ | |
964 : ((MODE) == XFmode \ | |
965 ? (TARGET_64BIT ? 2 : 3) \ | |
966 : (MODE) == XCmode \ | |
967 ? (TARGET_64BIT ? 4 : 6) \ | |
968 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) | |
969 | |
970 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ | |
971 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \ | |
972 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ | |
973 ? 0 \ | |
974 : ((MODE) == XFmode || (MODE) == XCmode)) \ | |
975 : 0) | |
976 | |
977 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) | |
978 | |
979 #define VALID_AVX256_REG_MODE(MODE) \ | |
980 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ | |
981 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode) | |
982 | |
983 #define VALID_SSE2_REG_MODE(MODE) \ | |
984 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ | |
985 || (MODE) == V2DImode || (MODE) == DFmode) | |
986 | |
987 #define VALID_SSE_REG_MODE(MODE) \ | |
988 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \ | |
989 || (MODE) == SFmode || (MODE) == TFmode) | |
990 | |
991 #define VALID_MMX_REG_MODE_3DNOW(MODE) \ | |
992 ((MODE) == V2SFmode || (MODE) == SFmode) | |
993 | |
994 #define VALID_MMX_REG_MODE(MODE) \ | |
995 ((MODE == V1DImode) || (MODE) == DImode \ | |
996 || (MODE) == V2SImode || (MODE) == SImode \ | |
997 || (MODE) == V4HImode || (MODE) == V8QImode) | |
998 | |
999 /* ??? No autovectorization into MMX or 3DNOW until we can reliably | |
1000 place emms and femms instructions. | |
1001 FIXME: AVX has 32byte floating point vector operations and 16byte | |
1002 integer vector operations. But vectorizer doesn't support | |
1003 different sizes for integer and floating point vectors. We limit | |
1004 vector size to 16byte. */ | |
1005 #define UNITS_PER_SIMD_WORD(MODE) \ | |
1006 (TARGET_AVX ? (((MODE) == DFmode || (MODE) == SFmode) ? 16 : 16) \ | |
1007 : (TARGET_SSE ? 16 : UNITS_PER_WORD)) | |
1008 | |
1009 #define VALID_DFP_MODE_P(MODE) \ | |
1010 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) | |
1011 | |
1012 #define VALID_FP_MODE_P(MODE) \ | |
1013 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ | |
1014 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ | |
1015 | |
1016 #define VALID_INT_MODE_P(MODE) \ | |
1017 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ | |
1018 || (MODE) == DImode \ | |
1019 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ | |
1020 || (MODE) == CDImode \ | |
1021 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ | |
1022 || (MODE) == TFmode || (MODE) == TCmode))) | |
1023 | |
1024 /* Return true for modes passed in SSE registers. */ | |
1025 #define SSE_REG_MODE_P(MODE) \ | |
1026 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \ | |
1027 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \ | |
1028 || (MODE) == V4SFmode || (MODE) == V4SImode || (MODE) == V32QImode \ | |
1029 || (MODE) == V16HImode || (MODE) == V8SImode || (MODE) == V4DImode \ | |
1030 || (MODE) == V8SFmode || (MODE) == V4DFmode) | |
1031 | |
1032 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ | |
1033 | |
1034 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
1035 ix86_hard_regno_mode_ok ((REGNO), (MODE)) | |
1036 | |
1037 /* Value is 1 if it is a good idea to tie two pseudo registers | |
1038 when one has mode MODE1 and one has mode MODE2. | |
1039 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
1040 for any hard reg, then this must be 0 for correct output. */ | |
1041 | |
1042 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) | |
1043 | |
1044 /* It is possible to write patterns to move flags; but until someone | |
1045 does it, */ | |
1046 #define AVOID_CCMODE_COPIES | |
1047 | |
1048 /* Specify the modes required to caller save a given hard regno. | |
1049 We do this on i386 to prevent flags from being saved at all. | |
1050 | |
1051 Kill any attempts to combine saving of modes. */ | |
1052 | |
1053 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ | |
1054 (CC_REGNO_P (REGNO) ? VOIDmode \ | |
1055 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ | |
1056 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ | |
1057 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ | |
1058 : (MODE) == QImode && (REGNO) > BX_REG && !TARGET_64BIT ? SImode \ | |
1059 : (MODE)) | |
1060 | |
1061 /* Specify the registers used for certain standard purposes. | |
1062 The values of these macros are register numbers. */ | |
1063 | |
1064 /* on the 386 the pc register is %eip, and is not usable as a general | |
1065 register. The ordinary mov instructions won't work */ | |
1066 /* #define PC_REGNUM */ | |
1067 | |
1068 /* Register to use for pushing function arguments. */ | |
1069 #define STACK_POINTER_REGNUM 7 | |
1070 | |
1071 /* Base register for access to local variables of the function. */ | |
1072 #define HARD_FRAME_POINTER_REGNUM 6 | |
1073 | |
1074 /* Base register for access to local variables of the function. */ | |
1075 #define FRAME_POINTER_REGNUM 20 | |
1076 | |
1077 /* First floating point reg */ | |
1078 #define FIRST_FLOAT_REG 8 | |
1079 | |
1080 /* First & last stack-like regs */ | |
1081 #define FIRST_STACK_REG FIRST_FLOAT_REG | |
1082 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) | |
1083 | |
1084 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) | |
1085 #define LAST_SSE_REG (FIRST_SSE_REG + 7) | |
1086 | |
1087 #define FIRST_MMX_REG (LAST_SSE_REG + 1) | |
1088 #define LAST_MMX_REG (FIRST_MMX_REG + 7) | |
1089 | |
1090 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1) | |
1091 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) | |
1092 | |
1093 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) | |
1094 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) | |
1095 | |
1096 /* Value should be nonzero if functions must have frame pointers. | |
1097 Zero means the frame pointer need not be set up (and parms | |
1098 may be accessed via the stack pointer) in functions that seem suitable. | |
1099 This is computed in `reload', in reload1.c. */ | |
1100 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required () | |
1101 | |
1102 /* Override this in other tm.h files to cope with various OS lossage | |
1103 requiring a frame pointer. */ | |
1104 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED | |
1105 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 | |
1106 #endif | |
1107 | |
1108 /* Make sure we can access arbitrary call frames. */ | |
1109 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () | |
1110 | |
1111 /* Base register for access to arguments of the function. */ | |
1112 #define ARG_POINTER_REGNUM 16 | |
1113 | |
1114 /* Register in which static-chain is passed to a function. | |
1115 We do use ECX as static chain register for 32 bit ABI. On the | |
1116 64bit ABI, ECX is an argument register, so we use R10 instead. */ | |
1117 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? R10_REG : CX_REG) | |
1118 | |
1119 /* Register to hold the addressing base for position independent | |
1120 code access to data items. We don't use PIC pointer for 64bit | |
1121 mode. Define the regnum to dummy value to prevent gcc from | |
1122 pessimizing code dealing with EBX. | |
1123 | |
1124 To avoid clobbering a call-saved register unnecessarily, we renumber | |
1125 the pic register when possible. The change is visible after the | |
1126 prologue has been emitted. */ | |
1127 | |
1128 #define REAL_PIC_OFFSET_TABLE_REGNUM BX_REG | |
1129 | |
1130 #define PIC_OFFSET_TABLE_REGNUM \ | |
1131 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \ | |
1132 || !flag_pic ? INVALID_REGNUM \ | |
1133 : reload_completed ? REGNO (pic_offset_table_rtx) \ | |
1134 : REAL_PIC_OFFSET_TABLE_REGNUM) | |
1135 | |
1136 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" | |
1137 | |
1138 /* This is overridden by <cygwin.h>. */ | |
1139 #define MS_AGGREGATE_RETURN 0 | |
1140 | |
1141 /* This is overridden by <netware.h>. */ | |
1142 #define KEEP_AGGREGATE_RETURN_POINTER 0 | |
1143 | |
1144 /* Define the classes of registers for register constraints in the | |
1145 machine description. Also define ranges of constants. | |
1146 | |
1147 One of the classes must always be named ALL_REGS and include all hard regs. | |
1148 If there is more than one class, another class must be named NO_REGS | |
1149 and contain no registers. | |
1150 | |
1151 The name GENERAL_REGS must be the name of a class (or an alias for | |
1152 another name such as ALL_REGS). This is the class of registers | |
1153 that is allowed by "g" or "r" in a register constraint. | |
1154 Also, registers outside this class are allocated only when | |
1155 instructions express preferences for them. | |
1156 | |
1157 The classes must be numbered in nondecreasing order; that is, | |
1158 a larger-numbered class must never be contained completely | |
1159 in a smaller-numbered class. | |
1160 | |
1161 For any two classes, it is very desirable that there be another | |
1162 class that represents their union. | |
1163 | |
1164 It might seem that class BREG is unnecessary, since no useful 386 | |
1165 opcode needs reg %ebx. But some systems pass args to the OS in ebx, | |
1166 and the "b" register constraint is useful in asms for syscalls. | |
1167 | |
1168 The flags, fpsr and fpcr registers are in no class. */ | |
1169 | |
1170 enum reg_class | |
1171 { | |
1172 NO_REGS, | |
1173 AREG, DREG, CREG, BREG, SIREG, DIREG, | |
1174 AD_REGS, /* %eax/%edx for DImode */ | |
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1175 CLOBBERED_REGS, /* call-clobbered integers */ |
0 | 1176 Q_REGS, /* %eax %ebx %ecx %edx */ |
1177 NON_Q_REGS, /* %esi %edi %ebp %esp */ | |
1178 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ | |
1179 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ | |
1180 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ | |
1181 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ | |
1182 FLOAT_REGS, | |
1183 SSE_FIRST_REG, | |
1184 SSE_REGS, | |
1185 MMX_REGS, | |
1186 FP_TOP_SSE_REGS, | |
1187 FP_SECOND_SSE_REGS, | |
1188 FLOAT_SSE_REGS, | |
1189 FLOAT_INT_REGS, | |
1190 INT_SSE_REGS, | |
1191 FLOAT_INT_SSE_REGS, | |
1192 ALL_REGS, LIM_REG_CLASSES | |
1193 }; | |
1194 | |
1195 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) | |
1196 | |
1197 #define INTEGER_CLASS_P(CLASS) \ | |
1198 reg_class_subset_p ((CLASS), GENERAL_REGS) | |
1199 #define FLOAT_CLASS_P(CLASS) \ | |
1200 reg_class_subset_p ((CLASS), FLOAT_REGS) | |
1201 #define SSE_CLASS_P(CLASS) \ | |
1202 reg_class_subset_p ((CLASS), SSE_REGS) | |
1203 #define MMX_CLASS_P(CLASS) \ | |
1204 ((CLASS) == MMX_REGS) | |
1205 #define MAYBE_INTEGER_CLASS_P(CLASS) \ | |
1206 reg_classes_intersect_p ((CLASS), GENERAL_REGS) | |
1207 #define MAYBE_FLOAT_CLASS_P(CLASS) \ | |
1208 reg_classes_intersect_p ((CLASS), FLOAT_REGS) | |
1209 #define MAYBE_SSE_CLASS_P(CLASS) \ | |
1210 reg_classes_intersect_p (SSE_REGS, (CLASS)) | |
1211 #define MAYBE_MMX_CLASS_P(CLASS) \ | |
1212 reg_classes_intersect_p (MMX_REGS, (CLASS)) | |
1213 | |
1214 #define Q_CLASS_P(CLASS) \ | |
1215 reg_class_subset_p ((CLASS), Q_REGS) | |
1216 | |
1217 /* Give names of register classes as strings for dump file. */ | |
1218 | |
1219 #define REG_CLASS_NAMES \ | |
1220 { "NO_REGS", \ | |
1221 "AREG", "DREG", "CREG", "BREG", \ | |
1222 "SIREG", "DIREG", \ | |
1223 "AD_REGS", \ | |
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1224 "CLOBBERED_REGS", \ |
0 | 1225 "Q_REGS", "NON_Q_REGS", \ |
1226 "INDEX_REGS", \ | |
1227 "LEGACY_REGS", \ | |
1228 "GENERAL_REGS", \ | |
1229 "FP_TOP_REG", "FP_SECOND_REG", \ | |
1230 "FLOAT_REGS", \ | |
1231 "SSE_FIRST_REG", \ | |
1232 "SSE_REGS", \ | |
1233 "MMX_REGS", \ | |
1234 "FP_TOP_SSE_REGS", \ | |
1235 "FP_SECOND_SSE_REGS", \ | |
1236 "FLOAT_SSE_REGS", \ | |
1237 "FLOAT_INT_REGS", \ | |
1238 "INT_SSE_REGS", \ | |
1239 "FLOAT_INT_SSE_REGS", \ | |
1240 "ALL_REGS" } | |
1241 | |
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1242 /* Define which registers fit in which classes. This is an initializer |
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1243 for a vector of HARD_REG_SET of length N_REG_CLASSES. |
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1244 |
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1245 Note that the default setting of CLOBBERED_REGS is for 32-bit; this |
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1246 is adjusted by CONDITIONAL_REGISTER_USAGE for the 64-bit ABI in effect. */ |
0 | 1247 |
1248 #define REG_CLASS_CONTENTS \ | |
1249 { { 0x00, 0x0 }, \ | |
1250 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ | |
1251 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ | |
1252 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ | |
1253 { 0x03, 0x0 }, /* AD_REGS */ \ | |
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1254 { 0x07, 0x0 }, /* CLOBBERED_REGS */ \ |
0 | 1255 { 0x0f, 0x0 }, /* Q_REGS */ \ |
1256 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ | |
1257 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ | |
1258 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ | |
1259 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ | |
1260 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ | |
1261 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ | |
1262 { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \ | |
1263 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ | |
1264 { 0xe0000000, 0x1f }, /* MMX_REGS */ \ | |
1265 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ | |
1266 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ | |
1267 { 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \ | |
1268 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ | |
1269 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ | |
1270 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ | |
1271 { 0xffffffff,0x1fffff } \ | |
1272 } | |
1273 | |
1274 /* The following macro defines cover classes for Integrated Register | |
1275 Allocator. Cover classes is a set of non-intersected register | |
1276 classes covering all hard registers used for register allocation | |
1277 purpose. Any move between two registers of a cover class should be | |
1278 cheaper than load or store of the registers. The macro value is | |
1279 array of register classes with LIM_REG_CLASSES used as the end | |
1280 marker. */ | |
1281 | |
1282 #define IRA_COVER_CLASSES \ | |
1283 { \ | |
1284 GENERAL_REGS, FLOAT_REGS, MMX_REGS, SSE_REGS, LIM_REG_CLASSES \ | |
1285 } | |
1286 | |
1287 /* The same information, inverted: | |
1288 Return the class number of the smallest class containing | |
1289 reg number REGNO. This could be a conditional expression | |
1290 or could index an array. */ | |
1291 | |
1292 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) | |
1293 | |
1294 /* When defined, the compiler allows registers explicitly used in the | |
1295 rtl to be used as spill registers but prevents the compiler from | |
1296 extending the lifetime of these registers. */ | |
1297 | |
1298 #define SMALL_REGISTER_CLASSES 1 | |
1299 | |
1300 #define QI_REG_P(X) (REG_P (X) && REGNO (X) <= BX_REG) | |
1301 | |
1302 #define GENERAL_REGNO_P(N) \ | |
1303 ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N)) | |
1304 | |
1305 #define GENERAL_REG_P(X) \ | |
1306 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) | |
1307 | |
1308 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) | |
1309 | |
1310 #define REX_INT_REGNO_P(N) \ | |
1311 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) | |
1312 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) | |
1313 | |
1314 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) | |
1315 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) | |
1316 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) | |
1317 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) | |
1318 | |
1319 #define X87_FLOAT_MODE_P(MODE) \ | |
1320 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) | |
1321 | |
1322 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) | |
1323 #define SSE_REGNO_P(N) \ | |
1324 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ | |
1325 || REX_SSE_REGNO_P (N)) | |
1326 | |
1327 #define REX_SSE_REGNO_P(N) \ | |
1328 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) | |
1329 | |
1330 #define SSE_REGNO(N) \ | |
1331 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) | |
1332 | |
1333 #define SSE_FLOAT_MODE_P(MODE) \ | |
1334 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) | |
1335 | |
1336 #define SSE_VEC_FLOAT_MODE_P(MODE) \ | |
1337 ((TARGET_SSE && (MODE) == V4SFmode) || (TARGET_SSE2 && (MODE) == V2DFmode)) | |
1338 | |
1339 #define AVX_FLOAT_MODE_P(MODE) \ | |
1340 (TARGET_AVX && ((MODE) == SFmode || (MODE) == DFmode)) | |
1341 | |
1342 #define AVX128_VEC_FLOAT_MODE_P(MODE) \ | |
1343 (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode)) | |
1344 | |
1345 #define AVX256_VEC_FLOAT_MODE_P(MODE) \ | |
1346 (TARGET_AVX && ((MODE) == V8SFmode || (MODE) == V4DFmode)) | |
1347 | |
1348 #define AVX_VEC_FLOAT_MODE_P(MODE) \ | |
1349 (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode \ | |
1350 || (MODE) == V8SFmode || (MODE) == V4DFmode)) | |
1351 | |
1352 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) | |
1353 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) | |
1354 | |
1355 #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP))) | |
1356 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) | |
1357 | |
1358 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) | |
1359 | |
1360 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) | |
1361 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) | |
1362 | |
1363 /* The class value for index registers, and the one for base regs. */ | |
1364 | |
1365 #define INDEX_REG_CLASS INDEX_REGS | |
1366 #define BASE_REG_CLASS GENERAL_REGS | |
1367 | |
1368 /* Place additional restrictions on the register class to use when it | |
1369 is necessary to be able to hold a value of mode MODE in a reload | |
1370 register for which class CLASS would ordinarily be used. */ | |
1371 | |
1372 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ | |
1373 ((MODE) == QImode && !TARGET_64BIT \ | |
1374 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ | |
1375 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ | |
1376 ? Q_REGS : (CLASS)) | |
1377 | |
1378 /* Given an rtx X being reloaded into a reg required to be | |
1379 in class CLASS, return the class of reg to actually use. | |
1380 In general this is just CLASS; but on some machines | |
1381 in some cases it is preferable to use a more restrictive class. | |
1382 On the 80386 series, we prevent floating constants from being | |
1383 reloaded into floating registers (since no move-insn can do that) | |
1384 and we ensure that QImodes aren't reloaded into the esi or edi reg. */ | |
1385 | |
1386 /* Put float CONST_DOUBLE in the constant pool instead of fp regs. | |
1387 QImode must go into class Q_REGS. | |
1388 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and | |
1389 movdf to do mem-to-mem moves through integer regs. */ | |
1390 | |
1391 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
1392 ix86_preferred_reload_class ((X), (CLASS)) | |
1393 | |
1394 /* Discourage putting floating-point values in SSE registers unless | |
1395 SSE math is being used, and likewise for the 387 registers. */ | |
1396 | |
1397 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \ | |
1398 ix86_preferred_output_reload_class ((X), (CLASS)) | |
1399 | |
1400 /* If we are copying between general and FP registers, we need a memory | |
1401 location. The same is true for SSE and MMX registers. */ | |
1402 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ | |
1403 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) | |
1404 | |
1405 /* Get_secondary_mem widens integral modes to BITS_PER_WORD. | |
1406 There is no need to emit full 64 bit move on 64 bit targets | |
1407 for integral modes that can be moved using 32 bit move. */ | |
1408 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
1409 (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \ | |
1410 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
1411 : MODE) | |
1412 | |
1413 /* Return the maximum number of consecutive registers | |
1414 needed to represent mode MODE in a register of class CLASS. */ | |
1415 /* On the 80386, this is the size of MODE in words, | |
1416 except in the FP regs, where a single reg is always enough. */ | |
1417 #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
1418 (!MAYBE_INTEGER_CLASS_P (CLASS) \ | |
1419 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ | |
1420 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \ | |
1421 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) | |
1422 | |
1423 /* A C expression whose value is nonzero if pseudos that have been | |
1424 assigned to registers of class CLASS would likely be spilled | |
1425 because registers of CLASS are needed for spill registers. | |
1426 | |
1427 The default value of this macro returns 1 if CLASS has exactly one | |
1428 register and zero otherwise. On most machines, this default | |
1429 should be used. Only define this macro to some other expression | |
1430 if pseudo allocated by `local-alloc.c' end up in memory because | |
1431 their hard registers were needed for spill registers. If this | |
1432 macro returns nonzero for those classes, those pseudos will only | |
1433 be allocated by `global.c', which knows how to reallocate the | |
1434 pseudo to another register. If there would not be another | |
1435 register available for reallocation, you should not change the | |
1436 definition of this macro since the only effect of such a | |
1437 definition would be to slow down register allocation. */ | |
1438 | |
1439 #define CLASS_LIKELY_SPILLED_P(CLASS) \ | |
1440 (((CLASS) == AREG) \ | |
1441 || ((CLASS) == DREG) \ | |
1442 || ((CLASS) == CREG) \ | |
1443 || ((CLASS) == BREG) \ | |
1444 || ((CLASS) == AD_REGS) \ | |
1445 || ((CLASS) == SIREG) \ | |
1446 || ((CLASS) == DIREG) \ | |
19
58ad6c70ea60
update gcc from 4.4.0 to 4.4.1.
kent@firefly.cr.ie.u-ryukyu.ac.jp
parents:
0
diff
changeset
|
1447 || ((CLASS) == SSE_FIRST_REG) \ |
0 | 1448 || ((CLASS) == FP_TOP_REG) \ |
1449 || ((CLASS) == FP_SECOND_REG)) | |
1450 | |
1451 /* Return a class of registers that cannot change FROM mode to TO mode. */ | |
1452 | |
1453 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
1454 ix86_cannot_change_mode_class (FROM, TO, CLASS) | |
1455 | |
1456 /* Stack layout; function entry, exit and calling. */ | |
1457 | |
1458 /* Define this if pushing a word on the stack | |
1459 makes the stack pointer a smaller address. */ | |
1460 #define STACK_GROWS_DOWNWARD | |
1461 | |
1462 /* Define this to nonzero if the nominal address of the stack frame | |
1463 is at the high-address end of the local variables; | |
1464 that is, each additional local variable allocated | |
1465 goes at a more negative offset in the frame. */ | |
1466 #define FRAME_GROWS_DOWNWARD 1 | |
1467 | |
1468 /* Offset within stack frame to start allocating local variables at. | |
1469 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1470 first local allocated. Otherwise, it is the offset to the BEGINNING | |
1471 of the first local allocated. */ | |
1472 #define STARTING_FRAME_OFFSET 0 | |
1473 | |
1474 /* If we generate an insn to push BYTES bytes, | |
1475 this says how many the stack pointer really advances by. | |
1476 On 386, we have pushw instruction that decrements by exactly 2 no | |
1477 matter what the position was, there is no pushb. | |
1478 But as CIE data alignment factor on this arch is -4, we need to make | |
1479 sure all stack pointer adjustments are in multiple of 4. | |
1480 | |
1481 For 64bit ABI we round up to 8 bytes. | |
1482 */ | |
1483 | |
1484 #define PUSH_ROUNDING(BYTES) \ | |
1485 (TARGET_64BIT \ | |
1486 ? (((BYTES) + 7) & (-8)) \ | |
1487 : (((BYTES) + 3) & (-4))) | |
1488 | |
1489 /* If defined, the maximum amount of space required for outgoing arguments will | |
1490 be computed and placed into the variable | |
1491 `crtl->outgoing_args_size'. No space will be pushed onto the | |
1492 stack for each call; instead, the function prologue should increase the stack | |
1493 frame size by this amount. | |
1494 | |
1495 MS ABI seem to require 16 byte alignment everywhere except for function | |
1496 prologue and apilogue. This is not possible without | |
1497 ACCUMULATE_OUTGOING_ARGS. */ | |
1498 | |
1499 #define ACCUMULATE_OUTGOING_ARGS \ | |
1500 (TARGET_ACCUMULATE_OUTGOING_ARGS || ix86_cfun_abi () == MS_ABI) | |
1501 | |
1502 /* If defined, a C expression whose value is nonzero when we want to use PUSH | |
1503 instructions to pass outgoing arguments. */ | |
1504 | |
1505 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) | |
1506 | |
1507 /* We want the stack and args grow in opposite directions, even if | |
1508 PUSH_ARGS is 0. */ | |
1509 #define PUSH_ARGS_REVERSED 1 | |
1510 | |
1511 /* Offset of first parameter from the argument pointer register value. */ | |
1512 #define FIRST_PARM_OFFSET(FNDECL) 0 | |
1513 | |
1514 /* Define this macro if functions should assume that stack space has been | |
1515 allocated for arguments even when their values are passed in registers. | |
1516 | |
1517 The value of this macro is the size, in bytes, of the area reserved for | |
1518 arguments passed in registers for the function represented by FNDECL. | |
1519 | |
1520 This space can be allocated by the caller, or be a part of the | |
1521 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says | |
1522 which. */ | |
1523 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) | |
1524 | |
1525 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ | |
1526 (ix86_function_type_abi (FNTYPE) == MS_ABI) | |
1527 | |
1528 /* Value is the number of bytes of arguments automatically | |
1529 popped when returning from a subroutine call. | |
1530 FUNDECL is the declaration node of the function (as a tree), | |
1531 FUNTYPE is the data type of the function (as a tree), | |
1532 or for a library call it is an identifier node for the subroutine name. | |
1533 SIZE is the number of bytes of arguments passed on the stack. | |
1534 | |
1535 On the 80386, the RTD insn may be used to pop them if the number | |
1536 of args is fixed, but if the number is variable then the caller | |
1537 must pop them all. RTD can't be used for library calls now | |
1538 because the library is compiled with the Unix compiler. | |
1539 Use of RTD is a selectable option, since it is incompatible with | |
1540 standard Unix calling sequences. If the option is not selected, | |
1541 the caller must always pop the args. | |
1542 | |
1543 The attribute stdcall is equivalent to RTD on a per module basis. */ | |
1544 | |
1545 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ | |
1546 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) | |
1547 | |
1548 #define FUNCTION_VALUE_REGNO_P(N) ix86_function_value_regno_p (N) | |
1549 | |
1550 /* Define how to find the value returned by a library function | |
1551 assuming the value has mode MODE. */ | |
1552 | |
1553 #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) | |
1554 | |
1555 /* Define the size of the result block used for communication between | |
1556 untyped_call and untyped_return. The block contains a DImode value | |
1557 followed by the block used by fnsave and frstor. */ | |
1558 | |
1559 #define APPLY_RESULT_SIZE (8+108) | |
1560 | |
1561 /* 1 if N is a possible register number for function argument passing. */ | |
1562 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) | |
1563 | |
1564 /* Define a data type for recording info about an argument list | |
1565 during the scan of that argument list. This data type should | |
1566 hold all necessary information about the function itself | |
1567 and about the args processed so far, enough to enable macros | |
1568 such as FUNCTION_ARG to determine where the next arg should go. */ | |
1569 | |
1570 typedef struct ix86_args { | |
1571 int words; /* # words passed so far */ | |
1572 int nregs; /* # registers available for passing */ | |
1573 int regno; /* next available register number */ | |
1574 int fastcall; /* fastcall calling convention is used */ | |
1575 int sse_words; /* # sse words passed so far */ | |
1576 int sse_nregs; /* # sse registers available for passing */ | |
1577 int warn_avx; /* True when we want to warn about AVX ABI. */ | |
1578 int warn_sse; /* True when we want to warn about SSE ABI. */ | |
1579 int warn_mmx; /* True when we want to warn about MMX ABI. */ | |
1580 int sse_regno; /* next available sse register number */ | |
1581 int mmx_words; /* # mmx words passed so far */ | |
1582 int mmx_nregs; /* # mmx registers available for passing */ | |
1583 int mmx_regno; /* next available mmx register number */ | |
1584 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ | |
1585 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should | |
1586 be passed in SSE registers. Otherwise 0. */ | |
1587 int call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise | |
1588 MS_ABI for ms abi. */ | |
1589 } CUMULATIVE_ARGS; | |
1590 | |
1591 /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1592 for a call to a function whose data type is FNTYPE. | |
1593 For a library call, FNTYPE is 0. */ | |
1594 | |
1595 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ | |
1596 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) | |
1597 | |
1598 /* Update the data in CUM to advance over an argument | |
1599 of mode MODE and data type TYPE. | |
1600 (TYPE is null for libcalls where that information may not be available.) */ | |
1601 | |
1602 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
1603 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) | |
1604 | |
1605 /* Define where to put the arguments to a function. | |
1606 Value is zero to push the argument on the stack, | |
1607 or a hard register in which to store the argument. | |
1608 | |
1609 MODE is the argument's machine mode. | |
1610 TYPE is the data type of the argument (as a tree). | |
1611 This is null for libcalls where that information may | |
1612 not be available. | |
1613 CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
1614 the preceding args and about the function being called. | |
1615 NAMED is nonzero if this argument is a named parameter | |
1616 (otherwise it is an extra parameter matching an ellipsis). */ | |
1617 | |
1618 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
1619 function_arg (&(CUM), (MODE), (TYPE), (NAMED)) | |
1620 | |
1621 #define TARGET_ASM_FILE_END ix86_file_end | |
1622 #define NEED_INDICATE_EXEC_STACK 0 | |
1623 | |
1624 /* Output assembler code to FILE to increment profiler label # LABELNO | |
1625 for profiling a function entry. */ | |
1626 | |
1627 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) | |
1628 | |
1629 #define MCOUNT_NAME "_mcount" | |
1630 | |
1631 #define PROFILE_COUNT_REGISTER "edx" | |
1632 | |
1633 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1634 the stack pointer does not matter. The value is tested only in | |
1635 functions that have frame pointers. | |
1636 No definition is equivalent to always zero. */ | |
1637 /* Note on the 386 it might be more efficient not to define this since | |
1638 we have to restore it ourselves from the frame pointer, in order to | |
1639 use pop */ | |
1640 | |
1641 #define EXIT_IGNORE_STACK 1 | |
1642 | |
1643 /* Output assembler code for a block containing the constant parts | |
1644 of a trampoline, leaving space for the variable parts. */ | |
1645 | |
1646 /* On the 386, the trampoline contains two instructions: | |
1647 mov #STATIC,ecx | |
1648 jmp FUNCTION | |
1649 The trampoline is generated entirely at runtime. The operand of JMP | |
1650 is the address of FUNCTION relative to the instruction following the | |
1651 JMP (which is 5 bytes long). */ | |
1652 | |
1653 /* Length in units of the trampoline for entering a nested function. */ | |
1654 | |
1655 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10) | |
1656 | |
1657 /* Emit RTL insns to initialize the variable parts of a trampoline. | |
1658 FNADDR is an RTX for the address of the function's pure code. | |
1659 CXT is an RTX for the static chain value for the function. */ | |
1660 | |
1661 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ | |
1662 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT)) | |
1663 | |
1664 /* Definitions for register eliminations. | |
1665 | |
1666 This is an array of structures. Each structure initializes one pair | |
1667 of eliminable registers. The "from" register number is given first, | |
1668 followed by "to". Eliminations of the same "from" register are listed | |
1669 in order of preference. | |
1670 | |
1671 There are two registers that can always be eliminated on the i386. | |
1672 The frame pointer and the arg pointer can be replaced by either the | |
1673 hard frame pointer or to the stack pointer, depending upon the | |
1674 circumstances. The hard frame pointer is not used before reload and | |
1675 so it is not eligible for elimination. */ | |
1676 | |
1677 #define ELIMINABLE_REGS \ | |
1678 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1679 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1680 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1681 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ | |
1682 | |
1683 /* Given FROM and TO register numbers, say whether this elimination is | |
1684 allowed. */ | |
1685 | |
1686 #define CAN_ELIMINATE(FROM, TO) ix86_can_eliminate ((FROM), (TO)) | |
1687 | |
1688 /* Define the offset between two registers, one to be eliminated, and the other | |
1689 its replacement, at the start of a routine. */ | |
1690 | |
1691 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
1692 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) | |
1693 | |
1694 /* Addressing modes, and classification of registers for them. */ | |
1695 | |
1696 /* Macros to check register numbers against specific register classes. */ | |
1697 | |
1698 /* These assume that REGNO is a hard or pseudo reg number. | |
1699 They give nonzero only if REGNO is a hard reg of the suitable class | |
1700 or a pseudo reg currently allocated to a suitable hard reg. | |
1701 Since they use reg_renumber, they are safe only once reg_renumber | |
1702 has been allocated, which happens in local-alloc.c. */ | |
1703 | |
1704 #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1705 ((REGNO) < STACK_POINTER_REGNUM \ | |
1706 || REX_INT_REGNO_P (REGNO) \ | |
1707 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ | |
1708 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) | |
1709 | |
1710 #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
1711 (GENERAL_REGNO_P (REGNO) \ | |
1712 || (REGNO) == ARG_POINTER_REGNUM \ | |
1713 || (REGNO) == FRAME_POINTER_REGNUM \ | |
1714 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) | |
1715 | |
1716 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx | |
1717 and check its validity for a certain class. | |
1718 We have two alternate definitions for each of them. | |
1719 The usual definition accepts all pseudo regs; the other rejects | |
1720 them unless they have been allocated suitable hard regs. | |
1721 The symbol REG_OK_STRICT causes the latter definition to be used. | |
1722 | |
1723 Most source files want to accept pseudo regs in the hope that | |
1724 they will get allocated to the class that the insn wants them to be in. | |
1725 Source files for reload pass need to be strict. | |
1726 After reload, it makes no difference, since pseudo regs have | |
1727 been eliminated by then. */ | |
1728 | |
1729 | |
1730 /* Non strict versions, pseudos are ok. */ | |
1731 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ | |
1732 (REGNO (X) < STACK_POINTER_REGNUM \ | |
1733 || REX_INT_REGNO_P (REGNO (X)) \ | |
1734 || REGNO (X) >= FIRST_PSEUDO_REGISTER) | |
1735 | |
1736 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ | |
1737 (GENERAL_REGNO_P (REGNO (X)) \ | |
1738 || REGNO (X) == ARG_POINTER_REGNUM \ | |
1739 || REGNO (X) == FRAME_POINTER_REGNUM \ | |
1740 || REGNO (X) >= FIRST_PSEUDO_REGISTER) | |
1741 | |
1742 /* Strict versions, hard registers only */ | |
1743 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) | |
1744 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) | |
1745 | |
1746 #ifndef REG_OK_STRICT | |
1747 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) | |
1748 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) | |
1749 | |
1750 #else | |
1751 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) | |
1752 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) | |
1753 #endif | |
1754 | |
1755 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression | |
1756 that is a valid memory address for an instruction. | |
1757 The MODE argument is the machine mode for the MEM expression | |
1758 that wants to use this address. | |
1759 | |
1760 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, | |
1761 except for CONSTANT_ADDRESS_P which is usually machine-independent. | |
1762 | |
1763 See legitimize_pic_address in i386.c for details as to what | |
1764 constitutes a legitimate address when -fpic is used. */ | |
1765 | |
1766 #define MAX_REGS_PER_ADDRESS 2 | |
1767 | |
1768 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) | |
1769 | |
1770 /* Nonzero if the constant value X is a legitimate general operand. | |
1771 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1772 | |
1773 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) | |
1774 | |
1775 #ifdef REG_OK_STRICT | |
1776 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1777 do { \ | |
1778 if (legitimate_address_p ((MODE), (X), 1)) \ | |
1779 goto ADDR; \ | |
1780 } while (0) | |
1781 | |
1782 #else | |
1783 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
1784 do { \ | |
1785 if (legitimate_address_p ((MODE), (X), 0)) \ | |
1786 goto ADDR; \ | |
1787 } while (0) | |
1788 | |
1789 #endif | |
1790 | |
1791 /* If defined, a C expression to determine the base term of address X. | |
1792 This macro is used in only one place: `find_base_term' in alias.c. | |
1793 | |
1794 It is always safe for this macro to not be defined. It exists so | |
1795 that alias analysis can understand machine-dependent addresses. | |
1796 | |
1797 The typical use of this macro is to handle addresses containing | |
1798 a label_ref or symbol_ref within an UNSPEC. */ | |
1799 | |
1800 #define FIND_BASE_TERM(X) ix86_find_base_term (X) | |
1801 | |
1802 /* Try machine-dependent ways of modifying an illegitimate address | |
1803 to be legitimate. If we find one, return the new, valid address. | |
1804 This macro is used in only one place: `memory_address' in explow.c. | |
1805 | |
1806 OLDX is the address as it was before break_out_memory_refs was called. | |
1807 In some cases it is useful to look at this to decide what needs to be done. | |
1808 | |
1809 MODE and WIN are passed so that this macro can use | |
1810 GO_IF_LEGITIMATE_ADDRESS. | |
1811 | |
1812 It is always safe for this macro to do nothing. It exists to recognize | |
1813 opportunities to optimize the output. | |
1814 | |
1815 For the 80386, we handle X+REG by loading X into a register R and | |
1816 using R+REG. R will go in a general reg and indexing will be used. | |
1817 However, if REG is a broken-out memory address or multiplication, | |
1818 nothing needs to be done because REG can certainly go in a general reg. | |
1819 | |
1820 When -fpic is used, special handling is needed for symbolic references. | |
1821 See comments by legitimize_pic_address in i386.c for details. */ | |
1822 | |
1823 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ | |
1824 do { \ | |
1825 (X) = legitimize_address ((X), (OLDX), (MODE)); \ | |
1826 if (memory_address_p ((MODE), (X))) \ | |
1827 goto WIN; \ | |
1828 } while (0) | |
1829 | |
1830 /* Nonzero if the constant value X is a legitimate general operand | |
1831 when generating PIC code. It is given that flag_pic is on and | |
1832 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
1833 | |
1834 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) | |
1835 | |
1836 #define SYMBOLIC_CONST(X) \ | |
1837 (GET_CODE (X) == SYMBOL_REF \ | |
1838 || GET_CODE (X) == LABEL_REF \ | |
1839 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
1840 | |
1841 /* Go to LABEL if ADDR (a legitimate address expression) | |
1842 has an effect that depends on the machine mode it is used for. | |
1843 On the 80386, only postdecrement and postincrement address depend thus | |
1844 (the amount of decrement or increment being the length of the operand). | |
1845 These are now caught in recog.c. */ | |
1846 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) | |
1847 | |
1848 /* Max number of args passed in registers. If this is more than 3, we will | |
1849 have problems with ebx (register #4), since it is a caller save register and | |
1850 is also used as the pic register in ELF. So for now, don't allow more than | |
1851 3 registers to be passed in registers. */ | |
1852 | |
1853 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ | |
1854 #define X86_64_REGPARM_MAX 6 | |
1855 #define X64_REGPARM_MAX 4 | |
1856 #define X86_32_REGPARM_MAX 3 | |
1857 | |
1858 #define X86_64_SSE_REGPARM_MAX 8 | |
1859 #define X64_SSE_REGPARM_MAX 4 | |
1860 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? 3 : 0) | |
1861 | |
1862 #define REGPARM_MAX \ | |
1863 (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X64_REGPARM_MAX \ | |
1864 : X86_64_REGPARM_MAX) \ | |
1865 : X86_32_REGPARM_MAX) | |
1866 | |
1867 #define SSE_REGPARM_MAX \ | |
1868 (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X64_SSE_REGPARM_MAX \ | |
1869 : X86_64_SSE_REGPARM_MAX) \ | |
1870 : X86_32_SSE_REGPARM_MAX) | |
1871 | |
1872 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) | |
1873 | |
1874 | |
1875 /* Specify the machine mode that this machine uses | |
1876 for the index in the tablejump instruction. */ | |
1877 #define CASE_VECTOR_MODE \ | |
1878 (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) | |
1879 | |
1880 /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
1881 #define DEFAULT_SIGNED_CHAR 1 | |
1882 | |
1883 /* Max number of bytes we can move from memory to memory | |
1884 in one reasonably fast instruction. */ | |
1885 #define MOVE_MAX 16 | |
1886 | |
1887 /* MOVE_MAX_PIECES is the number of bytes at a time which we can | |
1888 move efficiently, as opposed to MOVE_MAX which is the maximum | |
1889 number of bytes we can move with a single instruction. */ | |
1890 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) | |
1891 | |
1892 /* If a memory-to-memory move would take MOVE_RATIO or more simple | |
1893 move-instruction pairs, we will do a movmem or libcall instead. | |
1894 Increasing the value will always make code faster, but eventually | |
1895 incurs high cost in increased code size. | |
1896 | |
1897 If you don't define this, a reasonable default is used. */ | |
1898 | |
1899 #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) | |
1900 | |
1901 /* If a clear memory operation would take CLEAR_RATIO or more simple | |
1902 move-instruction sequences, we will do a clrmem or libcall instead. */ | |
1903 | |
1904 #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2) | |
1905 | |
1906 /* Define if shifts truncate the shift count | |
1907 which implies one can omit a sign-extension or zero-extension | |
1908 of a shift count. */ | |
1909 /* On i386, shifts do truncate the count. But bit opcodes don't. */ | |
1910 | |
1911 /* #define SHIFT_COUNT_TRUNCATED */ | |
1912 | |
1913 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1914 is done just by pretending it is already truncated. */ | |
1915 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1916 | |
1917 /* A macro to update M and UNSIGNEDP when an object whose type is | |
1918 TYPE and which has the specified mode and signedness is to be | |
1919 stored in a register. This macro is only called when TYPE is a | |
1920 scalar type. | |
1921 | |
1922 On i386 it is sometimes useful to promote HImode and QImode | |
1923 quantities to SImode. The choice depends on target type. */ | |
1924 | |
1925 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
1926 do { \ | |
1927 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ | |
1928 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ | |
1929 (MODE) = SImode; \ | |
1930 } while (0) | |
1931 | |
1932 /* Specify the machine mode that pointers have. | |
1933 After generation of rtl, the compiler makes no further distinction | |
1934 between pointers and any other objects of this machine mode. */ | |
1935 #define Pmode (TARGET_64BIT ? DImode : SImode) | |
1936 | |
1937 /* A function address in a call instruction | |
1938 is a byte address (for indexing purposes) | |
1939 so give the MEM rtx a byte's mode. */ | |
1940 #define FUNCTION_MODE QImode | |
1941 | |
1942 /* A C expression for the cost of moving data from a register in class FROM to | |
1943 one in class TO. The classes are expressed using the enumeration values | |
1944 such as `GENERAL_REGS'. A value of 2 is the default; other values are | |
1945 interpreted relative to that. | |
1946 | |
1947 It is not required that the cost always equal 2 when FROM is the same as TO; | |
1948 on some machines it is expensive to move between registers if they are not | |
1949 general registers. */ | |
1950 | |
1951 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ | |
1952 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) | |
1953 | |
1954 /* A C expression for the cost of moving data of mode M between a | |
1955 register and memory. A value of 2 is the default; this cost is | |
1956 relative to those in `REGISTER_MOVE_COST'. | |
1957 | |
1958 If moving between registers and memory is more expensive than | |
1959 between two registers, you should define this macro to express the | |
1960 relative cost. */ | |
1961 | |
1962 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \ | |
1963 ix86_memory_move_cost ((MODE), (CLASS), (IN)) | |
1964 | |
1965 /* A C expression for the cost of a branch instruction. A value of 1 | |
1966 is the default; other values are interpreted relative to that. */ | |
1967 | |
1968 #define BRANCH_COST(speed_p, predictable_p) \ | |
1969 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) | |
1970 | |
1971 /* Define this macro as a C expression which is nonzero if accessing | |
1972 less than a word of memory (i.e. a `char' or a `short') is no | |
1973 faster than accessing a word of memory, i.e., if such access | |
1974 require more than one instruction or if there is no difference in | |
1975 cost between byte and (aligned) word loads. | |
1976 | |
1977 When this macro is not defined, the compiler will access a field by | |
1978 finding the smallest containing object; when it is defined, a | |
1979 fullword load will be used if alignment permits. Unless bytes | |
1980 accesses are faster than word accesses, using word accesses is | |
1981 preferable since it may eliminate subsequent memory access if | |
1982 subsequent accesses occur to other fields in the same word of the | |
1983 structure, but to different bytes. */ | |
1984 | |
1985 #define SLOW_BYTE_ACCESS 0 | |
1986 | |
1987 /* Nonzero if access to memory by shorts is slow and undesirable. */ | |
1988 #define SLOW_SHORT_ACCESS 0 | |
1989 | |
1990 /* Define this macro to be the value 1 if unaligned accesses have a | |
1991 cost many times greater than aligned accesses, for example if they | |
1992 are emulated in a trap handler. | |
1993 | |
1994 When this macro is nonzero, the compiler will act as if | |
1995 `STRICT_ALIGNMENT' were nonzero when generating code for block | |
1996 moves. This can cause significantly more instructions to be | |
1997 produced. Therefore, do not set this macro nonzero if unaligned | |
1998 accesses only add a cycle or two to the time for a memory access. | |
1999 | |
2000 If the value of this macro is always zero, it need not be defined. */ | |
2001 | |
2002 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ | |
2003 | |
2004 /* Define this macro if it is as good or better to call a constant | |
2005 function address than to call an address kept in a register. | |
2006 | |
2007 Desirable on the 386 because a CALL with a constant address is | |
2008 faster than one with a register address. */ | |
2009 | |
2010 #define NO_FUNCTION_CSE | |
2011 | |
2012 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
2013 return the mode to be used for the comparison. | |
2014 | |
2015 For floating-point equality comparisons, CCFPEQmode should be used. | |
2016 VOIDmode should be used in all other cases. | |
2017 | |
2018 For integer comparisons against zero, reduce to CCNOmode or CCZmode if | |
2019 possible, to allow for more combinations. */ | |
2020 | |
2021 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) | |
2022 | |
2023 /* Return nonzero if MODE implies a floating point inequality can be | |
2024 reversed. */ | |
2025 | |
2026 #define REVERSIBLE_CC_MODE(MODE) 1 | |
2027 | |
2028 /* A C expression whose value is reversed condition code of the CODE for | |
2029 comparison done in CC_MODE mode. */ | |
2030 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) | |
2031 | |
2032 | |
2033 /* Control the assembler format that we output, to the extent | |
2034 this does not vary between assemblers. */ | |
2035 | |
2036 /* How to refer to registers in assembler output. | |
2037 This sequence is indexed by compiler's hard-register-number (see above). */ | |
2038 | |
2039 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". | |
2040 For non floating point regs, the following are the HImode names. | |
2041 | |
2042 For float regs, the stack top is sometimes referred to as "%st(0)" | |
2043 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */ | |
2044 | |
2045 #define HI_REGISTER_NAMES \ | |
2046 {"ax","dx","cx","bx","si","di","bp","sp", \ | |
2047 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ | |
2048 "argp", "flags", "fpsr", "fpcr", "frame", \ | |
2049 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ | |
2050 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ | |
2051 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ | |
2052 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} | |
2053 | |
2054 #define REGISTER_NAMES HI_REGISTER_NAMES | |
2055 | |
2056 /* Table of additional register names to use in user input. */ | |
2057 | |
2058 #define ADDITIONAL_REGISTER_NAMES \ | |
2059 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ | |
2060 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ | |
2061 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ | |
2062 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ | |
2063 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ | |
2064 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } } | |
2065 | |
2066 /* Note we are omitting these since currently I don't know how | |
2067 to get gcc to use these, since they want the same but different | |
2068 number as al, and ax. | |
2069 */ | |
2070 | |
2071 #define QI_REGISTER_NAMES \ | |
2072 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} | |
2073 | |
2074 /* These parallel the array above, and can be used to access bits 8:15 | |
2075 of regs 0 through 3. */ | |
2076 | |
2077 #define QI_HIGH_REGISTER_NAMES \ | |
2078 {"ah", "dh", "ch", "bh", } | |
2079 | |
2080 /* How to renumber registers for dbx and gdb. */ | |
2081 | |
2082 #define DBX_REGISTER_NUMBER(N) \ | |
2083 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) | |
2084 | |
2085 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
2086 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; | |
2087 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; | |
2088 | |
2089 /* Before the prologue, RA is at 0(%esp). */ | |
2090 #define INCOMING_RETURN_ADDR_RTX \ | |
2091 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) | |
2092 | |
2093 /* After the prologue, RA is at -4(AP) in the current frame. */ | |
2094 #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
2095 ((COUNT) == 0 \ | |
2096 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ | |
2097 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) | |
2098 | |
2099 /* PC is dbx register 8; let's use that column for RA. */ | |
2100 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) | |
2101 | |
2102 /* Before the prologue, the top of the frame is at 4(%esp). */ | |
2103 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD | |
2104 | |
2105 /* Describe how we implement __builtin_eh_return. */ | |
2106 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) | |
2107 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) | |
2108 | |
2109 | |
2110 /* Select a format to encode pointers in exception handling data. CODE | |
2111 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
2112 true if the symbol may be affected by dynamic relocations. | |
2113 | |
2114 ??? All x86 object file formats are capable of representing this. | |
2115 After all, the relocation needed is the same as for the call insn. | |
2116 Whether or not a particular assembler allows us to enter such, I | |
2117 guess we'll have to see. */ | |
2118 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
2119 asm_preferred_eh_data_format ((CODE), (GLOBAL)) | |
2120 | |
2121 /* This is how to output an insn to push a register on the stack. | |
2122 It need not be very fast code. */ | |
2123 | |
2124 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ | |
2125 do { \ | |
2126 if (TARGET_64BIT) \ | |
2127 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ | |
2128 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
2129 else \ | |
2130 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
2131 } while (0) | |
2132 | |
2133 /* This is how to output an insn to pop a register from the stack. | |
2134 It need not be very fast code. */ | |
2135 | |
2136 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ | |
2137 do { \ | |
2138 if (TARGET_64BIT) \ | |
2139 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ | |
2140 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ | |
2141 else \ | |
2142 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ | |
2143 } while (0) | |
2144 | |
2145 /* This is how to output an element of a case-vector that is absolute. */ | |
2146 | |
2147 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
2148 ix86_output_addr_vec_elt ((FILE), (VALUE)) | |
2149 | |
2150 /* This is how to output an element of a case-vector that is relative. */ | |
2151 | |
2152 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
2153 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) | |
2154 | |
2155 /* When we see %v, we will print the 'v' prefix if TARGET_AVX is | |
2156 true. */ | |
2157 | |
2158 #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ | |
2159 { \ | |
2160 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ | |
2161 { \ | |
2162 if (TARGET_AVX) \ | |
2163 (PTR) += 1; \ | |
2164 else \ | |
2165 (PTR) += 2; \ | |
2166 } \ | |
2167 } | |
2168 | |
2169 /* A C statement or statements which output an assembler instruction | |
2170 opcode to the stdio stream STREAM. The macro-operand PTR is a | |
2171 variable of type `char *' which points to the opcode name in | |
2172 its "internal" form--the form that is written in the machine | |
2173 description. */ | |
2174 | |
2175 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ | |
2176 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) | |
2177 | |
2178 /* Under some conditions we need jump tables in the text section, | |
2179 because the assembler cannot handle label differences between | |
2180 sections. This is the case for x86_64 on Mach-O for example. */ | |
2181 | |
2182 #define JUMP_TABLES_IN_TEXT_SECTION \ | |
2183 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ | |
2184 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) | |
2185 | |
2186 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, | |
2187 and switch back. For x86 we do this only to save a few bytes that | |
2188 would otherwise be unused in the text section. */ | |
2189 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
2190 asm (SECTION_OP "\n\t" \ | |
2191 "call " USER_LABEL_PREFIX #FUNC "\n" \ | |
2192 TEXT_SECTION_ASM_OP); | |
2193 | |
2194 /* Print operand X (an rtx) in assembler syntax to file FILE. | |
2195 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2196 Effect of various CODE letters is described in i386.c near | |
2197 print_operand function. */ | |
2198 | |
2199 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ | |
2200 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&' || (CODE) == ';') | |
2201 | |
2202 #define PRINT_OPERAND(FILE, X, CODE) \ | |
2203 print_operand ((FILE), (X), (CODE)) | |
2204 | |
2205 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ | |
2206 print_operand_address ((FILE), (ADDR)) | |
2207 | |
2208 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ | |
2209 do { \ | |
2210 if (! output_addr_const_extra (FILE, (X))) \ | |
2211 goto FAIL; \ | |
2212 } while (0); | |
2213 | |
2214 /* Which processor to schedule for. The cpu attribute defines a list that | |
2215 mirrors this list, so changes to i386.md must be made at the same time. */ | |
2216 | |
2217 enum processor_type | |
2218 { | |
2219 PROCESSOR_I386 = 0, /* 80386 */ | |
2220 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ | |
2221 PROCESSOR_PENTIUM, | |
2222 PROCESSOR_PENTIUMPRO, | |
2223 PROCESSOR_GEODE, | |
2224 PROCESSOR_K6, | |
2225 PROCESSOR_ATHLON, | |
2226 PROCESSOR_PENTIUM4, | |
2227 PROCESSOR_K8, | |
2228 PROCESSOR_NOCONA, | |
2229 PROCESSOR_CORE2, | |
2230 PROCESSOR_GENERIC32, | |
2231 PROCESSOR_GENERIC64, | |
2232 PROCESSOR_AMDFAM10, | |
2233 PROCESSOR_max | |
2234 }; | |
2235 | |
2236 extern enum processor_type ix86_tune; | |
2237 extern enum processor_type ix86_arch; | |
2238 | |
2239 enum fpmath_unit | |
2240 { | |
2241 FPMATH_387 = 1, | |
2242 FPMATH_SSE = 2 | |
2243 }; | |
2244 | |
2245 extern enum fpmath_unit ix86_fpmath; | |
2246 | |
2247 enum tls_dialect | |
2248 { | |
2249 TLS_DIALECT_GNU, | |
2250 TLS_DIALECT_GNU2, | |
2251 TLS_DIALECT_SUN | |
2252 }; | |
2253 | |
2254 extern enum tls_dialect ix86_tls_dialect; | |
2255 | |
2256 enum cmodel { | |
2257 CM_32, /* The traditional 32-bit ABI. */ | |
2258 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ | |
2259 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ | |
2260 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ | |
2261 CM_LARGE, /* No assumptions. */ | |
2262 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */ | |
2263 CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */ | |
2264 CM_LARGE_PIC /* No assumptions. */ | |
2265 }; | |
2266 | |
2267 extern enum cmodel ix86_cmodel; | |
2268 | |
2269 /* Size of the RED_ZONE area. */ | |
2270 #define RED_ZONE_SIZE 128 | |
2271 /* Reserved area of the red zone for temporaries. */ | |
2272 #define RED_ZONE_RESERVE 8 | |
2273 | |
2274 enum asm_dialect { | |
2275 ASM_ATT, | |
2276 ASM_INTEL | |
2277 }; | |
2278 | |
2279 extern enum asm_dialect ix86_asm_dialect; | |
2280 extern unsigned int ix86_preferred_stack_boundary; | |
2281 extern unsigned int ix86_incoming_stack_boundary; | |
2282 extern int ix86_branch_cost, ix86_section_threshold; | |
2283 | |
2284 /* Smallest class containing REGNO. */ | |
2285 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; | |
2286 | |
2287 extern rtx ix86_compare_op0; /* operand 0 for comparisons */ | |
2288 extern rtx ix86_compare_op1; /* operand 1 for comparisons */ | |
2289 extern rtx ix86_compare_emitted; | |
2290 | |
2291 /* To properly truncate FP values into integers, we need to set i387 control | |
2292 word. We can't emit proper mode switching code before reload, as spills | |
2293 generated by reload may truncate values incorrectly, but we still can avoid | |
2294 redundant computation of new control word by the mode switching pass. | |
2295 The fldcw instructions are still emitted redundantly, but this is probably | |
2296 not going to be noticeable problem, as most CPUs do have fast path for | |
2297 the sequence. | |
2298 | |
2299 The machinery is to emit simple truncation instructions and split them | |
2300 before reload to instructions having USEs of two memory locations that | |
2301 are filled by this code to old and new control word. | |
2302 | |
2303 Post-reload pass may be later used to eliminate the redundant fildcw if | |
2304 needed. */ | |
2305 | |
2306 enum ix86_entity | |
2307 { | |
2308 I387_TRUNC = 0, | |
2309 I387_FLOOR, | |
2310 I387_CEIL, | |
2311 I387_MASK_PM, | |
2312 MAX_386_ENTITIES | |
2313 }; | |
2314 | |
2315 enum ix86_stack_slot | |
2316 { | |
2317 SLOT_VIRTUAL = 0, | |
2318 SLOT_TEMP, | |
2319 SLOT_CW_STORED, | |
2320 SLOT_CW_TRUNC, | |
2321 SLOT_CW_FLOOR, | |
2322 SLOT_CW_CEIL, | |
2323 SLOT_CW_MASK_PM, | |
2324 MAX_386_STACK_LOCALS | |
2325 }; | |
2326 | |
2327 /* Define this macro if the port needs extra instructions inserted | |
2328 for mode switching in an optimizing compilation. */ | |
2329 | |
2330 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ | |
2331 ix86_optimize_mode_switching[(ENTITY)] | |
2332 | |
2333 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as | |
2334 initializer for an array of integers. Each initializer element N | |
2335 refers to an entity that needs mode switching, and specifies the | |
2336 number of different modes that might need to be set for this | |
2337 entity. The position of the initializer in the initializer - | |
2338 starting counting at zero - determines the integer that is used to | |
2339 refer to the mode-switched entity in question. */ | |
2340 | |
2341 #define NUM_MODES_FOR_MODE_SWITCHING \ | |
2342 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } | |
2343 | |
2344 /* ENTITY is an integer specifying a mode-switched entity. If | |
2345 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to | |
2346 return an integer value not larger than the corresponding element | |
2347 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY | |
2348 must be switched into prior to the execution of INSN. */ | |
2349 | |
2350 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I)) | |
2351 | |
2352 /* This macro specifies the order in which modes for ENTITY are | |
2353 processed. 0 is the highest priority. */ | |
2354 | |
2355 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) | |
2356 | |
2357 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE | |
2358 is the set of hard registers live at the point where the insn(s) | |
2359 are to be inserted. */ | |
2360 | |
2361 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ | |
2362 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \ | |
2363 ? emit_i387_cw_initialization (MODE), 0 \ | |
2364 : 0) | |
2365 | |
2366 | |
2367 /* Avoid renaming of stack registers, as doing so in combination with | |
2368 scheduling just increases amount of live registers at time and in | |
2369 the turn amount of fxch instructions needed. | |
2370 | |
2371 ??? Maybe Pentium chips benefits from renaming, someone can try.... */ | |
2372 | |
2373 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ | |
2374 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG)) | |
2375 | |
2376 | |
2377 #define FASTCALL_PREFIX '@' | |
2378 | |
2379 struct machine_function GTY(()) | |
2380 { | |
2381 struct stack_local_entry *stack_locals; | |
2382 const char *some_ld_name; | |
2383 int varargs_gpr_size; | |
2384 int varargs_fpr_size; | |
2385 int accesses_prev_frame; | |
2386 int optimize_mode_switching[MAX_386_ENTITIES]; | |
2387 int needs_cld; | |
2388 /* Set by ix86_compute_frame_layout and used by prologue/epilogue | |
2389 expander to determine the style used. */ | |
2390 int use_fast_prologue_epilogue; | |
2391 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed | |
2392 for. */ | |
2393 int use_fast_prologue_epilogue_nregs; | |
2394 /* If true, the current function needs the default PIC register, not | |
2395 an alternate register (on x86) and must not use the red zone (on | |
2396 x86_64), even if it's a leaf function. We don't want the | |
2397 function to be regarded as non-leaf because TLS calls need not | |
2398 affect register allocation. This flag is set when a TLS call | |
2399 instruction is expanded within a function, and never reset, even | |
2400 if all such instructions are optimized away. Use the | |
2401 ix86_current_function_calls_tls_descriptor macro for a better | |
2402 approximation. */ | |
2403 int tls_descriptor_call_expanded_p; | |
2404 /* This value is used for amd64 targets and specifies the current abi | |
2405 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ | |
2406 int call_abi; | |
2407 }; | |
2408 | |
2409 #define ix86_stack_locals (cfun->machine->stack_locals) | |
2410 #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) | |
2411 #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) | |
2412 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) | |
2413 #define ix86_current_function_needs_cld (cfun->machine->needs_cld) | |
2414 #define ix86_tls_descriptor_calls_expanded_in_cfun \ | |
2415 (cfun->machine->tls_descriptor_call_expanded_p) | |
2416 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS | |
2417 calls are optimized away, we try to detect cases in which it was | |
2418 optimized away. Since such instructions (use (reg REG_SP)), we can | |
2419 verify whether there's any such instruction live by testing that | |
2420 REG_SP is live. */ | |
2421 #define ix86_current_function_calls_tls_descriptor \ | |
2422 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) | |
2423 | |
2424 /* Control behavior of x86_file_start. */ | |
2425 #define X86_FILE_START_VERSION_DIRECTIVE false | |
2426 #define X86_FILE_START_FLTUSED false | |
2427 | |
2428 /* Flag to mark data that is in the large address area. */ | |
2429 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) | |
2430 #define SYMBOL_REF_FAR_ADDR_P(X) \ | |
2431 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) | |
2432 | |
2433 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to | |
2434 have defined always, to avoid ifdefing. */ | |
2435 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) | |
2436 #define SYMBOL_REF_DLLIMPORT_P(X) \ | |
2437 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) | |
2438 | |
2439 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) | |
2440 #define SYMBOL_REF_DLLEXPORT_P(X) \ | |
2441 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) | |
2442 | |
2443 /* Model costs for vectorizer. */ | |
2444 | |
2445 /* Cost of conditional branch. */ | |
2446 #undef TARG_COND_BRANCH_COST | |
2447 #define TARG_COND_BRANCH_COST ix86_cost->branch_cost | |
2448 | |
2449 /* Enum through the target specific extra va_list types. | |
2450 Please, do not iterate the base va_list type name. */ | |
2451 #define TARGET_ENUM_VA_LIST(IDX, PNAME, PTYPE) \ | |
2452 (TARGET_64BIT ? ix86_enum_va_list (IDX, PNAME, PTYPE) : 0) | |
2453 | |
2454 /* Cost of any scalar operation, excluding load and store. */ | |
2455 #undef TARG_SCALAR_STMT_COST | |
2456 #define TARG_SCALAR_STMT_COST ix86_cost->scalar_stmt_cost | |
2457 | |
2458 /* Cost of scalar load. */ | |
2459 #undef TARG_SCALAR_LOAD_COST | |
2460 #define TARG_SCALAR_LOAD_COST ix86_cost->scalar_load_cost | |
2461 | |
2462 /* Cost of scalar store. */ | |
2463 #undef TARG_SCALAR_STORE_COST | |
2464 #define TARG_SCALAR_STORE_COST ix86_cost->scalar_store_cost | |
2465 | |
2466 /* Cost of any vector operation, excluding load, store or vector to scalar | |
2467 operation. */ | |
2468 #undef TARG_VEC_STMT_COST | |
2469 #define TARG_VEC_STMT_COST ix86_cost->vec_stmt_cost | |
2470 | |
2471 /* Cost of vector to scalar operation. */ | |
2472 #undef TARG_VEC_TO_SCALAR_COST | |
2473 #define TARG_VEC_TO_SCALAR_COST ix86_cost->vec_to_scalar_cost | |
2474 | |
2475 /* Cost of scalar to vector operation. */ | |
2476 #undef TARG_SCALAR_TO_VEC_COST | |
2477 #define TARG_SCALAR_TO_VEC_COST ix86_cost->scalar_to_vec_cost | |
2478 | |
2479 /* Cost of aligned vector load. */ | |
2480 #undef TARG_VEC_LOAD_COST | |
2481 #define TARG_VEC_LOAD_COST ix86_cost->vec_align_load_cost | |
2482 | |
2483 /* Cost of misaligned vector load. */ | |
2484 #undef TARG_VEC_UNALIGNED_LOAD_COST | |
2485 #define TARG_VEC_UNALIGNED_LOAD_COST ix86_cost->vec_unalign_load_cost | |
2486 | |
2487 /* Cost of vector store. */ | |
2488 #undef TARG_VEC_STORE_COST | |
2489 #define TARG_VEC_STORE_COST ix86_cost->vec_store_cost | |
2490 | |
2491 /* Cost of conditional taken branch for vectorizer cost model. */ | |
2492 #undef TARG_COND_TAKEN_BRANCH_COST | |
2493 #define TARG_COND_TAKEN_BRANCH_COST ix86_cost->cond_taken_branch_cost | |
2494 | |
2495 /* Cost of conditional not taken branch for vectorizer cost model. */ | |
2496 #undef TARG_COND_NOT_TAKEN_BRANCH_COST | |
2497 #define TARG_COND_NOT_TAKEN_BRANCH_COST ix86_cost->cond_not_taken_branch_cost | |
2498 | |
2499 /* | |
2500 Local variables: | |
2501 version-control: t | |
2502 End: | |
2503 */ |