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1 /*
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2 * Copyright (C) 2007, 2008, 2009 Free Software Foundation, Inc.
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3 *
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4 * This file is free software; you can redistribute it and/or modify it
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5 * under the terms of the GNU General Public License as published by the
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6 * Free Software Foundation; either version 3, or (at your option) any
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7 * later version.
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8 *
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9 * This file is distributed in the hope that it will be useful, but
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10 * WITHOUT ANY WARRANTY; without even the implied warranty of
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11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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12 * General Public License for more details.
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13 *
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14 * Under Section 7 of GPL version 3, you are granted additional
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15 * permissions described in the GCC Runtime Library Exception, version
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16 * 3.1, as published by the Free Software Foundation.
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17 *
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18 * You should have received a copy of the GNU General Public License and
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19 * a copy of the GCC Runtime Library Exception along with this program;
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20 * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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21 * <http://www.gnu.org/licenses/>.
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22 */
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23
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24 /* %ecx */
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25 #define bit_SSE3 (1 << 0)
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26 #define bit_PCLMUL (1 << 1)
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27 #define bit_SSSE3 (1 << 9)
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28 #define bit_FMA (1 << 12)
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29 #define bit_CMPXCHG16B (1 << 13)
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30 #define bit_SSE4_1 (1 << 19)
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31 #define bit_SSE4_2 (1 << 20)
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32 #define bit_POPCNT (1 << 23)
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33 #define bit_AES (1 << 25)
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34 #define bit_XSAVE (1 << 26)
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35 #define bit_OSXSAVE (1 << 27)
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36 #define bit_AVX (1 << 28)
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37
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38 /* %edx */
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39 #define bit_CMPXCHG8B (1 << 8)
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40 #define bit_CMOV (1 << 15)
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41 #define bit_MMX (1 << 23)
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42 #define bit_FXSAVE (1 << 24)
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43 #define bit_SSE (1 << 25)
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44 #define bit_SSE2 (1 << 26)
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45
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46 /* Extended Features */
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47 /* %ecx */
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48 #define bit_LAHF_LM (1 << 0)
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49 #define bit_SSE4a (1 << 6)
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50 #define bit_SSE5 (1 << 11)
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51
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52 /* %edx */
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53 #define bit_LM (1 << 29)
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54 #define bit_3DNOWP (1 << 30)
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55 #define bit_3DNOW (1 << 31)
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56
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57
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58 #if defined(__i386__) && defined(__PIC__)
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59 /* %ebx may be the PIC register. */
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60 #if __GNUC__ >= 3
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61 #define __cpuid(level, a, b, c, d) \
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62 __asm__ ("xchg{l}\t{%%}ebx, %1\n\t" \
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63 "cpuid\n\t" \
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64 "xchg{l}\t{%%}ebx, %1\n\t" \
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65 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \
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66 : "0" (level))
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67
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68 #define __cpuid_count(level, count, a, b, c, d) \
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69 __asm__ ("xchg{l}\t{%%}ebx, %1\n\t" \
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70 "cpuid\n\t" \
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71 "xchg{l}\t{%%}ebx, %1\n\t" \
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72 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \
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73 : "0" (level), "2" (count))
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74 #else
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75 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
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76 nor alternatives in i386 code. */
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77 #define __cpuid(level, a, b, c, d) \
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78 __asm__ ("xchgl\t%%ebx, %1\n\t" \
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79 "cpuid\n\t" \
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80 "xchgl\t%%ebx, %1\n\t" \
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81 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \
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82 : "0" (level))
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83
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84 #define __cpuid_count(level, count, a, b, c, d) \
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85 __asm__ ("xchgl\t%%ebx, %1\n\t" \
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86 "cpuid\n\t" \
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87 "xchgl\t%%ebx, %1\n\t" \
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88 : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \
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89 : "0" (level), "2" (count))
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90 #endif
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91 #else
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92 #define __cpuid(level, a, b, c, d) \
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93 __asm__ ("cpuid\n\t" \
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94 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
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95 : "0" (level))
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96
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97 #define __cpuid_count(level, count, a, b, c, d) \
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98 __asm__ ("cpuid\n\t" \
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99 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
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100 : "0" (level), "2" (count))
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101 #endif
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102
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103 /* Return highest supported input value for cpuid instruction. ext can
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104 be either 0x0 or 0x8000000 to return highest supported value for
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105 basic or extended cpuid information. Function returns 0 if cpuid
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106 is not supported or whatever cpuid returns in eax register. If sig
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107 pointer is non-null, then first four bytes of the signature
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108 (as found in ebx register) are returned in location pointed by sig. */
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109
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110 static __inline unsigned int
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111 __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
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112 {
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113 unsigned int __eax, __ebx, __ecx, __edx;
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114
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115 #ifndef __x86_64__
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116 #if __GNUC__ >= 3
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117 /* See if we can use cpuid. On AMD64 we always can. */
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118 __asm__ ("pushf{l|d}\n\t"
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119 "pushf{l|d}\n\t"
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120 "pop{l}\t%0\n\t"
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121 "mov{l}\t{%0, %1|%1, %0}\n\t"
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122 "xor{l}\t{%2, %0|%0, %2}\n\t"
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123 "push{l}\t%0\n\t"
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124 "popf{l|d}\n\t"
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125 "pushf{l|d}\n\t"
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126 "pop{l}\t%0\n\t"
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127 "popf{l|d}\n\t"
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128 : "=&r" (__eax), "=&r" (__ebx)
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129 : "i" (0x00200000));
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130 #else
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131 /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
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132 nor alternatives in i386 code. */
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133 __asm__ ("pushfl\n\t"
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134 "pushfl\n\t"
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135 "popl\t%0\n\t"
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136 "movl\t%0, %1\n\t"
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137 "xorl\t%2, %0\n\t"
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138 "pushl\t%0\n\t"
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139 "popfl\n\t"
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140 "pushfl\n\t"
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141 "popl\t%0\n\t"
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142 "popfl\n\t"
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143 : "=&r" (__eax), "=&r" (__ebx)
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144 : "i" (0x00200000));
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145 #endif
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146
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147 if (!((__eax ^ __ebx) & 0x00200000))
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148 return 0;
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149 #endif
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150
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151 /* Host supports cpuid. Return highest supported cpuid input value. */
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152 __cpuid (__ext, __eax, __ebx, __ecx, __edx);
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153
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154 if (__sig)
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155 *__sig = __ebx;
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156
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157 return __eax;
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158 }
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159
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160 /* Return cpuid data for requested cpuid level, as found in returned
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161 eax, ebx, ecx and edx registers. The function checks if cpuid is
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162 supported and returns 1 for valid cpuid information or 0 for
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163 unsupported cpuid level. All pointers are required to be non-null. */
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164
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165 static __inline int
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166 __get_cpuid (unsigned int __level,
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167 unsigned int *__eax, unsigned int *__ebx,
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168 unsigned int *__ecx, unsigned int *__edx)
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169 {
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170 unsigned int __ext = __level & 0x80000000;
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171
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172 if (__get_cpuid_max (__ext, 0) < __level)
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173 return 0;
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174
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175 __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx);
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176 return 1;
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177 }
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