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111
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1 /* LRA (local register allocator) driver and LRA utilities.
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131
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2 Copyright (C) 2010-2018 Free Software Foundation, Inc.
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111
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3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify it under
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8 the terms of the GNU General Public License as published by the Free
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9 Software Foundation; either version 3, or (at your option) any later
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10 version.
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11
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12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
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14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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15 for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21
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22 /* The Local Register Allocator (LRA) is a replacement of former
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23 reload pass. It is focused to simplify code solving the reload
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24 pass tasks, to make the code maintenance easier, and to implement new
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25 perspective optimizations.
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26
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27 The major LRA design solutions are:
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28 o division small manageable, separated sub-tasks
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29 o reflection of all transformations and decisions in RTL as more
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30 as possible
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31 o insn constraints as a primary source of the info (minimizing
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32 number of target-depended macros/hooks)
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33
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34 In brief LRA works by iterative insn process with the final goal is
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35 to satisfy all insn and address constraints:
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36 o New reload insns (in brief reloads) and reload pseudos might be
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37 generated;
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38 o Some pseudos might be spilled to assign hard registers to
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39 new reload pseudos;
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40 o Recalculating spilled pseudo values (rematerialization);
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41 o Changing spilled pseudos to stack memory or their equivalences;
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42 o Allocation stack memory changes the address displacement and
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43 new iteration is needed.
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44
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45 Here is block diagram of LRA passes:
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46
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47 ------------------------
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48 --------------- | Undo inheritance for | ---------------
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49 | Memory-memory | | spilled pseudos, | | New (and old) |
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50 | move coalesce |<---| splits for pseudos got |<-- | pseudos |
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51 --------------- | the same hard regs, | | assignment |
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52 Start | | and optional reloads | ---------------
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53 | | ------------------------ ^
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54 V | ---------------- |
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55 ----------- V | Update virtual | |
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56 | Remove |----> ------------>| register | |
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57 | scratches | ^ | displacements | |
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58 ----------- | ---------------- |
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59 | | |
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60 | V New |
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61 | ------------ pseudos -------------------
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62 | |Constraints:| or insns | Inheritance/split |
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63 | | RTL |--------->| transformations |
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64 | | transfor- | | in EBB scope |
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65 | substi- | mations | -------------------
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66 | tutions ------------
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67 | | No change
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68 ---------------- V
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69 | Spilled pseudo | -------------------
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70 | to memory |<----| Rematerialization |
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71 | substitution | -------------------
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72 ----------------
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73 | No susbtitions
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74 V
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75 -------------------------
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76 | Hard regs substitution, |
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77 | devirtalization, and |------> Finish
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78 | restoring scratches got |
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79 | memory |
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80 -------------------------
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81
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82 To speed up the process:
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83 o We process only insns affected by changes on previous
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84 iterations;
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85 o We don't use DFA-infrastructure because it results in much slower
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86 compiler speed than a special IR described below does;
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87 o We use a special insn representation for quick access to insn
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88 info which is always *synchronized* with the current RTL;
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89 o Insn IR is minimized by memory. It is divided on three parts:
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90 o one specific for each insn in RTL (only operand locations);
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91 o one common for all insns in RTL with the same insn code
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92 (different operand attributes from machine descriptions);
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93 o one oriented for maintenance of live info (list of pseudos).
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94 o Pseudo data:
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95 o all insns where the pseudo is referenced;
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96 o live info (conflicting hard regs, live ranges, # of
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97 references etc);
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98 o data used for assigning (preferred hard regs, costs etc).
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99
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100 This file contains LRA driver, LRA utility functions and data, and
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101 code for dealing with scratches. */
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102
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103 #include "config.h"
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104 #include "system.h"
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105 #include "coretypes.h"
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106 #include "backend.h"
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107 #include "target.h"
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108 #include "rtl.h"
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109 #include "tree.h"
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110 #include "predict.h"
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111 #include "df.h"
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112 #include "memmodel.h"
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113 #include "tm_p.h"
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114 #include "optabs.h"
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115 #include "regs.h"
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116 #include "ira.h"
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117 #include "recog.h"
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118 #include "expr.h"
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119 #include "cfgrtl.h"
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120 #include "cfgbuild.h"
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121 #include "lra.h"
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122 #include "lra-int.h"
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123 #include "print-rtl.h"
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124
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125 /* Dump bitmap SET with TITLE and BB INDEX. */
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126 void
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127 lra_dump_bitmap_with_title (const char *title, bitmap set, int index)
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128 {
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129 unsigned int i;
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130 int count;
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131 bitmap_iterator bi;
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132 static const int max_nums_on_line = 10;
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133
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134 if (bitmap_empty_p (set))
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135 return;
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136 fprintf (lra_dump_file, " %s %d:", title, index);
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137 fprintf (lra_dump_file, "\n");
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138 count = max_nums_on_line + 1;
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139 EXECUTE_IF_SET_IN_BITMAP (set, 0, i, bi)
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140 {
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141 if (count > max_nums_on_line)
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142 {
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143 fprintf (lra_dump_file, "\n ");
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144 count = 0;
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145 }
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146 fprintf (lra_dump_file, " %4u", i);
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147 count++;
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148 }
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149 fprintf (lra_dump_file, "\n");
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150 }
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151
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152 /* Hard registers currently not available for allocation. It can
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153 changed after some hard registers become not eliminable. */
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154 HARD_REG_SET lra_no_alloc_regs;
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155
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156 static int get_new_reg_value (void);
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157 static void expand_reg_info (void);
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158 static void invalidate_insn_recog_data (int);
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159 static int get_insn_freq (rtx_insn *);
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160 static void invalidate_insn_data_regno_info (lra_insn_recog_data_t,
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161 rtx_insn *, int);
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162
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163 /* Expand all regno related info needed for LRA. */
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164 static void
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165 expand_reg_data (int old)
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166 {
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167 resize_reg_info ();
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168 expand_reg_info ();
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169 ira_expand_reg_equiv ();
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170 for (int i = (int) max_reg_num () - 1; i >= old; i--)
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171 lra_change_class (i, ALL_REGS, " Set", true);
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172 }
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173
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174 /* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL
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175 or of VOIDmode, use MD_MODE for the new reg. Initialize its
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176 register class to RCLASS. Print message about assigning class
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177 RCLASS containing new register name TITLE unless it is NULL. Use
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178 attributes of ORIGINAL if it is a register. The created register
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179 will have unique held value. */
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180 rtx
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181 lra_create_new_reg_with_unique_value (machine_mode md_mode, rtx original,
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182 enum reg_class rclass, const char *title)
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183 {
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184 machine_mode mode;
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185 rtx new_reg;
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186
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187 if (original == NULL_RTX || (mode = GET_MODE (original)) == VOIDmode)
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188 mode = md_mode;
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189 lra_assert (mode != VOIDmode);
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190 new_reg = gen_reg_rtx (mode);
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191 if (original == NULL_RTX || ! REG_P (original))
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192 {
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193 if (lra_dump_file != NULL)
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194 fprintf (lra_dump_file, " Creating newreg=%i", REGNO (new_reg));
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195 }
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196 else
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197 {
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198 if (ORIGINAL_REGNO (original) >= FIRST_PSEUDO_REGISTER)
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199 ORIGINAL_REGNO (new_reg) = ORIGINAL_REGNO (original);
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200 REG_USERVAR_P (new_reg) = REG_USERVAR_P (original);
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201 REG_POINTER (new_reg) = REG_POINTER (original);
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202 REG_ATTRS (new_reg) = REG_ATTRS (original);
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203 if (lra_dump_file != NULL)
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204 fprintf (lra_dump_file, " Creating newreg=%i from oldreg=%i",
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205 REGNO (new_reg), REGNO (original));
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206 }
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207 if (lra_dump_file != NULL)
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208 {
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209 if (title != NULL)
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210 fprintf (lra_dump_file, ", assigning class %s to%s%s r%d",
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211 reg_class_names[rclass], *title == '\0' ? "" : " ",
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212 title, REGNO (new_reg));
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213 fprintf (lra_dump_file, "\n");
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214 }
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215 expand_reg_data (max_reg_num ());
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216 setup_reg_classes (REGNO (new_reg), rclass, NO_REGS, rclass);
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217 return new_reg;
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218 }
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219
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220 /* Analogous to the previous function but also inherits value of
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221 ORIGINAL. */
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222 rtx
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223 lra_create_new_reg (machine_mode md_mode, rtx original,
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224 enum reg_class rclass, const char *title)
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225 {
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226 rtx new_reg;
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227
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228 new_reg
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229 = lra_create_new_reg_with_unique_value (md_mode, original, rclass, title);
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230 if (original != NULL_RTX && REG_P (original))
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231 lra_assign_reg_val (REGNO (original), REGNO (new_reg));
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232 return new_reg;
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233 }
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234
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235 /* Set up for REGNO unique hold value. */
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236 void
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237 lra_set_regno_unique_value (int regno)
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238 {
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239 lra_reg_info[regno].val = get_new_reg_value ();
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240 }
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241
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242 /* Invalidate INSN related info used by LRA. The info should never be
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243 used after that. */
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244 void
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245 lra_invalidate_insn_data (rtx_insn *insn)
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246 {
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247 lra_invalidate_insn_regno_info (insn);
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248 invalidate_insn_recog_data (INSN_UID (insn));
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249 }
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250
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251 /* Mark INSN deleted and invalidate the insn related info used by
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252 LRA. */
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253 void
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254 lra_set_insn_deleted (rtx_insn *insn)
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255 {
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256 lra_invalidate_insn_data (insn);
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257 SET_INSN_DELETED (insn);
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258 }
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259
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260 /* Delete an unneeded INSN and any previous insns who sole purpose is
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261 loading data that is dead in INSN. */
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262 void
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263 lra_delete_dead_insn (rtx_insn *insn)
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264 {
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265 rtx_insn *prev = prev_real_insn (insn);
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266 rtx prev_dest;
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267
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268 /* If the previous insn sets a register that dies in our insn,
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269 delete it too. */
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270 if (prev && GET_CODE (PATTERN (prev)) == SET
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271 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
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272 && reg_mentioned_p (prev_dest, PATTERN (insn))
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273 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
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274 && ! side_effects_p (SET_SRC (PATTERN (prev))))
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275 lra_delete_dead_insn (prev);
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276
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277 lra_set_insn_deleted (insn);
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278 }
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279
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280 /* Emit insn x = y + z. Return NULL if we failed to do it.
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281 Otherwise, return the insn. We don't use gen_add3_insn as it might
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282 clobber CC. */
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283 static rtx_insn *
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284 emit_add3_insn (rtx x, rtx y, rtx z)
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285 {
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286 rtx_insn *last;
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287
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288 last = get_last_insn ();
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289
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290 if (have_addptr3_insn (x, y, z))
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291 {
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292 rtx_insn *insn = gen_addptr3_insn (x, y, z);
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293
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294 /* If the target provides an "addptr" pattern it hopefully does
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295 for a reason. So falling back to the normal add would be
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296 a bug. */
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297 lra_assert (insn != NULL_RTX);
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298 emit_insn (insn);
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299 return insn;
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300 }
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301
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302 rtx_insn *insn = emit_insn (gen_rtx_SET (x, gen_rtx_PLUS (GET_MODE (y),
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303 y, z)));
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304 if (recog_memoized (insn) < 0)
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305 {
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306 delete_insns_since (last);
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307 insn = NULL;
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308 }
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309 return insn;
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310 }
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311
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312 /* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the
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313 last resort. */
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314 static rtx_insn *
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315 emit_add2_insn (rtx x, rtx y)
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316 {
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317 rtx_insn *insn = emit_add3_insn (x, x, y);
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318 if (insn == NULL_RTX)
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319 {
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320 insn = gen_add2_insn (x, y);
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321 if (insn != NULL_RTX)
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322 emit_insn (insn);
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323 }
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324 return insn;
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325 }
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326
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327 /* Target checks operands through operand predicates to recognize an
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328 insn. We should have a special precaution to generate add insns
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329 which are frequent results of elimination.
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330
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331 Emit insns for x = y + z. X can be used to store intermediate
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332 values and should be not in Y and Z when we use X to store an
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333 intermediate value. Y + Z should form [base] [+ index[ * scale]] [
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334 + disp] where base and index are registers, disp and scale are
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335 constants. Y should contain base if it is present, Z should
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336 contain disp if any. index[*scale] can be part of Y or Z. */
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337 void
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338 lra_emit_add (rtx x, rtx y, rtx z)
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339 {
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340 int old;
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341 rtx_insn *last;
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342 rtx a1, a2, base, index, disp, scale, index_scale;
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343 bool ok_p;
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344
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345 rtx_insn *add3_insn = emit_add3_insn (x, y, z);
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346 old = max_reg_num ();
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347 if (add3_insn != NULL)
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348 ;
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349 else
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350 {
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351 disp = a2 = NULL_RTX;
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352 if (GET_CODE (y) == PLUS)
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353 {
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354 a1 = XEXP (y, 0);
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355 a2 = XEXP (y, 1);
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356 disp = z;
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357 }
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358 else
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359 {
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360 a1 = y;
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361 if (CONSTANT_P (z))
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362 disp = z;
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363 else
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364 a2 = z;
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365 }
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366 index_scale = scale = NULL_RTX;
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367 if (GET_CODE (a1) == MULT)
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368 {
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369 index_scale = a1;
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370 index = XEXP (a1, 0);
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371 scale = XEXP (a1, 1);
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372 base = a2;
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373 }
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374 else if (a2 != NULL_RTX && GET_CODE (a2) == MULT)
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375 {
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376 index_scale = a2;
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377 index = XEXP (a2, 0);
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378 scale = XEXP (a2, 1);
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379 base = a1;
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380 }
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381 else
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382 {
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383 base = a1;
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384 index = a2;
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385 }
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386 if ((base != NULL_RTX && ! (REG_P (base) || GET_CODE (base) == SUBREG))
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387 || (index != NULL_RTX
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388 && ! (REG_P (index) || GET_CODE (index) == SUBREG))
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389 || (disp != NULL_RTX && ! CONSTANT_P (disp))
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390 || (scale != NULL_RTX && ! CONSTANT_P (scale)))
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391 {
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392 /* Probably we have no 3 op add. Last chance is to use 2-op
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393 add insn. To succeed, don't move Z to X as an address
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|
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394 segment always comes in Y. Otherwise, we might fail when
|
|
|
395 adding the address segment to register. */
|
|
|
396 lra_assert (x != y && x != z);
|
|
|
397 emit_move_insn (x, y);
|
|
|
398 rtx_insn *insn = emit_add2_insn (x, z);
|
|
|
399 lra_assert (insn != NULL_RTX);
|
|
|
400 }
|
|
|
401 else
|
|
|
402 {
|
|
|
403 if (index_scale == NULL_RTX)
|
|
|
404 index_scale = index;
|
|
|
405 if (disp == NULL_RTX)
|
|
|
406 {
|
|
|
407 /* Generate x = index_scale; x = x + base. */
|
|
|
408 lra_assert (index_scale != NULL_RTX && base != NULL_RTX);
|
|
|
409 emit_move_insn (x, index_scale);
|
|
|
410 rtx_insn *insn = emit_add2_insn (x, base);
|
|
|
411 lra_assert (insn != NULL_RTX);
|
|
|
412 }
|
|
|
413 else if (scale == NULL_RTX)
|
|
|
414 {
|
|
|
415 /* Try x = base + disp. */
|
|
|
416 lra_assert (base != NULL_RTX);
|
|
|
417 last = get_last_insn ();
|
|
|
418 rtx_insn *move_insn =
|
|
|
419 emit_move_insn (x, gen_rtx_PLUS (GET_MODE (base), base, disp));
|
|
|
420 if (recog_memoized (move_insn) < 0)
|
|
|
421 {
|
|
|
422 delete_insns_since (last);
|
|
|
423 /* Generate x = disp; x = x + base. */
|
|
|
424 emit_move_insn (x, disp);
|
|
|
425 rtx_insn *add2_insn = emit_add2_insn (x, base);
|
|
|
426 lra_assert (add2_insn != NULL_RTX);
|
|
|
427 }
|
|
|
428 /* Generate x = x + index. */
|
|
|
429 if (index != NULL_RTX)
|
|
|
430 {
|
|
|
431 rtx_insn *insn = emit_add2_insn (x, index);
|
|
|
432 lra_assert (insn != NULL_RTX);
|
|
|
433 }
|
|
|
434 }
|
|
|
435 else
|
|
|
436 {
|
|
|
437 /* Try x = index_scale; x = x + disp; x = x + base. */
|
|
|
438 last = get_last_insn ();
|
|
|
439 rtx_insn *move_insn = emit_move_insn (x, index_scale);
|
|
|
440 ok_p = false;
|
|
|
441 if (recog_memoized (move_insn) >= 0)
|
|
|
442 {
|
|
|
443 rtx_insn *insn = emit_add2_insn (x, disp);
|
|
|
444 if (insn != NULL_RTX)
|
|
|
445 {
|
|
|
446 if (base == NULL_RTX)
|
|
|
447 ok_p = true;
|
|
|
448 else
|
|
|
449 {
|
|
|
450 insn = emit_add2_insn (x, base);
|
|
|
451 if (insn != NULL_RTX)
|
|
|
452 ok_p = true;
|
|
|
453 }
|
|
|
454 }
|
|
|
455 }
|
|
|
456 if (! ok_p)
|
|
|
457 {
|
|
|
458 rtx_insn *insn;
|
|
|
459
|
|
|
460 delete_insns_since (last);
|
|
|
461 /* Generate x = disp; x = x + base; x = x + index_scale. */
|
|
|
462 emit_move_insn (x, disp);
|
|
|
463 if (base != NULL_RTX)
|
|
|
464 {
|
|
|
465 insn = emit_add2_insn (x, base);
|
|
|
466 lra_assert (insn != NULL_RTX);
|
|
|
467 }
|
|
|
468 insn = emit_add2_insn (x, index_scale);
|
|
|
469 lra_assert (insn != NULL_RTX);
|
|
|
470 }
|
|
|
471 }
|
|
|
472 }
|
|
|
473 }
|
|
|
474 /* Functions emit_... can create pseudos -- so expand the pseudo
|
|
|
475 data. */
|
|
|
476 if (old != max_reg_num ())
|
|
|
477 expand_reg_data (old);
|
|
|
478 }
|
|
|
479
|
|
|
480 /* The number of emitted reload insns so far. */
|
|
|
481 int lra_curr_reload_num;
|
|
|
482
|
|
|
483 /* Emit x := y, processing special case when y = u + v or y = u + v *
|
|
|
484 scale + w through emit_add (Y can be an address which is base +
|
|
|
485 index reg * scale + displacement in general case). X may be used
|
|
|
486 as intermediate result therefore it should be not in Y. */
|
|
|
487 void
|
|
|
488 lra_emit_move (rtx x, rtx y)
|
|
|
489 {
|
|
|
490 int old;
|
|
|
491
|
|
|
492 if (GET_CODE (y) != PLUS)
|
|
|
493 {
|
|
|
494 if (rtx_equal_p (x, y))
|
|
|
495 return;
|
|
|
496 old = max_reg_num ();
|
|
|
497 emit_move_insn (x, y);
|
|
|
498 if (REG_P (x))
|
|
|
499 lra_reg_info[ORIGINAL_REGNO (x)].last_reload = ++lra_curr_reload_num;
|
|
|
500 /* Function emit_move can create pseudos -- so expand the pseudo
|
|
|
501 data. */
|
|
|
502 if (old != max_reg_num ())
|
|
|
503 expand_reg_data (old);
|
|
|
504 return;
|
|
|
505 }
|
|
|
506 lra_emit_add (x, XEXP (y, 0), XEXP (y, 1));
|
|
|
507 }
|
|
|
508
|
|
|
509 /* Update insn operands which are duplication of operands whose
|
|
|
510 numbers are in array of NOPS (with end marker -1). The insn is
|
|
|
511 represented by its LRA internal representation ID. */
|
|
|
512 void
|
|
|
513 lra_update_dups (lra_insn_recog_data_t id, signed char *nops)
|
|
|
514 {
|
|
|
515 int i, j, nop;
|
|
|
516 struct lra_static_insn_data *static_id = id->insn_static_data;
|
|
|
517
|
|
|
518 for (i = 0; i < static_id->n_dups; i++)
|
|
|
519 for (j = 0; (nop = nops[j]) >= 0; j++)
|
|
|
520 if (static_id->dup_num[i] == nop)
|
|
|
521 *id->dup_loc[i] = *id->operand_loc[nop];
|
|
|
522 }
|
|
|
523
|
|
|
524
|
|
|
525
|
|
|
526 /* This page contains code dealing with info about registers in the
|
|
|
527 insns. */
|
|
|
528
|
|
|
529 /* Pools for insn reg info. */
|
|
|
530 object_allocator<lra_insn_reg> lra_insn_reg_pool ("insn regs");
|
|
|
531
|
|
|
532 /* Create LRA insn related info about a reference to REGNO in INSN
|
|
|
533 with TYPE (in/out/inout), biggest reference mode MODE, flag that it
|
|
|
534 is reference through subreg (SUBREG_P), flag that is early
|
|
|
535 clobbered in the insn (EARLY_CLOBBER), and reference to the next
|
|
|
536 insn reg info (NEXT). If REGNO can be early clobbered,
|
|
|
537 alternatives in which it can be early clobbered are given by
|
|
131
|
538 EARLY_CLOBBER_ALTS. CLOBBER_HIGH marks if reference is a clobber
|
|
|
539 high. */
|
|
111
|
540 static struct lra_insn_reg *
|
|
|
541 new_insn_reg (rtx_insn *insn, int regno, enum op_type type,
|
|
|
542 machine_mode mode,
|
|
|
543 bool subreg_p, bool early_clobber,
|
|
|
544 alternative_mask early_clobber_alts,
|
|
131
|
545 struct lra_insn_reg *next, bool clobber_high)
|
|
111
|
546 {
|
|
|
547 lra_insn_reg *ir = lra_insn_reg_pool.allocate ();
|
|
|
548 ir->type = type;
|
|
|
549 ir->biggest_mode = mode;
|
|
|
550 if (NONDEBUG_INSN_P (insn)
|
|
|
551 && partial_subreg_p (lra_reg_info[regno].biggest_mode, mode))
|
|
|
552 lra_reg_info[regno].biggest_mode = mode;
|
|
|
553 ir->subreg_p = subreg_p;
|
|
|
554 ir->early_clobber = early_clobber;
|
|
|
555 ir->early_clobber_alts = early_clobber_alts;
|
|
131
|
556 ir->clobber_high = clobber_high;
|
|
111
|
557 ir->regno = regno;
|
|
|
558 ir->next = next;
|
|
|
559 return ir;
|
|
|
560 }
|
|
|
561
|
|
|
562 /* Free insn reg info list IR. */
|
|
|
563 static void
|
|
|
564 free_insn_regs (struct lra_insn_reg *ir)
|
|
|
565 {
|
|
|
566 struct lra_insn_reg *next_ir;
|
|
|
567
|
|
|
568 for (; ir != NULL; ir = next_ir)
|
|
|
569 {
|
|
|
570 next_ir = ir->next;
|
|
|
571 lra_insn_reg_pool.remove (ir);
|
|
|
572 }
|
|
|
573 }
|
|
|
574
|
|
|
575 /* Finish pool for insn reg info. */
|
|
|
576 static void
|
|
|
577 finish_insn_regs (void)
|
|
|
578 {
|
|
|
579 lra_insn_reg_pool.release ();
|
|
|
580 }
|
|
|
581
|
|
|
582
|
|
|
583
|
|
|
584 /* This page contains code dealing LRA insn info (or in other words
|
|
|
585 LRA internal insn representation). */
|
|
|
586
|
|
|
587 /* Map INSN_CODE -> the static insn data. This info is valid during
|
|
|
588 all translation unit. */
|
|
|
589 struct lra_static_insn_data *insn_code_data[NUM_INSN_CODES];
|
|
|
590
|
|
|
591 /* Debug insns are represented as a special insn with one input
|
|
|
592 operand which is RTL expression in var_location. */
|
|
|
593
|
|
|
594 /* The following data are used as static insn operand data for all
|
|
|
595 debug insns. If structure lra_operand_data is changed, the
|
|
|
596 initializer should be changed too. */
|
|
|
597 static struct lra_operand_data debug_operand_data =
|
|
|
598 {
|
|
|
599 NULL, /* alternative */
|
|
|
600 0, /* early_clobber_alts */
|
|
|
601 E_VOIDmode, /* We are not interesting in the operand mode. */
|
|
|
602 OP_IN,
|
|
|
603 0, 0, 0, 0
|
|
|
604 };
|
|
|
605
|
|
|
606 /* The following data are used as static insn data for all debug
|
|
131
|
607 bind insns. If structure lra_static_insn_data is changed, the
|
|
111
|
608 initializer should be changed too. */
|
|
131
|
609 static struct lra_static_insn_data debug_bind_static_data =
|
|
111
|
610 {
|
|
|
611 &debug_operand_data,
|
|
|
612 0, /* Duplication operands #. */
|
|
|
613 -1, /* Commutative operand #. */
|
|
|
614 1, /* Operands #. There is only one operand which is debug RTL
|
|
|
615 expression. */
|
|
|
616 0, /* Duplications #. */
|
|
|
617 0, /* Alternatives #. We are not interesting in alternatives
|
|
|
618 because we does not proceed debug_insns for reloads. */
|
|
|
619 NULL, /* Hard registers referenced in machine description. */
|
|
|
620 NULL /* Descriptions of operands in alternatives. */
|
|
|
621 };
|
|
|
622
|
|
131
|
623 /* The following data are used as static insn data for all debug
|
|
|
624 marker insns. If structure lra_static_insn_data is changed, the
|
|
|
625 initializer should be changed too. */
|
|
|
626 static struct lra_static_insn_data debug_marker_static_data =
|
|
|
627 {
|
|
|
628 &debug_operand_data,
|
|
|
629 0, /* Duplication operands #. */
|
|
|
630 -1, /* Commutative operand #. */
|
|
|
631 0, /* Operands #. There isn't any operand. */
|
|
|
632 0, /* Duplications #. */
|
|
|
633 0, /* Alternatives #. We are not interesting in alternatives
|
|
|
634 because we does not proceed debug_insns for reloads. */
|
|
|
635 NULL, /* Hard registers referenced in machine description. */
|
|
|
636 NULL /* Descriptions of operands in alternatives. */
|
|
|
637 };
|
|
|
638
|
|
111
|
639 /* Called once per compiler work to initialize some LRA data related
|
|
|
640 to insns. */
|
|
|
641 static void
|
|
|
642 init_insn_code_data_once (void)
|
|
|
643 {
|
|
|
644 memset (insn_code_data, 0, sizeof (insn_code_data));
|
|
|
645 }
|
|
|
646
|
|
|
647 /* Called once per compiler work to finalize some LRA data related to
|
|
|
648 insns. */
|
|
|
649 static void
|
|
|
650 finish_insn_code_data_once (void)
|
|
|
651 {
|
|
|
652 for (unsigned int i = 0; i < NUM_INSN_CODES; i++)
|
|
|
653 {
|
|
|
654 if (insn_code_data[i] != NULL)
|
|
|
655 free (insn_code_data[i]);
|
|
|
656 }
|
|
|
657 }
|
|
|
658
|
|
|
659 /* Return static insn data, allocate and setup if necessary. Although
|
|
|
660 dup_num is static data (it depends only on icode), to set it up we
|
|
|
661 need to extract insn first. So recog_data should be valid for
|
|
|
662 normal insn (ICODE >= 0) before the call. */
|
|
|
663 static struct lra_static_insn_data *
|
|
|
664 get_static_insn_data (int icode, int nop, int ndup, int nalt)
|
|
|
665 {
|
|
|
666 struct lra_static_insn_data *data;
|
|
|
667 size_t n_bytes;
|
|
|
668
|
|
|
669 lra_assert (icode < (int) NUM_INSN_CODES);
|
|
|
670 if (icode >= 0 && (data = insn_code_data[icode]) != NULL)
|
|
|
671 return data;
|
|
|
672 lra_assert (nop >= 0 && ndup >= 0 && nalt >= 0);
|
|
|
673 n_bytes = sizeof (struct lra_static_insn_data)
|
|
|
674 + sizeof (struct lra_operand_data) * nop
|
|
|
675 + sizeof (int) * ndup;
|
|
|
676 data = XNEWVAR (struct lra_static_insn_data, n_bytes);
|
|
|
677 data->operand_alternative = NULL;
|
|
|
678 data->n_operands = nop;
|
|
|
679 data->n_dups = ndup;
|
|
|
680 data->n_alternatives = nalt;
|
|
|
681 data->operand = ((struct lra_operand_data *)
|
|
|
682 ((char *) data + sizeof (struct lra_static_insn_data)));
|
|
|
683 data->dup_num = ((int *) ((char *) data->operand
|
|
|
684 + sizeof (struct lra_operand_data) * nop));
|
|
|
685 if (icode >= 0)
|
|
|
686 {
|
|
|
687 int i;
|
|
|
688
|
|
|
689 insn_code_data[icode] = data;
|
|
|
690 for (i = 0; i < nop; i++)
|
|
|
691 {
|
|
|
692 data->operand[i].constraint
|
|
|
693 = insn_data[icode].operand[i].constraint;
|
|
|
694 data->operand[i].mode = insn_data[icode].operand[i].mode;
|
|
|
695 data->operand[i].strict_low = insn_data[icode].operand[i].strict_low;
|
|
|
696 data->operand[i].is_operator
|
|
|
697 = insn_data[icode].operand[i].is_operator;
|
|
|
698 data->operand[i].type
|
|
|
699 = (data->operand[i].constraint[0] == '=' ? OP_OUT
|
|
|
700 : data->operand[i].constraint[0] == '+' ? OP_INOUT
|
|
|
701 : OP_IN);
|
|
|
702 data->operand[i].is_address = false;
|
|
|
703 }
|
|
|
704 for (i = 0; i < ndup; i++)
|
|
|
705 data->dup_num[i] = recog_data.dup_num[i];
|
|
|
706 }
|
|
|
707 return data;
|
|
|
708 }
|
|
|
709
|
|
|
710 /* The current length of the following array. */
|
|
|
711 int lra_insn_recog_data_len;
|
|
|
712
|
|
|
713 /* Map INSN_UID -> the insn recog data (NULL if unknown). */
|
|
|
714 lra_insn_recog_data_t *lra_insn_recog_data;
|
|
|
715
|
|
|
716 /* Initialize LRA data about insns. */
|
|
|
717 static void
|
|
|
718 init_insn_recog_data (void)
|
|
|
719 {
|
|
|
720 lra_insn_recog_data_len = 0;
|
|
|
721 lra_insn_recog_data = NULL;
|
|
|
722 }
|
|
|
723
|
|
|
724 /* Expand, if necessary, LRA data about insns. */
|
|
|
725 static void
|
|
|
726 check_and_expand_insn_recog_data (int index)
|
|
|
727 {
|
|
|
728 int i, old;
|
|
|
729
|
|
|
730 if (lra_insn_recog_data_len > index)
|
|
|
731 return;
|
|
|
732 old = lra_insn_recog_data_len;
|
|
|
733 lra_insn_recog_data_len = index * 3 / 2 + 1;
|
|
|
734 lra_insn_recog_data = XRESIZEVEC (lra_insn_recog_data_t,
|
|
|
735 lra_insn_recog_data,
|
|
|
736 lra_insn_recog_data_len);
|
|
|
737 for (i = old; i < lra_insn_recog_data_len; i++)
|
|
|
738 lra_insn_recog_data[i] = NULL;
|
|
|
739 }
|
|
|
740
|
|
|
741 /* Finish LRA DATA about insn. */
|
|
|
742 static void
|
|
|
743 free_insn_recog_data (lra_insn_recog_data_t data)
|
|
|
744 {
|
|
|
745 if (data->operand_loc != NULL)
|
|
|
746 free (data->operand_loc);
|
|
|
747 if (data->dup_loc != NULL)
|
|
|
748 free (data->dup_loc);
|
|
|
749 if (data->arg_hard_regs != NULL)
|
|
|
750 free (data->arg_hard_regs);
|
|
|
751 if (data->icode < 0 && NONDEBUG_INSN_P (data->insn))
|
|
|
752 {
|
|
|
753 if (data->insn_static_data->operand_alternative != NULL)
|
|
|
754 free (const_cast <operand_alternative *>
|
|
|
755 (data->insn_static_data->operand_alternative));
|
|
|
756 free_insn_regs (data->insn_static_data->hard_regs);
|
|
|
757 free (data->insn_static_data);
|
|
|
758 }
|
|
|
759 free_insn_regs (data->regs);
|
|
|
760 data->regs = NULL;
|
|
|
761 free (data);
|
|
|
762 }
|
|
|
763
|
|
|
764 /* Pools for copies. */
|
|
|
765 static object_allocator<lra_copy> lra_copy_pool ("lra copies");
|
|
|
766
|
|
|
767 /* Finish LRA data about all insns. */
|
|
|
768 static void
|
|
|
769 finish_insn_recog_data (void)
|
|
|
770 {
|
|
|
771 int i;
|
|
|
772 lra_insn_recog_data_t data;
|
|
|
773
|
|
|
774 for (i = 0; i < lra_insn_recog_data_len; i++)
|
|
|
775 if ((data = lra_insn_recog_data[i]) != NULL)
|
|
|
776 free_insn_recog_data (data);
|
|
|
777 finish_insn_regs ();
|
|
|
778 lra_copy_pool.release ();
|
|
|
779 lra_insn_reg_pool.release ();
|
|
|
780 free (lra_insn_recog_data);
|
|
|
781 }
|
|
|
782
|
|
|
783 /* Setup info about operands in alternatives of LRA DATA of insn. */
|
|
|
784 static void
|
|
|
785 setup_operand_alternative (lra_insn_recog_data_t data,
|
|
|
786 const operand_alternative *op_alt)
|
|
|
787 {
|
|
|
788 int i, j, nop, nalt;
|
|
|
789 int icode = data->icode;
|
|
|
790 struct lra_static_insn_data *static_data = data->insn_static_data;
|
|
|
791
|
|
|
792 static_data->commutative = -1;
|
|
|
793 nop = static_data->n_operands;
|
|
|
794 nalt = static_data->n_alternatives;
|
|
|
795 static_data->operand_alternative = op_alt;
|
|
|
796 for (i = 0; i < nop; i++)
|
|
|
797 {
|
|
|
798 static_data->operand[i].early_clobber_alts = 0;
|
|
|
799 static_data->operand[i].early_clobber = false;
|
|
|
800 static_data->operand[i].is_address = false;
|
|
|
801 if (static_data->operand[i].constraint[0] == '%')
|
|
|
802 {
|
|
|
803 /* We currently only support one commutative pair of operands. */
|
|
|
804 if (static_data->commutative < 0)
|
|
|
805 static_data->commutative = i;
|
|
|
806 else
|
|
|
807 lra_assert (icode < 0); /* Asm */
|
|
|
808 /* The last operand should not be marked commutative. */
|
|
|
809 lra_assert (i != nop - 1);
|
|
|
810 }
|
|
|
811 }
|
|
|
812 for (j = 0; j < nalt; j++)
|
|
|
813 for (i = 0; i < nop; i++, op_alt++)
|
|
|
814 {
|
|
|
815 static_data->operand[i].early_clobber |= op_alt->earlyclobber;
|
|
|
816 if (op_alt->earlyclobber)
|
|
|
817 static_data->operand[i].early_clobber_alts |= (alternative_mask) 1 << j;
|
|
|
818 static_data->operand[i].is_address |= op_alt->is_address;
|
|
|
819 }
|
|
|
820 }
|
|
|
821
|
|
|
822 /* Recursively process X and collect info about registers, which are
|
|
|
823 not the insn operands, in X with TYPE (in/out/inout) and flag that
|
|
|
824 it is early clobbered in the insn (EARLY_CLOBBER) and add the info
|
|
|
825 to LIST. X is a part of insn given by DATA. Return the result
|
|
131
|
826 list. CLOBBER_HIGH marks if X is a clobber high. */
|
|
111
|
827 static struct lra_insn_reg *
|
|
131
|
828 collect_non_operand_hard_regs (rtx_insn *insn, rtx *x,
|
|
|
829 lra_insn_recog_data_t data,
|
|
111
|
830 struct lra_insn_reg *list,
|
|
131
|
831 enum op_type type, bool early_clobber,
|
|
|
832 bool clobber_high)
|
|
111
|
833 {
|
|
|
834 int i, j, regno, last;
|
|
|
835 bool subreg_p;
|
|
|
836 machine_mode mode;
|
|
|
837 struct lra_insn_reg *curr;
|
|
|
838 rtx op = *x;
|
|
|
839 enum rtx_code code = GET_CODE (op);
|
|
|
840 const char *fmt = GET_RTX_FORMAT (code);
|
|
|
841
|
|
|
842 for (i = 0; i < data->insn_static_data->n_operands; i++)
|
|
|
843 if (! data->insn_static_data->operand[i].is_operator
|
|
|
844 && x == data->operand_loc[i])
|
|
|
845 /* It is an operand loc. Stop here. */
|
|
|
846 return list;
|
|
|
847 for (i = 0; i < data->insn_static_data->n_dups; i++)
|
|
|
848 if (x == data->dup_loc[i])
|
|
|
849 /* It is a dup loc. Stop here. */
|
|
|
850 return list;
|
|
|
851 mode = GET_MODE (op);
|
|
|
852 subreg_p = false;
|
|
|
853 if (code == SUBREG)
|
|
|
854 {
|
|
|
855 mode = wider_subreg_mode (op);
|
|
|
856 if (read_modify_subreg_p (op))
|
|
|
857 subreg_p = true;
|
|
|
858 op = SUBREG_REG (op);
|
|
|
859 code = GET_CODE (op);
|
|
|
860 }
|
|
|
861 if (REG_P (op))
|
|
|
862 {
|
|
|
863 if ((regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER)
|
|
|
864 return list;
|
|
|
865 /* Process all regs even unallocatable ones as we need info
|
|
|
866 about all regs for rematerialization pass. */
|
|
|
867 for (last = end_hard_regno (mode, regno); regno < last; regno++)
|
|
|
868 {
|
|
|
869 for (curr = list; curr != NULL; curr = curr->next)
|
|
|
870 if (curr->regno == regno && curr->subreg_p == subreg_p
|
|
|
871 && curr->biggest_mode == mode)
|
|
|
872 {
|
|
|
873 if (curr->type != type)
|
|
|
874 curr->type = OP_INOUT;
|
|
|
875 if (early_clobber)
|
|
|
876 {
|
|
|
877 curr->early_clobber = true;
|
|
|
878 curr->early_clobber_alts = ALL_ALTERNATIVES;
|
|
|
879 }
|
|
|
880 break;
|
|
|
881 }
|
|
|
882 if (curr == NULL)
|
|
|
883 {
|
|
|
884 /* This is a new hard regno or the info can not be
|
|
|
885 integrated into the found structure. */
|
|
|
886 #ifdef STACK_REGS
|
|
|
887 early_clobber
|
|
|
888 = (early_clobber
|
|
|
889 /* This clobber is to inform popping floating
|
|
|
890 point stack only. */
|
|
|
891 && ! (FIRST_STACK_REG <= regno
|
|
|
892 && regno <= LAST_STACK_REG));
|
|
|
893 #endif
|
|
|
894 list = new_insn_reg (data->insn, regno, type, mode, subreg_p,
|
|
|
895 early_clobber,
|
|
131
|
896 early_clobber ? ALL_ALTERNATIVES : 0, list,
|
|
|
897 clobber_high);
|
|
111
|
898 }
|
|
|
899 }
|
|
|
900 return list;
|
|
|
901 }
|
|
|
902 switch (code)
|
|
|
903 {
|
|
|
904 case SET:
|
|
131
|
905 list = collect_non_operand_hard_regs (insn, &SET_DEST (op), data,
|
|
|
906 list, OP_OUT, false, false);
|
|
|
907 list = collect_non_operand_hard_regs (insn, &SET_SRC (op), data,
|
|
|
908 list, OP_IN, false, false);
|
|
111
|
909 break;
|
|
|
910 case CLOBBER:
|
|
131
|
911 /* We treat clobber of non-operand hard registers as early clobber. */
|
|
|
912 list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data,
|
|
|
913 list, OP_OUT, true, false);
|
|
|
914 break;
|
|
|
915 case CLOBBER_HIGH:
|
|
|
916 /* Clobber high should always span exactly one register. */
|
|
|
917 gcc_assert (REG_NREGS (XEXP (op, 0)) == 1);
|
|
|
918 /* We treat clobber of non-operand hard registers as early clobber. */
|
|
|
919 list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data,
|
|
|
920 list, OP_OUT, true, true);
|
|
111
|
921 break;
|
|
|
922 case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC:
|
|
131
|
923 list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data,
|
|
|
924 list, OP_INOUT, false, false);
|
|
111
|
925 break;
|
|
|
926 case PRE_MODIFY: case POST_MODIFY:
|
|
131
|
927 list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data,
|
|
|
928 list, OP_INOUT, false, false);
|
|
|
929 list = collect_non_operand_hard_regs (insn, &XEXP (op, 1), data,
|
|
|
930 list, OP_IN, false, false);
|
|
111
|
931 break;
|
|
|
932 default:
|
|
|
933 fmt = GET_RTX_FORMAT (code);
|
|
|
934 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
|
|
|
935 {
|
|
|
936 if (fmt[i] == 'e')
|
|
131
|
937 list = collect_non_operand_hard_regs (insn, &XEXP (op, i), data,
|
|
|
938 list, OP_IN, false, false);
|
|
111
|
939 else if (fmt[i] == 'E')
|
|
|
940 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
|
|
131
|
941 list = collect_non_operand_hard_regs (insn, &XVECEXP (op, i, j),
|
|
|
942 data, list, OP_IN, false,
|
|
|
943 false);
|
|
111
|
944 }
|
|
|
945 }
|
|
|
946 return list;
|
|
|
947 }
|
|
|
948
|
|
|
949 /* Set up and return info about INSN. Set up the info if it is not set up
|
|
|
950 yet. */
|
|
|
951 lra_insn_recog_data_t
|
|
|
952 lra_set_insn_recog_data (rtx_insn *insn)
|
|
|
953 {
|
|
|
954 lra_insn_recog_data_t data;
|
|
|
955 int i, n, icode;
|
|
|
956 rtx **locs;
|
|
|
957 unsigned int uid = INSN_UID (insn);
|
|
|
958 struct lra_static_insn_data *insn_static_data;
|
|
|
959
|
|
|
960 check_and_expand_insn_recog_data (uid);
|
|
|
961 if (DEBUG_INSN_P (insn))
|
|
|
962 icode = -1;
|
|
|
963 else
|
|
|
964 {
|
|
|
965 icode = INSN_CODE (insn);
|
|
|
966 if (icode < 0)
|
|
|
967 /* It might be a new simple insn which is not recognized yet. */
|
|
|
968 INSN_CODE (insn) = icode = recog_memoized (insn);
|
|
|
969 }
|
|
|
970 data = XNEW (struct lra_insn_recog_data);
|
|
|
971 lra_insn_recog_data[uid] = data;
|
|
|
972 data->insn = insn;
|
|
131
|
973 data->used_insn_alternative = LRA_UNKNOWN_ALT;
|
|
111
|
974 data->icode = icode;
|
|
|
975 data->regs = NULL;
|
|
|
976 if (DEBUG_INSN_P (insn))
|
|
|
977 {
|
|
|
978 data->dup_loc = NULL;
|
|
|
979 data->arg_hard_regs = NULL;
|
|
|
980 data->preferred_alternatives = ALL_ALTERNATIVES;
|
|
131
|
981 if (DEBUG_BIND_INSN_P (insn))
|
|
|
982 {
|
|
|
983 data->insn_static_data = &debug_bind_static_data;
|
|
|
984 data->operand_loc = XNEWVEC (rtx *, 1);
|
|
|
985 data->operand_loc[0] = &INSN_VAR_LOCATION_LOC (insn);
|
|
|
986 }
|
|
|
987 else if (DEBUG_MARKER_INSN_P (insn))
|
|
|
988 {
|
|
|
989 data->insn_static_data = &debug_marker_static_data;
|
|
|
990 data->operand_loc = NULL;
|
|
|
991 }
|
|
111
|
992 return data;
|
|
|
993 }
|
|
|
994 if (icode < 0)
|
|
|
995 {
|
|
|
996 int nop, nalt;
|
|
|
997 machine_mode operand_mode[MAX_RECOG_OPERANDS];
|
|
|
998 const char *constraints[MAX_RECOG_OPERANDS];
|
|
|
999
|
|
|
1000 nop = asm_noperands (PATTERN (insn));
|
|
|
1001 data->operand_loc = data->dup_loc = NULL;
|
|
|
1002 nalt = 1;
|
|
|
1003 if (nop < 0)
|
|
|
1004 {
|
|
|
1005 /* It is a special insn like USE or CLOBBER. We should
|
|
|
1006 recognize any regular insn otherwise LRA can do nothing
|
|
|
1007 with this insn. */
|
|
|
1008 gcc_assert (GET_CODE (PATTERN (insn)) == USE
|
|
|
1009 || GET_CODE (PATTERN (insn)) == CLOBBER
|
|
|
1010 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
|
|
|
1011 data->insn_static_data = insn_static_data
|
|
|
1012 = get_static_insn_data (-1, 0, 0, nalt);
|
|
|
1013 }
|
|
|
1014 else
|
|
|
1015 {
|
|
|
1016 /* expand_asm_operands makes sure there aren't too many
|
|
|
1017 operands. */
|
|
|
1018 lra_assert (nop <= MAX_RECOG_OPERANDS);
|
|
|
1019 if (nop != 0)
|
|
|
1020 data->operand_loc = XNEWVEC (rtx *, nop);
|
|
|
1021 /* Now get the operand values and constraints out of the
|
|
|
1022 insn. */
|
|
|
1023 decode_asm_operands (PATTERN (insn), NULL,
|
|
|
1024 data->operand_loc,
|
|
|
1025 constraints, operand_mode, NULL);
|
|
|
1026 if (nop > 0)
|
|
|
1027 {
|
|
|
1028 const char *p = recog_data.constraints[0];
|
|
|
1029
|
|
|
1030 for (p = constraints[0]; *p; p++)
|
|
|
1031 nalt += *p == ',';
|
|
|
1032 }
|
|
|
1033 data->insn_static_data = insn_static_data
|
|
|
1034 = get_static_insn_data (-1, nop, 0, nalt);
|
|
|
1035 for (i = 0; i < nop; i++)
|
|
|
1036 {
|
|
|
1037 insn_static_data->operand[i].mode = operand_mode[i];
|
|
|
1038 insn_static_data->operand[i].constraint = constraints[i];
|
|
|
1039 insn_static_data->operand[i].strict_low = false;
|
|
|
1040 insn_static_data->operand[i].is_operator = false;
|
|
|
1041 insn_static_data->operand[i].is_address = false;
|
|
|
1042 }
|
|
|
1043 }
|
|
|
1044 for (i = 0; i < insn_static_data->n_operands; i++)
|
|
|
1045 insn_static_data->operand[i].type
|
|
|
1046 = (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT
|
|
|
1047 : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT
|
|
|
1048 : OP_IN);
|
|
|
1049 data->preferred_alternatives = ALL_ALTERNATIVES;
|
|
|
1050 if (nop > 0)
|
|
|
1051 {
|
|
|
1052 operand_alternative *op_alt = XCNEWVEC (operand_alternative,
|
|
|
1053 nalt * nop);
|
|
131
|
1054 preprocess_constraints (nop, nalt, constraints, op_alt,
|
|
|
1055 data->operand_loc);
|
|
111
|
1056 setup_operand_alternative (data, op_alt);
|
|
|
1057 }
|
|
|
1058 }
|
|
|
1059 else
|
|
|
1060 {
|
|
|
1061 insn_extract (insn);
|
|
|
1062 data->insn_static_data = insn_static_data
|
|
|
1063 = get_static_insn_data (icode, insn_data[icode].n_operands,
|
|
|
1064 insn_data[icode].n_dups,
|
|
|
1065 insn_data[icode].n_alternatives);
|
|
|
1066 n = insn_static_data->n_operands;
|
|
|
1067 if (n == 0)
|
|
|
1068 locs = NULL;
|
|
|
1069 else
|
|
|
1070 {
|
|
|
1071 locs = XNEWVEC (rtx *, n);
|
|
|
1072 memcpy (locs, recog_data.operand_loc, n * sizeof (rtx *));
|
|
|
1073 }
|
|
|
1074 data->operand_loc = locs;
|
|
|
1075 n = insn_static_data->n_dups;
|
|
|
1076 if (n == 0)
|
|
|
1077 locs = NULL;
|
|
|
1078 else
|
|
|
1079 {
|
|
|
1080 locs = XNEWVEC (rtx *, n);
|
|
|
1081 memcpy (locs, recog_data.dup_loc, n * sizeof (rtx *));
|
|
|
1082 }
|
|
|
1083 data->dup_loc = locs;
|
|
|
1084 data->preferred_alternatives = get_preferred_alternatives (insn);
|
|
|
1085 const operand_alternative *op_alt = preprocess_insn_constraints (icode);
|
|
|
1086 if (!insn_static_data->operand_alternative)
|
|
|
1087 setup_operand_alternative (data, op_alt);
|
|
|
1088 else if (op_alt != insn_static_data->operand_alternative)
|
|
|
1089 insn_static_data->operand_alternative = op_alt;
|
|
|
1090 }
|
|
|
1091 if (GET_CODE (PATTERN (insn)) == CLOBBER || GET_CODE (PATTERN (insn)) == USE)
|
|
|
1092 insn_static_data->hard_regs = NULL;
|
|
|
1093 else
|
|
|
1094 insn_static_data->hard_regs
|
|
131
|
1095 = collect_non_operand_hard_regs (insn, &PATTERN (insn), data,
|
|
|
1096 NULL, OP_IN, false, false);
|
|
111
|
1097 data->arg_hard_regs = NULL;
|
|
|
1098 if (CALL_P (insn))
|
|
|
1099 {
|
|
|
1100 bool use_p;
|
|
|
1101 rtx link;
|
|
|
1102 int n_hard_regs, regno, arg_hard_regs[FIRST_PSEUDO_REGISTER];
|
|
|
1103
|
|
|
1104 n_hard_regs = 0;
|
|
|
1105 /* Finding implicit hard register usage. We believe it will be
|
|
|
1106 not changed whatever transformations are used. Call insns
|
|
|
1107 are such example. */
|
|
|
1108 for (link = CALL_INSN_FUNCTION_USAGE (insn);
|
|
|
1109 link != NULL_RTX;
|
|
|
1110 link = XEXP (link, 1))
|
|
|
1111 if (((use_p = GET_CODE (XEXP (link, 0)) == USE)
|
|
|
1112 || GET_CODE (XEXP (link, 0)) == CLOBBER)
|
|
|
1113 && REG_P (XEXP (XEXP (link, 0), 0)))
|
|
|
1114 {
|
|
|
1115 regno = REGNO (XEXP (XEXP (link, 0), 0));
|
|
|
1116 lra_assert (regno < FIRST_PSEUDO_REGISTER);
|
|
|
1117 /* It is an argument register. */
|
|
|
1118 for (i = REG_NREGS (XEXP (XEXP (link, 0), 0)) - 1; i >= 0; i--)
|
|
|
1119 arg_hard_regs[n_hard_regs++]
|
|
|
1120 = regno + i + (use_p ? 0 : FIRST_PSEUDO_REGISTER);
|
|
|
1121 }
|
|
131
|
1122 else if (GET_CODE (XEXP (link, 0)) == CLOBBER_HIGH)
|
|
|
1123 /* We could support CLOBBER_HIGH and treat it in the same way as
|
|
|
1124 HARD_REGNO_CALL_PART_CLOBBERED, but no port needs that yet. */
|
|
|
1125 gcc_unreachable ();
|
|
|
1126
|
|
111
|
1127 if (n_hard_regs != 0)
|
|
|
1128 {
|
|
|
1129 arg_hard_regs[n_hard_regs++] = -1;
|
|
|
1130 data->arg_hard_regs = XNEWVEC (int, n_hard_regs);
|
|
|
1131 memcpy (data->arg_hard_regs, arg_hard_regs,
|
|
|
1132 sizeof (int) * n_hard_regs);
|
|
|
1133 }
|
|
|
1134 }
|
|
|
1135 /* Some output operand can be recognized only from the context not
|
|
|
1136 from the constraints which are empty in this case. Call insn may
|
|
|
1137 contain a hard register in set destination with empty constraint
|
|
|
1138 and extract_insn treats them as an input. */
|
|
|
1139 for (i = 0; i < insn_static_data->n_operands; i++)
|
|
|
1140 {
|
|
|
1141 int j;
|
|
|
1142 rtx pat, set;
|
|
|
1143 struct lra_operand_data *operand = &insn_static_data->operand[i];
|
|
|
1144
|
|
|
1145 /* ??? Should we treat 'X' the same way. It looks to me that
|
|
|
1146 'X' means anything and empty constraint means we do not
|
|
|
1147 care. */
|
|
|
1148 if (operand->type != OP_IN || *operand->constraint != '\0'
|
|
|
1149 || operand->is_operator)
|
|
|
1150 continue;
|
|
|
1151 pat = PATTERN (insn);
|
|
|
1152 if (GET_CODE (pat) == SET)
|
|
|
1153 {
|
|
|
1154 if (data->operand_loc[i] != &SET_DEST (pat))
|
|
|
1155 continue;
|
|
|
1156 }
|
|
|
1157 else if (GET_CODE (pat) == PARALLEL)
|
|
|
1158 {
|
|
|
1159 for (j = XVECLEN (pat, 0) - 1; j >= 0; j--)
|
|
|
1160 {
|
|
|
1161 set = XVECEXP (PATTERN (insn), 0, j);
|
|
|
1162 if (GET_CODE (set) == SET
|
|
|
1163 && &SET_DEST (set) == data->operand_loc[i])
|
|
|
1164 break;
|
|
|
1165 }
|
|
|
1166 if (j < 0)
|
|
|
1167 continue;
|
|
|
1168 }
|
|
|
1169 else
|
|
|
1170 continue;
|
|
|
1171 operand->type = OP_OUT;
|
|
|
1172 }
|
|
|
1173 return data;
|
|
|
1174 }
|
|
|
1175
|
|
|
1176 /* Return info about insn give by UID. The info should be already set
|
|
|
1177 up. */
|
|
|
1178 static lra_insn_recog_data_t
|
|
|
1179 get_insn_recog_data_by_uid (int uid)
|
|
|
1180 {
|
|
|
1181 lra_insn_recog_data_t data;
|
|
|
1182
|
|
|
1183 data = lra_insn_recog_data[uid];
|
|
|
1184 lra_assert (data != NULL);
|
|
|
1185 return data;
|
|
|
1186 }
|
|
|
1187
|
|
|
1188 /* Invalidate all info about insn given by its UID. */
|
|
|
1189 static void
|
|
|
1190 invalidate_insn_recog_data (int uid)
|
|
|
1191 {
|
|
|
1192 lra_insn_recog_data_t data;
|
|
|
1193
|
|
|
1194 data = lra_insn_recog_data[uid];
|
|
|
1195 lra_assert (data != NULL);
|
|
|
1196 free_insn_recog_data (data);
|
|
|
1197 lra_insn_recog_data[uid] = NULL;
|
|
|
1198 }
|
|
|
1199
|
|
|
1200 /* Update all the insn info about INSN. It is usually called when
|
|
|
1201 something in the insn was changed. Return the updated info. */
|
|
|
1202 lra_insn_recog_data_t
|
|
|
1203 lra_update_insn_recog_data (rtx_insn *insn)
|
|
|
1204 {
|
|
|
1205 lra_insn_recog_data_t data;
|
|
|
1206 int n;
|
|
|
1207 unsigned int uid = INSN_UID (insn);
|
|
|
1208 struct lra_static_insn_data *insn_static_data;
|
|
131
|
1209 poly_int64 sp_offset = 0;
|
|
111
|
1210
|
|
|
1211 check_and_expand_insn_recog_data (uid);
|
|
|
1212 if ((data = lra_insn_recog_data[uid]) != NULL
|
|
|
1213 && data->icode != INSN_CODE (insn))
|
|
|
1214 {
|
|
|
1215 sp_offset = data->sp_offset;
|
|
|
1216 invalidate_insn_data_regno_info (data, insn, get_insn_freq (insn));
|
|
|
1217 invalidate_insn_recog_data (uid);
|
|
|
1218 data = NULL;
|
|
|
1219 }
|
|
|
1220 if (data == NULL)
|
|
|
1221 {
|
|
|
1222 data = lra_get_insn_recog_data (insn);
|
|
|
1223 /* Initiate or restore SP offset. */
|
|
|
1224 data->sp_offset = sp_offset;
|
|
|
1225 return data;
|
|
|
1226 }
|
|
|
1227 insn_static_data = data->insn_static_data;
|
|
131
|
1228 data->used_insn_alternative = LRA_UNKNOWN_ALT;
|
|
111
|
1229 if (DEBUG_INSN_P (insn))
|
|
|
1230 return data;
|
|
|
1231 if (data->icode < 0)
|
|
|
1232 {
|
|
|
1233 int nop;
|
|
|
1234 machine_mode operand_mode[MAX_RECOG_OPERANDS];
|
|
|
1235 const char *constraints[MAX_RECOG_OPERANDS];
|
|
|
1236
|
|
|
1237 nop = asm_noperands (PATTERN (insn));
|
|
|
1238 if (nop >= 0)
|
|
|
1239 {
|
|
|
1240 lra_assert (nop == data->insn_static_data->n_operands);
|
|
|
1241 /* Now get the operand values and constraints out of the
|
|
|
1242 insn. */
|
|
|
1243 decode_asm_operands (PATTERN (insn), NULL,
|
|
|
1244 data->operand_loc,
|
|
|
1245 constraints, operand_mode, NULL);
|
|
|
1246
|
|
|
1247 if (flag_checking)
|
|
|
1248 for (int i = 0; i < nop; i++)
|
|
|
1249 lra_assert
|
|
|
1250 (insn_static_data->operand[i].mode == operand_mode[i]
|
|
|
1251 && insn_static_data->operand[i].constraint == constraints[i]
|
|
|
1252 && ! insn_static_data->operand[i].is_operator);
|
|
|
1253 }
|
|
|
1254
|
|
|
1255 if (flag_checking)
|
|
|
1256 for (int i = 0; i < insn_static_data->n_operands; i++)
|
|
|
1257 lra_assert
|
|
|
1258 (insn_static_data->operand[i].type
|
|
|
1259 == (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT
|
|
|
1260 : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT
|
|
|
1261 : OP_IN));
|
|
|
1262 }
|
|
|
1263 else
|
|
|
1264 {
|
|
|
1265 insn_extract (insn);
|
|
|
1266 n = insn_static_data->n_operands;
|
|
|
1267 if (n != 0)
|
|
|
1268 memcpy (data->operand_loc, recog_data.operand_loc, n * sizeof (rtx *));
|
|
|
1269 n = insn_static_data->n_dups;
|
|
|
1270 if (n != 0)
|
|
|
1271 memcpy (data->dup_loc, recog_data.dup_loc, n * sizeof (rtx *));
|
|
|
1272 lra_assert (check_bool_attrs (insn));
|
|
|
1273 }
|
|
|
1274 return data;
|
|
|
1275 }
|
|
|
1276
|
|
|
1277 /* Set up that INSN is using alternative ALT now. */
|
|
|
1278 void
|
|
|
1279 lra_set_used_insn_alternative (rtx_insn *insn, int alt)
|
|
|
1280 {
|
|
|
1281 lra_insn_recog_data_t data;
|
|
|
1282
|
|
|
1283 data = lra_get_insn_recog_data (insn);
|
|
|
1284 data->used_insn_alternative = alt;
|
|
|
1285 }
|
|
|
1286
|
|
|
1287 /* Set up that insn with UID is using alternative ALT now. The insn
|
|
|
1288 info should be already set up. */
|
|
|
1289 void
|
|
|
1290 lra_set_used_insn_alternative_by_uid (int uid, int alt)
|
|
|
1291 {
|
|
|
1292 lra_insn_recog_data_t data;
|
|
|
1293
|
|
|
1294 check_and_expand_insn_recog_data (uid);
|
|
|
1295 data = lra_insn_recog_data[uid];
|
|
|
1296 lra_assert (data != NULL);
|
|
|
1297 data->used_insn_alternative = alt;
|
|
|
1298 }
|
|
|
1299
|
|
|
1300
|
|
|
1301
|
|
|
1302 /* This page contains code dealing with common register info and
|
|
|
1303 pseudo copies. */
|
|
|
1304
|
|
|
1305 /* The size of the following array. */
|
|
|
1306 static int reg_info_size;
|
|
|
1307 /* Common info about each register. */
|
|
|
1308 struct lra_reg *lra_reg_info;
|
|
|
1309
|
|
131
|
1310 HARD_REG_SET hard_regs_spilled_into;
|
|
|
1311
|
|
111
|
1312 /* Last register value. */
|
|
|
1313 static int last_reg_value;
|
|
|
1314
|
|
|
1315 /* Return new register value. */
|
|
|
1316 static int
|
|
|
1317 get_new_reg_value (void)
|
|
|
1318 {
|
|
|
1319 return ++last_reg_value;
|
|
|
1320 }
|
|
|
1321
|
|
|
1322 /* Vec referring to pseudo copies. */
|
|
|
1323 static vec<lra_copy_t> copy_vec;
|
|
|
1324
|
|
|
1325 /* Initialize I-th element of lra_reg_info. */
|
|
|
1326 static inline void
|
|
|
1327 initialize_lra_reg_info_element (int i)
|
|
|
1328 {
|
|
|
1329 bitmap_initialize (&lra_reg_info[i].insn_bitmap, ®_obstack);
|
|
|
1330 #ifdef STACK_REGS
|
|
|
1331 lra_reg_info[i].no_stack_p = false;
|
|
|
1332 #endif
|
|
|
1333 CLEAR_HARD_REG_SET (lra_reg_info[i].conflict_hard_regs);
|
|
|
1334 CLEAR_HARD_REG_SET (lra_reg_info[i].actual_call_used_reg_set);
|
|
|
1335 lra_reg_info[i].preferred_hard_regno1 = -1;
|
|
|
1336 lra_reg_info[i].preferred_hard_regno2 = -1;
|
|
|
1337 lra_reg_info[i].preferred_hard_regno_profit1 = 0;
|
|
|
1338 lra_reg_info[i].preferred_hard_regno_profit2 = 0;
|
|
|
1339 lra_reg_info[i].biggest_mode = VOIDmode;
|
|
|
1340 lra_reg_info[i].live_ranges = NULL;
|
|
|
1341 lra_reg_info[i].nrefs = lra_reg_info[i].freq = 0;
|
|
|
1342 lra_reg_info[i].last_reload = 0;
|
|
|
1343 lra_reg_info[i].restore_rtx = NULL_RTX;
|
|
|
1344 lra_reg_info[i].val = get_new_reg_value ();
|
|
|
1345 lra_reg_info[i].offset = 0;
|
|
|
1346 lra_reg_info[i].copies = NULL;
|
|
|
1347 }
|
|
|
1348
|
|
|
1349 /* Initialize common reg info and copies. */
|
|
|
1350 static void
|
|
|
1351 init_reg_info (void)
|
|
|
1352 {
|
|
|
1353 int i;
|
|
|
1354
|
|
|
1355 last_reg_value = 0;
|
|
|
1356 reg_info_size = max_reg_num () * 3 / 2 + 1;
|
|
|
1357 lra_reg_info = XNEWVEC (struct lra_reg, reg_info_size);
|
|
|
1358 for (i = 0; i < reg_info_size; i++)
|
|
|
1359 initialize_lra_reg_info_element (i);
|
|
|
1360 copy_vec.truncate (0);
|
|
131
|
1361 CLEAR_HARD_REG_SET (hard_regs_spilled_into);
|
|
111
|
1362 }
|
|
|
1363
|
|
|
1364
|
|
|
1365 /* Finish common reg info and copies. */
|
|
|
1366 static void
|
|
|
1367 finish_reg_info (void)
|
|
|
1368 {
|
|
|
1369 int i;
|
|
|
1370
|
|
|
1371 for (i = 0; i < reg_info_size; i++)
|
|
|
1372 bitmap_clear (&lra_reg_info[i].insn_bitmap);
|
|
|
1373 free (lra_reg_info);
|
|
|
1374 reg_info_size = 0;
|
|
|
1375 }
|
|
|
1376
|
|
|
1377 /* Expand common reg info if it is necessary. */
|
|
|
1378 static void
|
|
|
1379 expand_reg_info (void)
|
|
|
1380 {
|
|
|
1381 int i, old = reg_info_size;
|
|
|
1382
|
|
|
1383 if (reg_info_size > max_reg_num ())
|
|
|
1384 return;
|
|
|
1385 reg_info_size = max_reg_num () * 3 / 2 + 1;
|
|
|
1386 lra_reg_info = XRESIZEVEC (struct lra_reg, lra_reg_info, reg_info_size);
|
|
|
1387 for (i = old; i < reg_info_size; i++)
|
|
|
1388 initialize_lra_reg_info_element (i);
|
|
|
1389 }
|
|
|
1390
|
|
|
1391 /* Free all copies. */
|
|
|
1392 void
|
|
|
1393 lra_free_copies (void)
|
|
|
1394 {
|
|
|
1395 lra_copy_t cp;
|
|
|
1396
|
|
|
1397 while (copy_vec.length () != 0)
|
|
|
1398 {
|
|
|
1399 cp = copy_vec.pop ();
|
|
|
1400 lra_reg_info[cp->regno1].copies = lra_reg_info[cp->regno2].copies = NULL;
|
|
|
1401 lra_copy_pool.remove (cp);
|
|
|
1402 }
|
|
|
1403 }
|
|
|
1404
|
|
|
1405 /* Create copy of two pseudos REGNO1 and REGNO2. The copy execution
|
|
|
1406 frequency is FREQ. */
|
|
|
1407 void
|
|
|
1408 lra_create_copy (int regno1, int regno2, int freq)
|
|
|
1409 {
|
|
|
1410 bool regno1_dest_p;
|
|
|
1411 lra_copy_t cp;
|
|
|
1412
|
|
|
1413 lra_assert (regno1 != regno2);
|
|
|
1414 regno1_dest_p = true;
|
|
|
1415 if (regno1 > regno2)
|
|
|
1416 {
|
|
|
1417 std::swap (regno1, regno2);
|
|
|
1418 regno1_dest_p = false;
|
|
|
1419 }
|
|
|
1420 cp = lra_copy_pool.allocate ();
|
|
|
1421 copy_vec.safe_push (cp);
|
|
|
1422 cp->regno1_dest_p = regno1_dest_p;
|
|
|
1423 cp->freq = freq;
|
|
|
1424 cp->regno1 = regno1;
|
|
|
1425 cp->regno2 = regno2;
|
|
|
1426 cp->regno1_next = lra_reg_info[regno1].copies;
|
|
|
1427 lra_reg_info[regno1].copies = cp;
|
|
|
1428 cp->regno2_next = lra_reg_info[regno2].copies;
|
|
|
1429 lra_reg_info[regno2].copies = cp;
|
|
|
1430 if (lra_dump_file != NULL)
|
|
|
1431 fprintf (lra_dump_file, " Creating copy r%d%sr%d@%d\n",
|
|
|
1432 regno1, regno1_dest_p ? "<-" : "->", regno2, freq);
|
|
|
1433 }
|
|
|
1434
|
|
|
1435 /* Return N-th (0, 1, ...) copy. If there is no copy, return
|
|
|
1436 NULL. */
|
|
|
1437 lra_copy_t
|
|
|
1438 lra_get_copy (int n)
|
|
|
1439 {
|
|
|
1440 if (n >= (int) copy_vec.length ())
|
|
|
1441 return NULL;
|
|
|
1442 return copy_vec[n];
|
|
|
1443 }
|
|
|
1444
|
|
|
1445
|
|
|
1446
|
|
|
1447 /* This page contains code dealing with info about registers in
|
|
|
1448 insns. */
|
|
|
1449
|
|
131
|
1450 /* Process X of INSN recursively and add info (operand type is
|
|
111
|
1451 given by TYPE, flag of that it is early clobber is EARLY_CLOBBER)
|
|
|
1452 about registers in X to the insn DATA. If X can be early clobbered,
|
|
|
1453 alternatives in which it can be early clobbered are given by
|
|
|
1454 EARLY_CLOBBER_ALTS. */
|
|
|
1455 static void
|
|
131
|
1456 add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x,
|
|
|
1457 rtx_insn *insn,
|
|
111
|
1458 enum op_type type, bool early_clobber,
|
|
|
1459 alternative_mask early_clobber_alts)
|
|
|
1460 {
|
|
|
1461 int i, j, regno;
|
|
|
1462 bool subreg_p;
|
|
|
1463 machine_mode mode;
|
|
|
1464 const char *fmt;
|
|
|
1465 enum rtx_code code;
|
|
|
1466 struct lra_insn_reg *curr;
|
|
|
1467
|
|
|
1468 code = GET_CODE (x);
|
|
|
1469 mode = GET_MODE (x);
|
|
|
1470 subreg_p = false;
|
|
|
1471 if (GET_CODE (x) == SUBREG)
|
|
|
1472 {
|
|
|
1473 mode = wider_subreg_mode (x);
|
|
|
1474 if (read_modify_subreg_p (x))
|
|
|
1475 subreg_p = true;
|
|
|
1476 x = SUBREG_REG (x);
|
|
|
1477 code = GET_CODE (x);
|
|
|
1478 }
|
|
|
1479 if (REG_P (x))
|
|
|
1480 {
|
|
|
1481 regno = REGNO (x);
|
|
|
1482 /* Process all regs even unallocatable ones as we need info about
|
|
|
1483 all regs for rematerialization pass. */
|
|
|
1484 expand_reg_info ();
|
|
131
|
1485 if (bitmap_set_bit (&lra_reg_info[regno].insn_bitmap, INSN_UID (insn)))
|
|
111
|
1486 {
|
|
|
1487 data->regs = new_insn_reg (data->insn, regno, type, mode, subreg_p,
|
|
|
1488 early_clobber, early_clobber_alts,
|
|
131
|
1489 data->regs, false);
|
|
111
|
1490 return;
|
|
|
1491 }
|
|
|
1492 else
|
|
|
1493 {
|
|
|
1494 for (curr = data->regs; curr != NULL; curr = curr->next)
|
|
|
1495 if (curr->regno == regno)
|
|
|
1496 {
|
|
|
1497 if (curr->subreg_p != subreg_p || curr->biggest_mode != mode)
|
|
|
1498 /* The info can not be integrated into the found
|
|
|
1499 structure. */
|
|
|
1500 data->regs = new_insn_reg (data->insn, regno, type, mode,
|
|
|
1501 subreg_p, early_clobber,
|
|
131
|
1502 early_clobber_alts, data->regs,
|
|
|
1503 false);
|
|
111
|
1504 else
|
|
|
1505 {
|
|
|
1506 if (curr->type != type)
|
|
|
1507 curr->type = OP_INOUT;
|
|
|
1508 if (curr->early_clobber != early_clobber)
|
|
|
1509 curr->early_clobber = true;
|
|
|
1510 curr->early_clobber_alts |= early_clobber_alts;
|
|
|
1511 }
|
|
|
1512 return;
|
|
|
1513 }
|
|
|
1514 gcc_unreachable ();
|
|
|
1515 }
|
|
|
1516 }
|
|
|
1517
|
|
|
1518 switch (code)
|
|
|
1519 {
|
|
|
1520 case SET:
|
|
131
|
1521 add_regs_to_insn_regno_info (data, SET_DEST (x), insn, OP_OUT, false, 0);
|
|
|
1522 add_regs_to_insn_regno_info (data, SET_SRC (x), insn, OP_IN, false, 0);
|
|
111
|
1523 break;
|
|
|
1524 case CLOBBER:
|
|
|
1525 /* We treat clobber of non-operand hard registers as early
|
|
131
|
1526 clobber. */
|
|
|
1527 add_regs_to_insn_regno_info (data, XEXP (x, 0), insn, OP_OUT,
|
|
|
1528 true, ALL_ALTERNATIVES);
|
|
111
|
1529 break;
|
|
131
|
1530 case CLOBBER_HIGH:
|
|
|
1531 gcc_unreachable ();
|
|
111
|
1532 case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC:
|
|
131
|
1533 add_regs_to_insn_regno_info (data, XEXP (x, 0), insn, OP_INOUT, false, 0);
|
|
111
|
1534 break;
|
|
|
1535 case PRE_MODIFY: case POST_MODIFY:
|
|
131
|
1536 add_regs_to_insn_regno_info (data, XEXP (x, 0), insn, OP_INOUT, false, 0);
|
|
|
1537 add_regs_to_insn_regno_info (data, XEXP (x, 1), insn, OP_IN, false, 0);
|
|
111
|
1538 break;
|
|
|
1539 default:
|
|
|
1540 if ((code != PARALLEL && code != EXPR_LIST) || type != OP_OUT)
|
|
|
1541 /* Some targets place small structures in registers for return
|
|
|
1542 values of functions, and those registers are wrapped in
|
|
|
1543 PARALLEL that we may see as the destination of a SET. Here
|
|
|
1544 is an example:
|
|
|
1545
|
|
|
1546 (call_insn 13 12 14 2 (set (parallel:BLK [
|
|
|
1547 (expr_list:REG_DEP_TRUE (reg:DI 0 ax)
|
|
|
1548 (const_int 0 [0]))
|
|
|
1549 (expr_list:REG_DEP_TRUE (reg:DI 1 dx)
|
|
|
1550 (const_int 8 [0x8]))
|
|
|
1551 ])
|
|
|
1552 (call (mem:QI (symbol_ref:DI (... */
|
|
|
1553 type = OP_IN;
|
|
|
1554 fmt = GET_RTX_FORMAT (code);
|
|
|
1555 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
|
|
|
1556 {
|
|
|
1557 if (fmt[i] == 'e')
|
|
131
|
1558 add_regs_to_insn_regno_info (data, XEXP (x, i), insn, type, false, 0);
|
|
111
|
1559 else if (fmt[i] == 'E')
|
|
|
1560 {
|
|
|
1561 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
|
|
131
|
1562 add_regs_to_insn_regno_info (data, XVECEXP (x, i, j), insn,
|
|
111
|
1563 type, false, 0);
|
|
|
1564 }
|
|
|
1565 }
|
|
|
1566 }
|
|
|
1567 }
|
|
|
1568
|
|
|
1569 /* Return execution frequency of INSN. */
|
|
|
1570 static int
|
|
|
1571 get_insn_freq (rtx_insn *insn)
|
|
|
1572 {
|
|
|
1573 basic_block bb = BLOCK_FOR_INSN (insn);
|
|
|
1574
|
|
|
1575 gcc_checking_assert (bb != NULL);
|
|
|
1576 return REG_FREQ_FROM_BB (bb);
|
|
|
1577 }
|
|
|
1578
|
|
|
1579 /* Invalidate all reg info of INSN with DATA and execution frequency
|
|
|
1580 FREQ. Update common info about the invalidated registers. */
|
|
|
1581 static void
|
|
|
1582 invalidate_insn_data_regno_info (lra_insn_recog_data_t data, rtx_insn *insn,
|
|
|
1583 int freq)
|
|
|
1584 {
|
|
|
1585 int uid;
|
|
|
1586 bool debug_p;
|
|
|
1587 unsigned int i;
|
|
|
1588 struct lra_insn_reg *ir, *next_ir;
|
|
|
1589
|
|
|
1590 uid = INSN_UID (insn);
|
|
|
1591 debug_p = DEBUG_INSN_P (insn);
|
|
|
1592 for (ir = data->regs; ir != NULL; ir = next_ir)
|
|
|
1593 {
|
|
|
1594 i = ir->regno;
|
|
|
1595 next_ir = ir->next;
|
|
|
1596 lra_insn_reg_pool.remove (ir);
|
|
|
1597 bitmap_clear_bit (&lra_reg_info[i].insn_bitmap, uid);
|
|
|
1598 if (i >= FIRST_PSEUDO_REGISTER && ! debug_p)
|
|
|
1599 {
|
|
|
1600 lra_reg_info[i].nrefs--;
|
|
|
1601 lra_reg_info[i].freq -= freq;
|
|
|
1602 lra_assert (lra_reg_info[i].nrefs >= 0 && lra_reg_info[i].freq >= 0);
|
|
|
1603 }
|
|
|
1604 }
|
|
|
1605 data->regs = NULL;
|
|
|
1606 }
|
|
|
1607
|
|
|
1608 /* Invalidate all reg info of INSN. Update common info about the
|
|
|
1609 invalidated registers. */
|
|
|
1610 void
|
|
|
1611 lra_invalidate_insn_regno_info (rtx_insn *insn)
|
|
|
1612 {
|
|
|
1613 invalidate_insn_data_regno_info (lra_get_insn_recog_data (insn), insn,
|
|
|
1614 get_insn_freq (insn));
|
|
|
1615 }
|
|
|
1616
|
|
|
1617 /* Update common reg info from reg info of insn given by its DATA and
|
|
|
1618 execution frequency FREQ. */
|
|
|
1619 static void
|
|
|
1620 setup_insn_reg_info (lra_insn_recog_data_t data, int freq)
|
|
|
1621 {
|
|
|
1622 unsigned int i;
|
|
|
1623 struct lra_insn_reg *ir;
|
|
|
1624
|
|
|
1625 for (ir = data->regs; ir != NULL; ir = ir->next)
|
|
|
1626 if ((i = ir->regno) >= FIRST_PSEUDO_REGISTER)
|
|
|
1627 {
|
|
|
1628 lra_reg_info[i].nrefs++;
|
|
|
1629 lra_reg_info[i].freq += freq;
|
|
|
1630 }
|
|
|
1631 }
|
|
|
1632
|
|
|
1633 /* Set up insn reg info of INSN. Update common reg info from reg info
|
|
|
1634 of INSN. */
|
|
|
1635 void
|
|
|
1636 lra_update_insn_regno_info (rtx_insn *insn)
|
|
|
1637 {
|
|
131
|
1638 int i, freq;
|
|
111
|
1639 lra_insn_recog_data_t data;
|
|
|
1640 struct lra_static_insn_data *static_data;
|
|
|
1641 enum rtx_code code;
|
|
|
1642 rtx link;
|
|
|
1643
|
|
|
1644 if (! INSN_P (insn))
|
|
|
1645 return;
|
|
|
1646 data = lra_get_insn_recog_data (insn);
|
|
|
1647 static_data = data->insn_static_data;
|
|
131
|
1648 freq = NONDEBUG_INSN_P (insn) ? get_insn_freq (insn) : 0;
|
|
111
|
1649 invalidate_insn_data_regno_info (data, insn, freq);
|
|
|
1650 for (i = static_data->n_operands - 1; i >= 0; i--)
|
|
131
|
1651 add_regs_to_insn_regno_info (data, *data->operand_loc[i], insn,
|
|
111
|
1652 static_data->operand[i].type,
|
|
|
1653 static_data->operand[i].early_clobber,
|
|
|
1654 static_data->operand[i].early_clobber_alts);
|
|
|
1655 if ((code = GET_CODE (PATTERN (insn))) == CLOBBER || code == USE)
|
|
131
|
1656 add_regs_to_insn_regno_info (data, XEXP (PATTERN (insn), 0), insn,
|
|
111
|
1657 code == USE ? OP_IN : OP_OUT, false, 0);
|
|
|
1658 if (CALL_P (insn))
|
|
|
1659 /* On some targets call insns can refer to pseudos in memory in
|
|
|
1660 CALL_INSN_FUNCTION_USAGE list. Process them in order to
|
|
|
1661 consider their occurrences in calls for different
|
|
|
1662 transformations (e.g. inheritance) with given pseudos. */
|
|
|
1663 for (link = CALL_INSN_FUNCTION_USAGE (insn);
|
|
|
1664 link != NULL_RTX;
|
|
|
1665 link = XEXP (link, 1))
|
|
131
|
1666 {
|
|
|
1667 code = GET_CODE (XEXP (link, 0));
|
|
|
1668 /* We could support CLOBBER_HIGH and treat it in the same way as
|
|
|
1669 HARD_REGNO_CALL_PART_CLOBBERED, but no port needs that yet. */
|
|
|
1670 gcc_assert (code != CLOBBER_HIGH);
|
|
|
1671 if ((code == USE || code == CLOBBER)
|
|
|
1672 && MEM_P (XEXP (XEXP (link, 0), 0)))
|
|
|
1673 add_regs_to_insn_regno_info (data, XEXP (XEXP (link, 0), 0), insn,
|
|
|
1674 code == USE ? OP_IN : OP_OUT, false, 0);
|
|
|
1675 }
|
|
111
|
1676 if (NONDEBUG_INSN_P (insn))
|
|
|
1677 setup_insn_reg_info (data, freq);
|
|
|
1678 }
|
|
|
1679
|
|
|
1680 /* Return reg info of insn given by it UID. */
|
|
|
1681 struct lra_insn_reg *
|
|
|
1682 lra_get_insn_regs (int uid)
|
|
|
1683 {
|
|
|
1684 lra_insn_recog_data_t data;
|
|
|
1685
|
|
|
1686 data = get_insn_recog_data_by_uid (uid);
|
|
|
1687 return data->regs;
|
|
|
1688 }
|
|
|
1689
|
|
|
1690
|
|
|
1691
|
|
|
1692 /* Recursive hash function for RTL X. */
|
|
|
1693 hashval_t
|
|
|
1694 lra_rtx_hash (rtx x)
|
|
|
1695 {
|
|
|
1696 int i, j;
|
|
|
1697 enum rtx_code code;
|
|
|
1698 const char *fmt;
|
|
|
1699 hashval_t val = 0;
|
|
|
1700
|
|
|
1701 if (x == 0)
|
|
|
1702 return val;
|
|
|
1703
|
|
|
1704 code = GET_CODE (x);
|
|
|
1705 val += (int) code + 4095;
|
|
|
1706
|
|
|
1707 /* Some RTL can be compared nonrecursively. */
|
|
|
1708 switch (code)
|
|
|
1709 {
|
|
|
1710 case REG:
|
|
|
1711 return val + REGNO (x);
|
|
|
1712
|
|
|
1713 case LABEL_REF:
|
|
|
1714 return iterative_hash_object (XEXP (x, 0), val);
|
|
|
1715
|
|
|
1716 case SYMBOL_REF:
|
|
|
1717 return iterative_hash_object (XSTR (x, 0), val);
|
|
|
1718
|
|
|
1719 case SCRATCH:
|
|
|
1720 case CONST_DOUBLE:
|
|
|
1721 case CONST_INT:
|
|
|
1722 case CONST_VECTOR:
|
|
|
1723 return val;
|
|
|
1724
|
|
|
1725 default:
|
|
|
1726 break;
|
|
|
1727 }
|
|
|
1728
|
|
|
1729 /* Hash the elements. */
|
|
|
1730 fmt = GET_RTX_FORMAT (code);
|
|
|
1731 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
|
|
|
1732 {
|
|
|
1733 switch (fmt[i])
|
|
|
1734 {
|
|
|
1735 case 'w':
|
|
|
1736 val += XWINT (x, i);
|
|
|
1737 break;
|
|
|
1738
|
|
|
1739 case 'n':
|
|
|
1740 case 'i':
|
|
|
1741 val += XINT (x, i);
|
|
|
1742 break;
|
|
|
1743
|
|
|
1744 case 'V':
|
|
|
1745 case 'E':
|
|
|
1746 val += XVECLEN (x, i);
|
|
|
1747
|
|
|
1748 for (j = 0; j < XVECLEN (x, i); j++)
|
|
|
1749 val += lra_rtx_hash (XVECEXP (x, i, j));
|
|
|
1750 break;
|
|
|
1751
|
|
|
1752 case 'e':
|
|
|
1753 val += lra_rtx_hash (XEXP (x, i));
|
|
|
1754 break;
|
|
|
1755
|
|
|
1756 case 'S':
|
|
|
1757 case 's':
|
|
|
1758 val += htab_hash_string (XSTR (x, i));
|
|
|
1759 break;
|
|
|
1760
|
|
|
1761 case 'u':
|
|
|
1762 case '0':
|
|
|
1763 case 't':
|
|
|
1764 break;
|
|
|
1765
|
|
|
1766 /* It is believed that rtx's at this level will never
|
|
|
1767 contain anything but integers and other rtx's, except for
|
|
|
1768 within LABEL_REFs and SYMBOL_REFs. */
|
|
|
1769 default:
|
|
|
1770 abort ();
|
|
|
1771 }
|
|
|
1772 }
|
|
|
1773 return val;
|
|
|
1774 }
|
|
|
1775
|
|
|
1776
|
|
|
1777
|
|
|
1778 /* This page contains code dealing with stack of the insns which
|
|
|
1779 should be processed by the next constraint pass. */
|
|
|
1780
|
|
|
1781 /* Bitmap used to put an insn on the stack only in one exemplar. */
|
|
|
1782 static sbitmap lra_constraint_insn_stack_bitmap;
|
|
|
1783
|
|
|
1784 /* The stack itself. */
|
|
|
1785 vec<rtx_insn *> lra_constraint_insn_stack;
|
|
|
1786
|
|
|
1787 /* Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg
|
|
|
1788 info for INSN, otherwise only update it if INSN is not already on the
|
|
|
1789 stack. */
|
|
|
1790 static inline void
|
|
|
1791 lra_push_insn_1 (rtx_insn *insn, bool always_update)
|
|
|
1792 {
|
|
|
1793 unsigned int uid = INSN_UID (insn);
|
|
|
1794 if (always_update)
|
|
|
1795 lra_update_insn_regno_info (insn);
|
|
|
1796 if (uid >= SBITMAP_SIZE (lra_constraint_insn_stack_bitmap))
|
|
|
1797 lra_constraint_insn_stack_bitmap =
|
|
|
1798 sbitmap_resize (lra_constraint_insn_stack_bitmap, 3 * uid / 2, 0);
|
|
|
1799 if (bitmap_bit_p (lra_constraint_insn_stack_bitmap, uid))
|
|
|
1800 return;
|
|
|
1801 bitmap_set_bit (lra_constraint_insn_stack_bitmap, uid);
|
|
|
1802 if (! always_update)
|
|
|
1803 lra_update_insn_regno_info (insn);
|
|
|
1804 lra_constraint_insn_stack.safe_push (insn);
|
|
|
1805 }
|
|
|
1806
|
|
|
1807 /* Put INSN on the stack. */
|
|
|
1808 void
|
|
|
1809 lra_push_insn (rtx_insn *insn)
|
|
|
1810 {
|
|
|
1811 lra_push_insn_1 (insn, false);
|
|
|
1812 }
|
|
|
1813
|
|
|
1814 /* Put INSN on the stack and update its reg info. */
|
|
|
1815 void
|
|
|
1816 lra_push_insn_and_update_insn_regno_info (rtx_insn *insn)
|
|
|
1817 {
|
|
|
1818 lra_push_insn_1 (insn, true);
|
|
|
1819 }
|
|
|
1820
|
|
|
1821 /* Put insn with UID on the stack. */
|
|
|
1822 void
|
|
|
1823 lra_push_insn_by_uid (unsigned int uid)
|
|
|
1824 {
|
|
|
1825 lra_push_insn (lra_insn_recog_data[uid]->insn);
|
|
|
1826 }
|
|
|
1827
|
|
|
1828 /* Take the last-inserted insns off the stack and return it. */
|
|
|
1829 rtx_insn *
|
|
|
1830 lra_pop_insn (void)
|
|
|
1831 {
|
|
|
1832 rtx_insn *insn = lra_constraint_insn_stack.pop ();
|
|
|
1833 bitmap_clear_bit (lra_constraint_insn_stack_bitmap, INSN_UID (insn));
|
|
|
1834 return insn;
|
|
|
1835 }
|
|
|
1836
|
|
|
1837 /* Return the current size of the insn stack. */
|
|
|
1838 unsigned int
|
|
|
1839 lra_insn_stack_length (void)
|
|
|
1840 {
|
|
|
1841 return lra_constraint_insn_stack.length ();
|
|
|
1842 }
|
|
|
1843
|
|
|
1844 /* Push insns FROM to TO (excluding it) going in reverse order. */
|
|
|
1845 static void
|
|
|
1846 push_insns (rtx_insn *from, rtx_insn *to)
|
|
|
1847 {
|
|
|
1848 rtx_insn *insn;
|
|
|
1849
|
|
|
1850 if (from == NULL_RTX)
|
|
|
1851 return;
|
|
|
1852 for (insn = from; insn != to; insn = PREV_INSN (insn))
|
|
|
1853 if (INSN_P (insn))
|
|
|
1854 lra_push_insn (insn);
|
|
|
1855 }
|
|
|
1856
|
|
|
1857 /* Set up sp offset for insn in range [FROM, LAST]. The offset is
|
|
|
1858 taken from the next BB insn after LAST or zero if there in such
|
|
|
1859 insn. */
|
|
|
1860 static void
|
|
|
1861 setup_sp_offset (rtx_insn *from, rtx_insn *last)
|
|
|
1862 {
|
|
131
|
1863 rtx_insn *before = next_nonnote_nondebug_insn_bb (last);
|
|
|
1864 poly_int64 offset = (before == NULL_RTX || ! INSN_P (before)
|
|
|
1865 ? 0 : lra_get_insn_recog_data (before)->sp_offset);
|
|
111
|
1866
|
|
|
1867 for (rtx_insn *insn = from; insn != NEXT_INSN (last); insn = NEXT_INSN (insn))
|
|
|
1868 lra_get_insn_recog_data (insn)->sp_offset = offset;
|
|
|
1869 }
|
|
|
1870
|
|
|
1871 /* Emit insns BEFORE before INSN and insns AFTER after INSN. Put the
|
|
|
1872 insns onto the stack. Print about emitting the insns with
|
|
|
1873 TITLE. */
|
|
|
1874 void
|
|
|
1875 lra_process_new_insns (rtx_insn *insn, rtx_insn *before, rtx_insn *after,
|
|
|
1876 const char *title)
|
|
|
1877 {
|
|
|
1878 rtx_insn *last;
|
|
|
1879
|
|
|
1880 if (before == NULL_RTX && after == NULL_RTX)
|
|
|
1881 return;
|
|
|
1882 if (lra_dump_file != NULL)
|
|
|
1883 {
|
|
|
1884 dump_insn_slim (lra_dump_file, insn);
|
|
|
1885 if (before != NULL_RTX)
|
|
|
1886 {
|
|
|
1887 fprintf (lra_dump_file," %s before:\n", title);
|
|
|
1888 dump_rtl_slim (lra_dump_file, before, NULL, -1, 0);
|
|
|
1889 }
|
|
|
1890 if (after != NULL_RTX)
|
|
|
1891 {
|
|
|
1892 fprintf (lra_dump_file, " %s after:\n", title);
|
|
|
1893 dump_rtl_slim (lra_dump_file, after, NULL, -1, 0);
|
|
|
1894 }
|
|
|
1895 fprintf (lra_dump_file, "\n");
|
|
|
1896 }
|
|
|
1897 if (before != NULL_RTX)
|
|
|
1898 {
|
|
|
1899 if (cfun->can_throw_non_call_exceptions)
|
|
|
1900 copy_reg_eh_region_note_forward (insn, before, NULL);
|
|
|
1901 emit_insn_before (before, insn);
|
|
|
1902 push_insns (PREV_INSN (insn), PREV_INSN (before));
|
|
|
1903 setup_sp_offset (before, PREV_INSN (insn));
|
|
|
1904 }
|
|
|
1905 if (after != NULL_RTX)
|
|
|
1906 {
|
|
|
1907 if (cfun->can_throw_non_call_exceptions)
|
|
|
1908 copy_reg_eh_region_note_forward (insn, after, NULL);
|
|
|
1909 for (last = after; NEXT_INSN (last) != NULL_RTX; last = NEXT_INSN (last))
|
|
|
1910 ;
|
|
|
1911 emit_insn_after (after, insn);
|
|
|
1912 push_insns (last, insn);
|
|
|
1913 setup_sp_offset (after, last);
|
|
|
1914 }
|
|
|
1915 if (cfun->can_throw_non_call_exceptions)
|
|
|
1916 {
|
|
|
1917 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
|
|
|
1918 if (note && !insn_could_throw_p (insn))
|
|
|
1919 remove_note (insn, note);
|
|
|
1920 }
|
|
|
1921 }
|
|
|
1922
|
|
|
1923
|
|
|
1924 /* Replace all references to register OLD_REGNO in *LOC with pseudo
|
|
|
1925 register NEW_REG. Try to simplify subreg of constant if SUBREG_P.
|
|
131
|
1926 DEBUG_P is if LOC is within a DEBUG_INSN. Return true if any
|
|
|
1927 change was made. */
|
|
111
|
1928 bool
|
|
131
|
1929 lra_substitute_pseudo (rtx *loc, int old_regno, rtx new_reg, bool subreg_p,
|
|
|
1930 bool debug_p)
|
|
111
|
1931 {
|
|
|
1932 rtx x = *loc;
|
|
|
1933 bool result = false;
|
|
|
1934 enum rtx_code code;
|
|
|
1935 const char *fmt;
|
|
|
1936 int i, j;
|
|
|
1937
|
|
|
1938 if (x == NULL_RTX)
|
|
|
1939 return false;
|
|
|
1940
|
|
|
1941 code = GET_CODE (x);
|
|
|
1942 if (code == SUBREG && subreg_p)
|
|
|
1943 {
|
|
|
1944 rtx subst, inner = SUBREG_REG (x);
|
|
|
1945 /* Transform subreg of constant while we still have inner mode
|
|
|
1946 of the subreg. The subreg internal should not be an insn
|
|
|
1947 operand. */
|
|
|
1948 if (REG_P (inner) && (int) REGNO (inner) == old_regno
|
|
|
1949 && CONSTANT_P (new_reg)
|
|
|
1950 && (subst = simplify_subreg (GET_MODE (x), new_reg, GET_MODE (inner),
|
|
|
1951 SUBREG_BYTE (x))) != NULL_RTX)
|
|
|
1952 {
|
|
|
1953 *loc = subst;
|
|
|
1954 return true;
|
|
|
1955 }
|
|
|
1956
|
|
|
1957 }
|
|
|
1958 else if (code == REG && (int) REGNO (x) == old_regno)
|
|
|
1959 {
|
|
|
1960 machine_mode mode = GET_MODE (x);
|
|
|
1961 machine_mode inner_mode = GET_MODE (new_reg);
|
|
|
1962
|
|
|
1963 if (mode != inner_mode
|
|
|
1964 && ! (CONST_INT_P (new_reg) && SCALAR_INT_MODE_P (mode)))
|
|
|
1965 {
|
|
131
|
1966 poly_uint64 offset = 0;
|
|
|
1967 if (partial_subreg_p (mode, inner_mode)
|
|
|
1968 && SCALAR_INT_MODE_P (inner_mode))
|
|
|
1969 offset = subreg_lowpart_offset (mode, inner_mode);
|
|
|
1970 if (debug_p)
|
|
|
1971 new_reg = gen_rtx_raw_SUBREG (mode, new_reg, offset);
|
|
111
|
1972 else
|
|
131
|
1973 new_reg = gen_rtx_SUBREG (mode, new_reg, offset);
|
|
111
|
1974 }
|
|
|
1975 *loc = new_reg;
|
|
|
1976 return true;
|
|
|
1977 }
|
|
|
1978
|
|
|
1979 /* Scan all the operand sub-expressions. */
|
|
|
1980 fmt = GET_RTX_FORMAT (code);
|
|
|
1981 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
|
|
|
1982 {
|
|
|
1983 if (fmt[i] == 'e')
|
|
|
1984 {
|
|
|
1985 if (lra_substitute_pseudo (&XEXP (x, i), old_regno,
|
|
131
|
1986 new_reg, subreg_p, debug_p))
|
|
111
|
1987 result = true;
|
|
|
1988 }
|
|
|
1989 else if (fmt[i] == 'E')
|
|
|
1990 {
|
|
|
1991 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
|
|
|
1992 if (lra_substitute_pseudo (&XVECEXP (x, i, j), old_regno,
|
|
131
|
1993 new_reg, subreg_p, debug_p))
|
|
111
|
1994 result = true;
|
|
|
1995 }
|
|
|
1996 }
|
|
|
1997 return result;
|
|
|
1998 }
|
|
|
1999
|
|
|
2000 /* Call lra_substitute_pseudo within an insn. Try to simplify subreg
|
|
|
2001 of constant if SUBREG_P. This won't update the insn ptr, just the
|
|
|
2002 contents of the insn. */
|
|
|
2003 bool
|
|
|
2004 lra_substitute_pseudo_within_insn (rtx_insn *insn, int old_regno,
|
|
|
2005 rtx new_reg, bool subreg_p)
|
|
|
2006 {
|
|
|
2007 rtx loc = insn;
|
|
131
|
2008 return lra_substitute_pseudo (&loc, old_regno, new_reg, subreg_p,
|
|
|
2009 DEBUG_INSN_P (insn));
|
|
111
|
2010 }
|
|
|
2011
|
|
|
2012
|
|
|
2013
|
|
|
2014 /* This page contains code dealing with scratches (changing them onto
|
|
|
2015 pseudos and restoring them from the pseudos).
|
|
|
2016
|
|
|
2017 We change scratches into pseudos at the beginning of LRA to
|
|
|
2018 simplify dealing with them (conflicts, hard register assignments).
|
|
|
2019
|
|
|
2020 If the pseudo denoting scratch was spilled it means that we do need
|
|
|
2021 a hard register for it. Such pseudos are transformed back to
|
|
|
2022 scratches at the end of LRA. */
|
|
|
2023
|
|
|
2024 /* Description of location of a former scratch operand. */
|
|
|
2025 struct sloc
|
|
|
2026 {
|
|
|
2027 rtx_insn *insn; /* Insn where the scratch was. */
|
|
|
2028 int nop; /* Number of the operand which was a scratch. */
|
|
|
2029 };
|
|
|
2030
|
|
|
2031 typedef struct sloc *sloc_t;
|
|
|
2032
|
|
|
2033 /* Locations of the former scratches. */
|
|
|
2034 static vec<sloc_t> scratches;
|
|
|
2035
|
|
|
2036 /* Bitmap of scratch regnos. */
|
|
|
2037 static bitmap_head scratch_bitmap;
|
|
|
2038
|
|
|
2039 /* Bitmap of scratch operands. */
|
|
|
2040 static bitmap_head scratch_operand_bitmap;
|
|
|
2041
|
|
|
2042 /* Return true if pseudo REGNO is made of SCRATCH. */
|
|
|
2043 bool
|
|
|
2044 lra_former_scratch_p (int regno)
|
|
|
2045 {
|
|
|
2046 return bitmap_bit_p (&scratch_bitmap, regno);
|
|
|
2047 }
|
|
|
2048
|
|
|
2049 /* Return true if the operand NOP of INSN is a former scratch. */
|
|
|
2050 bool
|
|
|
2051 lra_former_scratch_operand_p (rtx_insn *insn, int nop)
|
|
|
2052 {
|
|
|
2053 return bitmap_bit_p (&scratch_operand_bitmap,
|
|
|
2054 INSN_UID (insn) * MAX_RECOG_OPERANDS + nop) != 0;
|
|
|
2055 }
|
|
|
2056
|
|
|
2057 /* Register operand NOP in INSN as a former scratch. It will be
|
|
|
2058 changed to scratch back, if it is necessary, at the LRA end. */
|
|
|
2059 void
|
|
|
2060 lra_register_new_scratch_op (rtx_insn *insn, int nop)
|
|
|
2061 {
|
|
|
2062 lra_insn_recog_data_t id = lra_get_insn_recog_data (insn);
|
|
|
2063 rtx op = *id->operand_loc[nop];
|
|
|
2064 sloc_t loc = XNEW (struct sloc);
|
|
|
2065 lra_assert (REG_P (op));
|
|
|
2066 loc->insn = insn;
|
|
|
2067 loc->nop = nop;
|
|
|
2068 scratches.safe_push (loc);
|
|
|
2069 bitmap_set_bit (&scratch_bitmap, REGNO (op));
|
|
|
2070 bitmap_set_bit (&scratch_operand_bitmap,
|
|
|
2071 INSN_UID (insn) * MAX_RECOG_OPERANDS + nop);
|
|
|
2072 add_reg_note (insn, REG_UNUSED, op);
|
|
|
2073 }
|
|
|
2074
|
|
|
2075 /* Change scratches onto pseudos and save their location. */
|
|
|
2076 static void
|
|
|
2077 remove_scratches (void)
|
|
|
2078 {
|
|
|
2079 int i;
|
|
|
2080 bool insn_changed_p;
|
|
|
2081 basic_block bb;
|
|
|
2082 rtx_insn *insn;
|
|
|
2083 rtx reg;
|
|
|
2084 lra_insn_recog_data_t id;
|
|
|
2085 struct lra_static_insn_data *static_id;
|
|
|
2086
|
|
|
2087 scratches.create (get_max_uid ());
|
|
|
2088 bitmap_initialize (&scratch_bitmap, ®_obstack);
|
|
|
2089 bitmap_initialize (&scratch_operand_bitmap, ®_obstack);
|
|
|
2090 FOR_EACH_BB_FN (bb, cfun)
|
|
|
2091 FOR_BB_INSNS (bb, insn)
|
|
|
2092 if (INSN_P (insn))
|
|
|
2093 {
|
|
|
2094 id = lra_get_insn_recog_data (insn);
|
|
|
2095 static_id = id->insn_static_data;
|
|
|
2096 insn_changed_p = false;
|
|
|
2097 for (i = 0; i < static_id->n_operands; i++)
|
|
|
2098 if (GET_CODE (*id->operand_loc[i]) == SCRATCH
|
|
|
2099 && GET_MODE (*id->operand_loc[i]) != VOIDmode)
|
|
|
2100 {
|
|
|
2101 insn_changed_p = true;
|
|
|
2102 *id->operand_loc[i] = reg
|
|
|
2103 = lra_create_new_reg (static_id->operand[i].mode,
|
|
|
2104 *id->operand_loc[i], ALL_REGS, NULL);
|
|
|
2105 lra_register_new_scratch_op (insn, i);
|
|
|
2106 if (lra_dump_file != NULL)
|
|
|
2107 fprintf (lra_dump_file,
|
|
|
2108 "Removing SCRATCH in insn #%u (nop %d)\n",
|
|
|
2109 INSN_UID (insn), i);
|
|
|
2110 }
|
|
|
2111 if (insn_changed_p)
|
|
|
2112 /* Because we might use DF right after caller-saves sub-pass
|
|
|
2113 we need to keep DF info up to date. */
|
|
|
2114 df_insn_rescan (insn);
|
|
|
2115 }
|
|
|
2116 }
|
|
|
2117
|
|
|
2118 /* Changes pseudos created by function remove_scratches onto scratches. */
|
|
|
2119 static void
|
|
|
2120 restore_scratches (void)
|
|
|
2121 {
|
|
|
2122 int regno;
|
|
|
2123 unsigned i;
|
|
|
2124 sloc_t loc;
|
|
|
2125 rtx_insn *last = NULL;
|
|
|
2126 lra_insn_recog_data_t id = NULL;
|
|
|
2127
|
|
|
2128 for (i = 0; scratches.iterate (i, &loc); i++)
|
|
|
2129 {
|
|
|
2130 /* Ignore already deleted insns. */
|
|
|
2131 if (NOTE_P (loc->insn)
|
|
|
2132 && NOTE_KIND (loc->insn) == NOTE_INSN_DELETED)
|
|
|
2133 continue;
|
|
|
2134 if (last != loc->insn)
|
|
|
2135 {
|
|
|
2136 last = loc->insn;
|
|
|
2137 id = lra_get_insn_recog_data (last);
|
|
|
2138 }
|
|
|
2139 if (REG_P (*id->operand_loc[loc->nop])
|
|
|
2140 && ((regno = REGNO (*id->operand_loc[loc->nop]))
|
|
|
2141 >= FIRST_PSEUDO_REGISTER)
|
|
|
2142 && lra_get_regno_hard_regno (regno) < 0)
|
|
|
2143 {
|
|
|
2144 /* It should be only case when scratch register with chosen
|
|
|
2145 constraint 'X' did not get memory or hard register. */
|
|
|
2146 lra_assert (lra_former_scratch_p (regno));
|
|
|
2147 *id->operand_loc[loc->nop]
|
|
|
2148 = gen_rtx_SCRATCH (GET_MODE (*id->operand_loc[loc->nop]));
|
|
|
2149 lra_update_dup (id, loc->nop);
|
|
|
2150 if (lra_dump_file != NULL)
|
|
|
2151 fprintf (lra_dump_file, "Restoring SCRATCH in insn #%u(nop %d)\n",
|
|
|
2152 INSN_UID (loc->insn), loc->nop);
|
|
|
2153 }
|
|
|
2154 }
|
|
|
2155 for (i = 0; scratches.iterate (i, &loc); i++)
|
|
|
2156 free (loc);
|
|
|
2157 scratches.release ();
|
|
|
2158 bitmap_clear (&scratch_bitmap);
|
|
|
2159 bitmap_clear (&scratch_operand_bitmap);
|
|
|
2160 }
|
|
|
2161
|
|
|
2162
|
|
|
2163
|
|
|
2164 /* Function checks RTL for correctness. If FINAL_P is true, it is
|
|
|
2165 done at the end of LRA and the check is more rigorous. */
|
|
|
2166 static void
|
|
|
2167 check_rtl (bool final_p)
|
|
|
2168 {
|
|
|
2169 basic_block bb;
|
|
|
2170 rtx_insn *insn;
|
|
|
2171
|
|
|
2172 lra_assert (! final_p || reload_completed);
|
|
|
2173 FOR_EACH_BB_FN (bb, cfun)
|
|
|
2174 FOR_BB_INSNS (bb, insn)
|
|
|
2175 if (NONDEBUG_INSN_P (insn)
|
|
|
2176 && GET_CODE (PATTERN (insn)) != USE
|
|
|
2177 && GET_CODE (PATTERN (insn)) != CLOBBER
|
|
|
2178 && GET_CODE (PATTERN (insn)) != ASM_INPUT)
|
|
|
2179 {
|
|
|
2180 if (final_p)
|
|
|
2181 {
|
|
|
2182 extract_constrain_insn (insn);
|
|
|
2183 continue;
|
|
|
2184 }
|
|
|
2185 /* LRA code is based on assumption that all addresses can be
|
|
|
2186 correctly decomposed. LRA can generate reloads for
|
|
|
2187 decomposable addresses. The decomposition code checks the
|
|
|
2188 correctness of the addresses. So we don't need to check
|
|
|
2189 the addresses here. Don't call insn_invalid_p here, it can
|
|
|
2190 change the code at this stage. */
|
|
|
2191 if (recog_memoized (insn) < 0 && asm_noperands (PATTERN (insn)) < 0)
|
|
|
2192 fatal_insn_not_found (insn);
|
|
|
2193 }
|
|
|
2194 }
|
|
|
2195
|
|
|
2196 /* Determine if the current function has an exception receiver block
|
|
|
2197 that reaches the exit block via non-exceptional edges */
|
|
|
2198 static bool
|
|
|
2199 has_nonexceptional_receiver (void)
|
|
|
2200 {
|
|
|
2201 edge e;
|
|
|
2202 edge_iterator ei;
|
|
|
2203 basic_block *tos, *worklist, bb;
|
|
|
2204
|
|
|
2205 /* If we're not optimizing, then just err on the safe side. */
|
|
|
2206 if (!optimize)
|
|
|
2207 return true;
|
|
|
2208
|
|
|
2209 /* First determine which blocks can reach exit via normal paths. */
|
|
|
2210 tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1);
|
|
|
2211
|
|
|
2212 FOR_EACH_BB_FN (bb, cfun)
|
|
|
2213 bb->flags &= ~BB_REACHABLE;
|
|
|
2214
|
|
|
2215 /* Place the exit block on our worklist. */
|
|
|
2216 EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE;
|
|
|
2217 *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun);
|
|
|
2218
|
|
|
2219 /* Iterate: find everything reachable from what we've already seen. */
|
|
|
2220 while (tos != worklist)
|
|
|
2221 {
|
|
|
2222 bb = *--tos;
|
|
|
2223
|
|
|
2224 FOR_EACH_EDGE (e, ei, bb->preds)
|
|
|
2225 if (e->flags & EDGE_ABNORMAL)
|
|
|
2226 {
|
|
|
2227 free (worklist);
|
|
|
2228 return true;
|
|
|
2229 }
|
|
|
2230 else
|
|
|
2231 {
|
|
|
2232 basic_block src = e->src;
|
|
|
2233
|
|
|
2234 if (!(src->flags & BB_REACHABLE))
|
|
|
2235 {
|
|
|
2236 src->flags |= BB_REACHABLE;
|
|
|
2237 *tos++ = src;
|
|
|
2238 }
|
|
|
2239 }
|
|
|
2240 }
|
|
|
2241 free (worklist);
|
|
|
2242 /* No exceptional block reached exit unexceptionally. */
|
|
|
2243 return false;
|
|
|
2244 }
|
|
|
2245
|
|
|
2246
|
|
|
2247 /* Process recursively X of INSN and add REG_INC notes if necessary. */
|
|
|
2248 static void
|
|
|
2249 add_auto_inc_notes (rtx_insn *insn, rtx x)
|
|
|
2250 {
|
|
|
2251 enum rtx_code code = GET_CODE (x);
|
|
|
2252 const char *fmt;
|
|
|
2253 int i, j;
|
|
|
2254
|
|
|
2255 if (code == MEM && auto_inc_p (XEXP (x, 0)))
|
|
|
2256 {
|
|
|
2257 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
|
|
|
2258 return;
|
|
|
2259 }
|
|
|
2260
|
|
|
2261 /* Scan all X sub-expressions. */
|
|
|
2262 fmt = GET_RTX_FORMAT (code);
|
|
|
2263 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
|
|
|
2264 {
|
|
|
2265 if (fmt[i] == 'e')
|
|
|
2266 add_auto_inc_notes (insn, XEXP (x, i));
|
|
|
2267 else if (fmt[i] == 'E')
|
|
|
2268 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
|
|
|
2269 add_auto_inc_notes (insn, XVECEXP (x, i, j));
|
|
|
2270 }
|
|
|
2271 }
|
|
|
2272
|
|
|
2273
|
|
|
2274 /* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC.
|
|
|
2275 We change pseudos by hard registers without notification of DF and
|
|
|
2276 that can make the notes obsolete. DF-infrastructure does not deal
|
|
|
2277 with REG_INC notes -- so we should regenerate them here. */
|
|
|
2278 static void
|
|
|
2279 update_inc_notes (void)
|
|
|
2280 {
|
|
|
2281 rtx *pnote;
|
|
|
2282 basic_block bb;
|
|
|
2283 rtx_insn *insn;
|
|
|
2284
|
|
|
2285 FOR_EACH_BB_FN (bb, cfun)
|
|
|
2286 FOR_BB_INSNS (bb, insn)
|
|
|
2287 if (NONDEBUG_INSN_P (insn))
|
|
|
2288 {
|
|
|
2289 pnote = ®_NOTES (insn);
|
|
|
2290 while (*pnote != 0)
|
|
|
2291 {
|
|
|
2292 if (REG_NOTE_KIND (*pnote) == REG_DEAD
|
|
|
2293 || REG_NOTE_KIND (*pnote) == REG_UNUSED
|
|
|
2294 || REG_NOTE_KIND (*pnote) == REG_INC)
|
|
|
2295 *pnote = XEXP (*pnote, 1);
|
|
|
2296 else
|
|
|
2297 pnote = &XEXP (*pnote, 1);
|
|
|
2298 }
|
|
|
2299
|
|
|
2300 if (AUTO_INC_DEC)
|
|
|
2301 add_auto_inc_notes (insn, PATTERN (insn));
|
|
|
2302 }
|
|
|
2303 }
|
|
|
2304
|
|
|
2305 /* Set to 1 while in lra. */
|
|
|
2306 int lra_in_progress;
|
|
|
2307
|
|
|
2308 /* Start of pseudo regnos before the LRA. */
|
|
|
2309 int lra_new_regno_start;
|
|
|
2310
|
|
|
2311 /* Start of reload pseudo regnos before the new spill pass. */
|
|
|
2312 int lra_constraint_new_regno_start;
|
|
|
2313
|
|
|
2314 /* Avoid spilling pseudos with regno more than the following value if
|
|
|
2315 it is possible. */
|
|
|
2316 int lra_bad_spill_regno_start;
|
|
|
2317
|
|
|
2318 /* Inheritance pseudo regnos before the new spill pass. */
|
|
|
2319 bitmap_head lra_inheritance_pseudos;
|
|
|
2320
|
|
|
2321 /* Split regnos before the new spill pass. */
|
|
|
2322 bitmap_head lra_split_regs;
|
|
|
2323
|
|
|
2324 /* Reload pseudo regnos before the new assignment pass which still can
|
|
|
2325 be spilled after the assignment pass as memory is also accepted in
|
|
|
2326 insns for the reload pseudos. */
|
|
|
2327 bitmap_head lra_optional_reload_pseudos;
|
|
|
2328
|
|
|
2329 /* Pseudo regnos used for subreg reloads before the new assignment
|
|
|
2330 pass. Such pseudos still can be spilled after the assignment
|
|
|
2331 pass. */
|
|
|
2332 bitmap_head lra_subreg_reload_pseudos;
|
|
|
2333
|
|
|
2334 /* File used for output of LRA debug information. */
|
|
|
2335 FILE *lra_dump_file;
|
|
|
2336
|
|
|
2337 /* True if we should try spill into registers of different classes
|
|
|
2338 instead of memory. */
|
|
|
2339 bool lra_reg_spill_p;
|
|
|
2340
|
|
|
2341 /* Set up value LRA_REG_SPILL_P. */
|
|
|
2342 static void
|
|
|
2343 setup_reg_spill_flag (void)
|
|
|
2344 {
|
|
|
2345 int cl, mode;
|
|
|
2346
|
|
|
2347 if (targetm.spill_class != NULL)
|
|
|
2348 for (cl = 0; cl < (int) LIM_REG_CLASSES; cl++)
|
|
|
2349 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
|
|
|
2350 if (targetm.spill_class ((enum reg_class) cl,
|
|
|
2351 (machine_mode) mode) != NO_REGS)
|
|
|
2352 {
|
|
|
2353 lra_reg_spill_p = true;
|
|
|
2354 return;
|
|
|
2355 }
|
|
|
2356 lra_reg_spill_p = false;
|
|
|
2357 }
|
|
|
2358
|
|
|
2359 /* True if the current function is too big to use regular algorithms
|
|
|
2360 in LRA. In other words, we should use simpler and faster algorithms
|
|
|
2361 in LRA. It also means we should not worry about generation code
|
|
|
2362 for caller saves. The value is set up in IRA. */
|
|
|
2363 bool lra_simple_p;
|
|
|
2364
|
|
|
2365 /* Major LRA entry function. F is a file should be used to dump LRA
|
|
|
2366 debug info. */
|
|
|
2367 void
|
|
|
2368 lra (FILE *f)
|
|
|
2369 {
|
|
|
2370 int i;
|
|
|
2371 bool live_p, inserted_p;
|
|
|
2372
|
|
|
2373 lra_dump_file = f;
|
|
|
2374
|
|
|
2375 timevar_push (TV_LRA);
|
|
|
2376
|
|
|
2377 /* Make sure that the last insn is a note. Some subsequent passes
|
|
|
2378 need it. */
|
|
|
2379 emit_note (NOTE_INSN_DELETED);
|
|
|
2380
|
|
|
2381 COPY_HARD_REG_SET (lra_no_alloc_regs, ira_no_alloc_regs);
|
|
|
2382
|
|
|
2383 init_reg_info ();
|
|
|
2384 expand_reg_info ();
|
|
|
2385
|
|
|
2386 init_insn_recog_data ();
|
|
|
2387
|
|
|
2388 /* Some quick check on RTL generated by previous passes. */
|
|
|
2389 if (flag_checking)
|
|
|
2390 check_rtl (false);
|
|
|
2391
|
|
|
2392 lra_in_progress = 1;
|
|
|
2393
|
|
|
2394 lra_live_range_iter = lra_coalesce_iter = lra_constraint_iter = 0;
|
|
|
2395 lra_assignment_iter = lra_assignment_iter_after_spill = 0;
|
|
|
2396 lra_inheritance_iter = lra_undo_inheritance_iter = 0;
|
|
|
2397 lra_rematerialization_iter = 0;
|
|
|
2398
|
|
|
2399 setup_reg_spill_flag ();
|
|
|
2400
|
|
|
2401 /* Function remove_scratches can creates new pseudos for clobbers --
|
|
|
2402 so set up lra_constraint_new_regno_start before its call to
|
|
|
2403 permit changing reg classes for pseudos created by this
|
|
|
2404 simplification. */
|
|
|
2405 lra_constraint_new_regno_start = lra_new_regno_start = max_reg_num ();
|
|
|
2406 lra_bad_spill_regno_start = INT_MAX;
|
|
|
2407 remove_scratches ();
|
|
|
2408
|
|
|
2409 /* A function that has a non-local label that can reach the exit
|
|
|
2410 block via non-exceptional paths must save all call-saved
|
|
|
2411 registers. */
|
|
|
2412 if (cfun->has_nonlocal_label && has_nonexceptional_receiver ())
|
|
|
2413 crtl->saves_all_registers = 1;
|
|
|
2414
|
|
|
2415 if (crtl->saves_all_registers)
|
|
|
2416 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
|
|
|
2417 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
|
|
|
2418 df_set_regs_ever_live (i, true);
|
|
|
2419
|
|
|
2420 /* We don't DF from now and avoid its using because it is to
|
|
|
2421 expensive when a lot of RTL changes are made. */
|
|
|
2422 df_set_flags (DF_NO_INSN_RESCAN);
|
|
|
2423 lra_constraint_insn_stack.create (get_max_uid ());
|
|
|
2424 lra_constraint_insn_stack_bitmap = sbitmap_alloc (get_max_uid ());
|
|
|
2425 bitmap_clear (lra_constraint_insn_stack_bitmap);
|
|
|
2426 lra_live_ranges_init ();
|
|
|
2427 lra_constraints_init ();
|
|
|
2428 lra_curr_reload_num = 0;
|
|
|
2429 push_insns (get_last_insn (), NULL);
|
|
|
2430 /* It is needed for the 1st coalescing. */
|
|
|
2431 bitmap_initialize (&lra_inheritance_pseudos, ®_obstack);
|
|
|
2432 bitmap_initialize (&lra_split_regs, ®_obstack);
|
|
|
2433 bitmap_initialize (&lra_optional_reload_pseudos, ®_obstack);
|
|
|
2434 bitmap_initialize (&lra_subreg_reload_pseudos, ®_obstack);
|
|
|
2435 live_p = false;
|
|
131
|
2436 if (maybe_ne (get_frame_size (), 0) && crtl->stack_alignment_needed)
|
|
111
|
2437 /* If we have a stack frame, we must align it now. The stack size
|
|
|
2438 may be a part of the offset computation for register
|
|
|
2439 elimination. */
|
|
|
2440 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
|
|
|
2441 lra_init_equiv ();
|
|
|
2442 for (;;)
|
|
|
2443 {
|
|
|
2444 for (;;)
|
|
|
2445 {
|
|
|
2446 bool reloads_p = lra_constraints (lra_constraint_iter == 0);
|
|
|
2447 /* Constraint transformations may result in that eliminable
|
|
|
2448 hard regs become uneliminable and pseudos which use them
|
|
|
2449 should be spilled. It is better to do it before pseudo
|
|
|
2450 assignments.
|
|
|
2451
|
|
|
2452 For example, rs6000 can make
|
|
|
2453 RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started
|
|
|
2454 to use a constant pool. */
|
|
|
2455 lra_eliminate (false, false);
|
|
|
2456 /* We should try to assign hard registers to scratches even
|
|
|
2457 if there were no RTL transformations in lra_constraints.
|
|
|
2458 Also we should check IRA assignments on the first
|
|
|
2459 iteration as they can be wrong because of early clobbers
|
|
|
2460 operands which are ignored in IRA. */
|
|
|
2461 if (! reloads_p && lra_constraint_iter > 1)
|
|
|
2462 {
|
|
|
2463 /* Stack is not empty here only when there are changes
|
|
|
2464 during the elimination sub-pass. */
|
|
|
2465 if (bitmap_empty_p (lra_constraint_insn_stack_bitmap))
|
|
|
2466 break;
|
|
|
2467 else
|
|
|
2468 /* If there are no reloads but changing due
|
|
|
2469 elimination, restart the constraint sub-pass
|
|
|
2470 first. */
|
|
|
2471 continue;
|
|
|
2472 }
|
|
|
2473 /* Do inheritance only for regular algorithms. */
|
|
|
2474 if (! lra_simple_p)
|
|
|
2475 {
|
|
|
2476 if (flag_ipa_ra)
|
|
|
2477 {
|
|
|
2478 if (live_p)
|
|
|
2479 lra_clear_live_ranges ();
|
|
|
2480 /* As a side-effect of lra_create_live_ranges, we calculate
|
|
|
2481 actual_call_used_reg_set, which is needed during
|
|
|
2482 lra_inheritance. */
|
|
|
2483 lra_create_live_ranges (true, true);
|
|
|
2484 live_p = true;
|
|
|
2485 }
|
|
|
2486 lra_inheritance ();
|
|
|
2487 }
|
|
|
2488 if (live_p)
|
|
|
2489 lra_clear_live_ranges ();
|
|
131
|
2490 bool fails_p;
|
|
|
2491 do
|
|
111
|
2492 {
|
|
131
|
2493 /* We need live ranges for lra_assign -- so build them.
|
|
|
2494 But don't remove dead insns or change global live
|
|
|
2495 info as we can undo inheritance transformations after
|
|
|
2496 inheritance pseudo assigning. */
|
|
|
2497 lra_create_live_ranges (true, false);
|
|
|
2498 live_p = true;
|
|
|
2499 /* If we don't spill non-reload and non-inheritance
|
|
|
2500 pseudos, there is no sense to run memory-memory move
|
|
|
2501 coalescing. If inheritance pseudos were spilled, the
|
|
|
2502 memory-memory moves involving them will be removed by
|
|
|
2503 pass undoing inheritance. */
|
|
|
2504 if (lra_simple_p)
|
|
|
2505 lra_assign (fails_p);
|
|
|
2506 else
|
|
111
|
2507 {
|
|
131
|
2508 bool spill_p = !lra_assign (fails_p);
|
|
|
2509
|
|
|
2510 if (lra_undo_inheritance ())
|
|
|
2511 live_p = false;
|
|
|
2512 if (spill_p && ! fails_p)
|
|
111
|
2513 {
|
|
131
|
2514 if (! live_p)
|
|
|
2515 {
|
|
|
2516 lra_create_live_ranges (true, true);
|
|
|
2517 live_p = true;
|
|
|
2518 }
|
|
|
2519 if (lra_coalesce ())
|
|
|
2520 live_p = false;
|
|
111
|
2521 }
|
|
131
|
2522 if (! live_p)
|
|
|
2523 lra_clear_live_ranges ();
|
|
111
|
2524 }
|
|
131
|
2525 if (fails_p)
|
|
|
2526 {
|
|
|
2527 /* It is a very rare case. It is the last hope to
|
|
|
2528 split a hard regno live range for a reload
|
|
|
2529 pseudo. */
|
|
|
2530 if (live_p)
|
|
|
2531 lra_clear_live_ranges ();
|
|
|
2532 live_p = false;
|
|
|
2533 if (! lra_split_hard_reg_for ())
|
|
|
2534 break;
|
|
|
2535 }
|
|
111
|
2536 }
|
|
131
|
2537 while (fails_p);
|
|
111
|
2538 }
|
|
|
2539 /* Don't clear optional reloads bitmap until all constraints are
|
|
|
2540 satisfied as we need to differ them from regular reloads. */
|
|
|
2541 bitmap_clear (&lra_optional_reload_pseudos);
|
|
|
2542 bitmap_clear (&lra_subreg_reload_pseudos);
|
|
|
2543 bitmap_clear (&lra_inheritance_pseudos);
|
|
|
2544 bitmap_clear (&lra_split_regs);
|
|
|
2545 if (! live_p)
|
|
|
2546 {
|
|
|
2547 /* We need full live info for spilling pseudos into
|
|
|
2548 registers instead of memory. */
|
|
|
2549 lra_create_live_ranges (lra_reg_spill_p, true);
|
|
|
2550 live_p = true;
|
|
|
2551 }
|
|
|
2552 /* We should check necessity for spilling here as the above live
|
|
|
2553 range pass can remove spilled pseudos. */
|
|
|
2554 if (! lra_need_for_spills_p ())
|
|
|
2555 break;
|
|
|
2556 /* Now we know what pseudos should be spilled. Try to
|
|
|
2557 rematerialize them first. */
|
|
|
2558 if (lra_remat ())
|
|
|
2559 {
|
|
|
2560 /* We need full live info -- see the comment above. */
|
|
|
2561 lra_create_live_ranges (lra_reg_spill_p, true);
|
|
|
2562 live_p = true;
|
|
|
2563 if (! lra_need_for_spills_p ())
|
|
|
2564 break;
|
|
|
2565 }
|
|
|
2566 lra_spill ();
|
|
|
2567 /* Assignment of stack slots changes elimination offsets for
|
|
|
2568 some eliminations. So update the offsets here. */
|
|
|
2569 lra_eliminate (false, false);
|
|
|
2570 lra_constraint_new_regno_start = max_reg_num ();
|
|
|
2571 if (lra_bad_spill_regno_start == INT_MAX
|
|
|
2572 && lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES
|
|
|
2573 && lra_rematerialization_iter > LRA_MAX_REMATERIALIZATION_PASSES)
|
|
|
2574 /* After switching off inheritance and rematerialization
|
|
|
2575 passes, avoid spilling reload pseudos will be created to
|
|
|
2576 prevent LRA cycling in some complicated cases. */
|
|
|
2577 lra_bad_spill_regno_start = lra_constraint_new_regno_start;
|
|
|
2578 lra_assignment_iter_after_spill = 0;
|
|
|
2579 }
|
|
|
2580 restore_scratches ();
|
|
|
2581 lra_eliminate (true, false);
|
|
|
2582 lra_final_code_change ();
|
|
|
2583 lra_in_progress = 0;
|
|
|
2584 if (live_p)
|
|
|
2585 lra_clear_live_ranges ();
|
|
|
2586 lra_live_ranges_finish ();
|
|
|
2587 lra_constraints_finish ();
|
|
|
2588 finish_reg_info ();
|
|
|
2589 sbitmap_free (lra_constraint_insn_stack_bitmap);
|
|
|
2590 lra_constraint_insn_stack.release ();
|
|
|
2591 finish_insn_recog_data ();
|
|
|
2592 regstat_free_n_sets_and_refs ();
|
|
|
2593 regstat_free_ri ();
|
|
|
2594 reload_completed = 1;
|
|
|
2595 update_inc_notes ();
|
|
|
2596
|
|
|
2597 inserted_p = fixup_abnormal_edges ();
|
|
|
2598
|
|
|
2599 /* We've possibly turned single trapping insn into multiple ones. */
|
|
|
2600 if (cfun->can_throw_non_call_exceptions)
|
|
|
2601 {
|
|
|
2602 auto_sbitmap blocks (last_basic_block_for_fn (cfun));
|
|
|
2603 bitmap_ones (blocks);
|
|
|
2604 find_many_sub_basic_blocks (blocks);
|
|
|
2605 }
|
|
|
2606
|
|
|
2607 if (inserted_p)
|
|
|
2608 commit_edge_insertions ();
|
|
|
2609
|
|
|
2610 /* Replacing pseudos with their memory equivalents might have
|
|
|
2611 created shared rtx. Subsequent passes would get confused
|
|
|
2612 by this, so unshare everything here. */
|
|
|
2613 unshare_all_rtl_again (get_insns ());
|
|
|
2614
|
|
|
2615 if (flag_checking)
|
|
|
2616 check_rtl (true);
|
|
|
2617
|
|
|
2618 timevar_pop (TV_LRA);
|
|
|
2619 }
|
|
|
2620
|
|
|
2621 /* Called once per compiler to initialize LRA data once. */
|
|
|
2622 void
|
|
|
2623 lra_init_once (void)
|
|
|
2624 {
|
|
|
2625 init_insn_code_data_once ();
|
|
|
2626 }
|
|
|
2627
|
|
|
2628 /* Called once per compiler to finish LRA data which are initialize
|
|
|
2629 once. */
|
|
|
2630 void
|
|
|
2631 lra_finish_once (void)
|
|
|
2632 {
|
|
|
2633 finish_insn_code_data_once ();
|
|
|
2634 }
|
