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1 ;; Decimal Floating Point (DFP) patterns.
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2 ;; Copyright (C) 2007, 2008
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3 ;; Free Software Foundation, Inc.
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4 ;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner
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5 ;; (bergner@vnet.ibm.com).
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6
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7 ;; This file is part of GCC.
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8
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9 ;; GCC is free software; you can redistribute it and/or modify it
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10 ;; under the terms of the GNU General Public License as published
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11 ;; by the Free Software Foundation; either version 3, or (at your
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12 ;; option) any later version.
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13
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14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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17 ;; License for more details.
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18
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19 ;; You should have received a copy of the GNU General Public License
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20 ;; along with GCC; see the file COPYING3. If not see
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21 ;; <http://www.gnu.org/licenses/>.
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22
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23 ;;
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24 ;; UNSPEC usage
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25 ;;
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26
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27 (define_constants
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28 [(UNSPEC_MOVSD_LOAD 400)
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29 (UNSPEC_MOVSD_STORE 401)
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30 ])
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31
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32
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33 (define_expand "movsd"
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34 [(set (match_operand:SD 0 "nonimmediate_operand" "")
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35 (match_operand:SD 1 "any_operand" ""))]
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36 "TARGET_HARD_FLOAT && TARGET_FPRS"
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37 "{ rs6000_emit_move (operands[0], operands[1], SDmode); DONE; }")
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38
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39 (define_split
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40 [(set (match_operand:SD 0 "gpc_reg_operand" "")
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41 (match_operand:SD 1 "const_double_operand" ""))]
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42 "reload_completed
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43 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
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44 || (GET_CODE (operands[0]) == SUBREG
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45 && GET_CODE (SUBREG_REG (operands[0])) == REG
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46 && REGNO (SUBREG_REG (operands[0])) <= 31))"
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47 [(set (match_dup 2) (match_dup 3))]
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48 "
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49 {
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50 long l;
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51 REAL_VALUE_TYPE rv;
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52
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53 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
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54 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
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55
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56 if (! TARGET_POWERPC64)
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57 operands[2] = operand_subword (operands[0], 0, 0, SDmode);
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58 else
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59 operands[2] = gen_lowpart (SImode, operands[0]);
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60
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61 operands[3] = gen_int_mode (l, SImode);
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62 }")
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63
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64 (define_insn "movsd_hardfloat"
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65 [(set (match_operand:SD 0 "nonimmediate_operand" "=r,r,m,f,*c*l,*q,!r,*h,!r,!r")
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66 (match_operand:SD 1 "input_operand" "r,m,r,f,r,r,h,0,G,Fn"))]
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67 "(gpc_reg_operand (operands[0], SDmode)
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68 || gpc_reg_operand (operands[1], SDmode))
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69 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
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70 "@
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71 mr %0,%1
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72 {l%U1%X1|lwz%U1%X1} %0,%1
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73 {st%U0%X0|stw%U0%X0} %1,%0
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74 fmr %0,%1
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75 mt%0 %1
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76 mt%0 %1
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77 mf%1 %0
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78 {cror 0,0,0|nop}
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79 #
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80 #"
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81 [(set_attr "type" "*,load,store,fp,mtjmpr,*,mfjmpr,*,*,*")
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82 (set_attr "length" "4,4,4,4,4,4,4,4,4,8")])
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83
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84 (define_insn "movsd_softfloat"
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85 [(set (match_operand:SD 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
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86 (match_operand:SD 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
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87 "(gpc_reg_operand (operands[0], SDmode)
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88 || gpc_reg_operand (operands[1], SDmode))
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89 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
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90 "@
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91 mr %0,%1
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92 mt%0 %1
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93 mt%0 %1
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94 mf%1 %0
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95 {l%U1%X1|lwz%U1%X1} %0,%1
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96 {st%U0%X0|stw%U0%X0} %1,%0
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97 {lil|li} %0,%1
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98 {liu|lis} %0,%v1
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99 {cal|la} %0,%a1
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100 #
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101 #
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102 {cror 0,0,0|nop}"
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103 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
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104 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
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105
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106 (define_insn "movsd_store"
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107 [(set (match_operand:DD 0 "nonimmediate_operand" "=m")
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108 (unspec:DD [(match_operand:SD 1 "input_operand" "f")]
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109 UNSPEC_MOVSD_STORE))]
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110 "(gpc_reg_operand (operands[0], DDmode)
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111 || gpc_reg_operand (operands[1], SDmode))
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112 && TARGET_HARD_FLOAT && TARGET_FPRS"
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113 "stfd%U0%X0 %1,%0"
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114 [(set_attr "type" "fpstore")
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115 (set_attr "length" "4")])
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116
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117 (define_insn "movsd_load"
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118 [(set (match_operand:SD 0 "nonimmediate_operand" "=f")
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119 (unspec:SD [(match_operand:DD 1 "input_operand" "m")]
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120 UNSPEC_MOVSD_LOAD))]
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121 "(gpc_reg_operand (operands[0], SDmode)
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122 || gpc_reg_operand (operands[1], DDmode))
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123 && TARGET_HARD_FLOAT && TARGET_FPRS"
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124 "lfd%U1%X1 %0,%1"
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125 [(set_attr "type" "fpload")
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126 (set_attr "length" "4")])
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127
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128 ;; Hardware support for decimal floating point operations.
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129
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130 (define_insn "extendsddd2"
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131 [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
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132 (float_extend:DD (match_operand:SD 1 "gpc_reg_operand" "f")))]
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133 "TARGET_DFP"
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134 "dctdp %0,%1"
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135 [(set_attr "type" "fp")])
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136
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137 (define_expand "extendsdtd2"
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138 [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
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139 (float_extend:TD (match_operand:SD 1 "gpc_reg_operand" "f")))]
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140 "TARGET_DFP"
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141 {
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142 rtx tmp = gen_reg_rtx (DDmode);
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143 emit_insn (gen_extendsddd2 (tmp, operands[1]));
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144 emit_insn (gen_extendddtd2 (operands[0], tmp));
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145 DONE;
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146 })
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147
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148 (define_insn "truncddsd2"
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149 [(set (match_operand:SD 0 "gpc_reg_operand" "=f")
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150 (float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "f")))]
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151 "TARGET_DFP"
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152 "drsp %0,%1"
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153 [(set_attr "type" "fp")])
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154
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155 (define_expand "negdd2"
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156 [(set (match_operand:DD 0 "gpc_reg_operand" "")
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157 (neg:DD (match_operand:DD 1 "gpc_reg_operand" "")))]
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158 "TARGET_HARD_FLOAT && TARGET_FPRS"
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159 "")
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160
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161 (define_insn "*negdd2_fpr"
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162 [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
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163 (neg:DD (match_operand:DD 1 "gpc_reg_operand" "f")))]
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164 "TARGET_HARD_FLOAT && TARGET_FPRS"
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165 "fneg %0,%1"
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166 [(set_attr "type" "fp")])
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167
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168 (define_expand "absdd2"
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169 [(set (match_operand:DD 0 "gpc_reg_operand" "")
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170 (abs:DD (match_operand:DD 1 "gpc_reg_operand" "")))]
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171 "TARGET_HARD_FLOAT && TARGET_FPRS"
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172 "")
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173
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174 (define_insn "*absdd2_fpr"
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175 [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
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176 (abs:DD (match_operand:DD 1 "gpc_reg_operand" "f")))]
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177 "TARGET_HARD_FLOAT && TARGET_FPRS"
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178 "fabs %0,%1"
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179 [(set_attr "type" "fp")])
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180
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181 (define_insn "*nabsdd2_fpr"
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182 [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
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183 (neg:DD (abs:DD (match_operand:DF 1 "gpc_reg_operand" "f"))))]
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184 "TARGET_HARD_FLOAT && TARGET_FPRS"
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185 "fnabs %0,%1"
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186 [(set_attr "type" "fp")])
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187
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188 (define_expand "movdd"
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189 [(set (match_operand:DD 0 "nonimmediate_operand" "")
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190 (match_operand:DD 1 "any_operand" ""))]
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191 ""
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192 "{ rs6000_emit_move (operands[0], operands[1], DDmode); DONE; }")
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193
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194 (define_split
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195 [(set (match_operand:DD 0 "gpc_reg_operand" "")
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196 (match_operand:DD 1 "const_int_operand" ""))]
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197 "! TARGET_POWERPC64 && reload_completed
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198 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
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199 || (GET_CODE (operands[0]) == SUBREG
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200 && GET_CODE (SUBREG_REG (operands[0])) == REG
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201 && REGNO (SUBREG_REG (operands[0])) <= 31))"
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202 [(set (match_dup 2) (match_dup 4))
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203 (set (match_dup 3) (match_dup 1))]
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204 "
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205 {
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206 int endian = (WORDS_BIG_ENDIAN == 0);
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207 HOST_WIDE_INT value = INTVAL (operands[1]);
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208
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209 operands[2] = operand_subword (operands[0], endian, 0, DDmode);
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210 operands[3] = operand_subword (operands[0], 1 - endian, 0, DDmode);
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211 #if HOST_BITS_PER_WIDE_INT == 32
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212 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
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213 #else
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214 operands[4] = GEN_INT (value >> 32);
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215 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
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216 #endif
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217 }")
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218
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219 (define_split
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220 [(set (match_operand:DD 0 "gpc_reg_operand" "")
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221 (match_operand:DD 1 "const_double_operand" ""))]
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222 "! TARGET_POWERPC64 && reload_completed
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223 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
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224 || (GET_CODE (operands[0]) == SUBREG
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225 && GET_CODE (SUBREG_REG (operands[0])) == REG
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226 && REGNO (SUBREG_REG (operands[0])) <= 31))"
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227 [(set (match_dup 2) (match_dup 4))
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228 (set (match_dup 3) (match_dup 5))]
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229 "
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230 {
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231 int endian = (WORDS_BIG_ENDIAN == 0);
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232 long l[2];
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233 REAL_VALUE_TYPE rv;
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234
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235 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
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236 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
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237
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238 operands[2] = operand_subword (operands[0], endian, 0, DDmode);
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239 operands[3] = operand_subword (operands[0], 1 - endian, 0, DDmode);
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240 operands[4] = gen_int_mode (l[endian], SImode);
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241 operands[5] = gen_int_mode (l[1 - endian], SImode);
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242 }")
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243
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244 (define_split
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245 [(set (match_operand:DD 0 "gpc_reg_operand" "")
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246 (match_operand:DD 1 "const_double_operand" ""))]
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247 "TARGET_POWERPC64 && reload_completed
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248 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
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249 || (GET_CODE (operands[0]) == SUBREG
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250 && GET_CODE (SUBREG_REG (operands[0])) == REG
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251 && REGNO (SUBREG_REG (operands[0])) <= 31))"
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252 [(set (match_dup 2) (match_dup 3))]
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253 "
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254 {
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255 int endian = (WORDS_BIG_ENDIAN == 0);
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256 long l[2];
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257 REAL_VALUE_TYPE rv;
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258 #if HOST_BITS_PER_WIDE_INT >= 64
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259 HOST_WIDE_INT val;
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260 #endif
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261
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262 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
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263 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
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264
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265 operands[2] = gen_lowpart (DImode, operands[0]);
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266 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
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267 #if HOST_BITS_PER_WIDE_INT >= 64
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268 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
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269 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
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270
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271 operands[3] = gen_int_mode (val, DImode);
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272 #else
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273 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
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274 #endif
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275 }")
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276
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277 ;; Don't have reload use general registers to load a constant. First,
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278 ;; it might not work if the output operand is the equivalent of
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279 ;; a non-offsettable memref, but also it is less efficient than loading
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280 ;; the constant into an FP register, since it will probably be used there.
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281 ;; The "??" is a kludge until we can figure out a more reasonable way
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282 ;; of handling these non-offsettable values.
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283 (define_insn "*movdd_hardfloat32"
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284 [(set (match_operand:DD 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
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285 (match_operand:DD 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
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286 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
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287 && (gpc_reg_operand (operands[0], DDmode)
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288 || gpc_reg_operand (operands[1], DDmode))"
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289 "*
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290 {
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291 switch (which_alternative)
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292 {
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293 default:
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294 gcc_unreachable ();
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295 case 0:
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296 /* We normally copy the low-numbered register first. However, if
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297 the first register operand 0 is the same as the second register
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298 of operand 1, we must copy in the opposite order. */
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299 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
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300 return \"mr %L0,%L1\;mr %0,%1\";
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301 else
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302 return \"mr %0,%1\;mr %L0,%L1\";
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303 case 1:
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304 if (rs6000_offsettable_memref_p (operands[1])
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305 || (GET_CODE (operands[1]) == MEM
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306 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
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307 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
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308 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
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309 {
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310 /* If the low-address word is used in the address, we must load
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311 it last. Otherwise, load it first. Note that we cannot have
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312 auto-increment in that case since the address register is
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313 known to be dead. */
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314 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
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315 operands[1], 0))
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316 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
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317 else
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318 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
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319 }
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320 else
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321 {
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322 rtx addreg;
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323
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324 addreg = find_addr_reg (XEXP (operands[1], 0));
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325 if (refers_to_regno_p (REGNO (operands[0]),
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326 REGNO (operands[0]) + 1,
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327 operands[1], 0))
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328 {
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329 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
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330 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
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331 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
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332 return \"{lx|lwzx} %0,%1\";
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333 }
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334 else
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335 {
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336 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
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337 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
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338 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
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339 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
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340 return \"\";
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341 }
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342 }
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343 case 2:
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344 if (rs6000_offsettable_memref_p (operands[0])
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345 || (GET_CODE (operands[0]) == MEM
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346 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
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347 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
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348 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
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349 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
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350 else
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351 {
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352 rtx addreg;
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353
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354 addreg = find_addr_reg (XEXP (operands[0], 0));
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355 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
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356 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
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357 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
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358 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
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359 return \"\";
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360 }
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361 case 3:
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362 return \"fmr %0,%1\";
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363 case 4:
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364 return \"lfd%U1%X1 %0,%1\";
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365 case 5:
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366 return \"stfd%U0%X0 %1,%0\";
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367 case 6:
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368 case 7:
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369 case 8:
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370 return \"#\";
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371 }
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372 }"
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373 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
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374 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
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375
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376 (define_insn "*movdd_softfloat32"
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377 [(set (match_operand:DD 0 "nonimmediate_operand" "=r,r,m,r,r,r")
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378 (match_operand:DD 1 "input_operand" "r,m,r,G,H,F"))]
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379 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
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380 && (gpc_reg_operand (operands[0], DDmode)
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381 || gpc_reg_operand (operands[1], DDmode))"
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382 "*
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383 {
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384 switch (which_alternative)
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385 {
|
|
386 default:
|
|
387 gcc_unreachable ();
|
|
388 case 0:
|
|
389 /* We normally copy the low-numbered register first. However, if
|
|
390 the first register operand 0 is the same as the second register of
|
|
391 operand 1, we must copy in the opposite order. */
|
|
392 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
|
|
393 return \"mr %L0,%L1\;mr %0,%1\";
|
|
394 else
|
|
395 return \"mr %0,%1\;mr %L0,%L1\";
|
|
396 case 1:
|
|
397 /* If the low-address word is used in the address, we must load
|
|
398 it last. Otherwise, load it first. Note that we cannot have
|
|
399 auto-increment in that case since the address register is
|
|
400 known to be dead. */
|
|
401 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
|
|
402 operands[1], 0))
|
|
403 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
|
|
404 else
|
|
405 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
|
|
406 case 2:
|
|
407 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
|
|
408 case 3:
|
|
409 case 4:
|
|
410 case 5:
|
|
411 return \"#\";
|
|
412 }
|
|
413 }"
|
|
414 [(set_attr "type" "two,load,store,*,*,*")
|
|
415 (set_attr "length" "8,8,8,8,12,16")])
|
|
416
|
|
417 ; ld/std require word-aligned displacements -> 'Y' constraint.
|
|
418 ; List Y->r and r->Y before r->r for reload.
|
|
419 (define_insn "*movdd_hardfloat64_mfpgpr"
|
|
420 [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
|
|
421 (match_operand:DD 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
|
|
422 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
423 && (gpc_reg_operand (operands[0], DDmode)
|
|
424 || gpc_reg_operand (operands[1], DDmode))"
|
|
425 "@
|
|
426 std%U0%X0 %1,%0
|
|
427 ld%U1%X1 %0,%1
|
|
428 mr %0,%1
|
|
429 fmr %0,%1
|
|
430 lfd%U1%X1 %0,%1
|
|
431 stfd%U0%X0 %1,%0
|
|
432 mt%0 %1
|
|
433 mf%1 %0
|
|
434 {cror 0,0,0|nop}
|
|
435 #
|
|
436 #
|
|
437 #
|
|
438 mftgpr %0,%1
|
|
439 mffgpr %0,%1"
|
|
440 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
|
|
441 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
|
|
442
|
|
443 ; ld/std require word-aligned displacements -> 'Y' constraint.
|
|
444 ; List Y->r and r->Y before r->r for reload.
|
|
445 (define_insn "*movdd_hardfloat64"
|
|
446 [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
|
|
447 (match_operand:DD 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
|
|
448 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
449 && (gpc_reg_operand (operands[0], DDmode)
|
|
450 || gpc_reg_operand (operands[1], DDmode))"
|
|
451 "@
|
|
452 std%U0%X0 %1,%0
|
|
453 ld%U1%X1 %0,%1
|
|
454 mr %0,%1
|
|
455 fmr %0,%1
|
|
456 lfd%U1%X1 %0,%1
|
|
457 stfd%U0%X0 %1,%0
|
|
458 mt%0 %1
|
|
459 mf%1 %0
|
|
460 {cror 0,0,0|nop}
|
|
461 #
|
|
462 #
|
|
463 #"
|
|
464 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
|
|
465 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
|
|
466
|
|
467 (define_insn "*movdd_softfloat64"
|
|
468 [(set (match_operand:DD 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
|
|
469 (match_operand:DD 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
|
|
470 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
|
|
471 && (gpc_reg_operand (operands[0], DDmode)
|
|
472 || gpc_reg_operand (operands[1], DDmode))"
|
|
473 "@
|
|
474 ld%U1%X1 %0,%1
|
|
475 std%U0%X0 %1,%0
|
|
476 mr %0,%1
|
|
477 mt%0 %1
|
|
478 mf%1 %0
|
|
479 #
|
|
480 #
|
|
481 #
|
|
482 {cror 0,0,0|nop}"
|
|
483 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
|
|
484 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
|
|
485
|
|
486 (define_expand "negtd2"
|
|
487 [(set (match_operand:TD 0 "gpc_reg_operand" "")
|
|
488 (neg:TD (match_operand:TD 1 "gpc_reg_operand" "")))]
|
|
489 "TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
490 "")
|
|
491
|
|
492 (define_insn "*negtd2_fpr"
|
|
493 [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
|
|
494 (neg:TD (match_operand:TD 1 "gpc_reg_operand" "f")))]
|
|
495 "TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
496 "fneg %0,%1"
|
|
497 [(set_attr "type" "fp")])
|
|
498
|
|
499 (define_expand "abstd2"
|
|
500 [(set (match_operand:TD 0 "gpc_reg_operand" "")
|
|
501 (abs:TD (match_operand:TD 1 "gpc_reg_operand" "")))]
|
|
502 "TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
503 "")
|
|
504
|
|
505 (define_insn "*abstd2_fpr"
|
|
506 [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
|
|
507 (abs:TD (match_operand:TD 1 "gpc_reg_operand" "f")))]
|
|
508 "TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
509 "fabs %0,%1"
|
|
510 [(set_attr "type" "fp")])
|
|
511
|
|
512 (define_insn "*nabstd2_fpr"
|
|
513 [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
|
|
514 (neg:TD (abs:TD (match_operand:DF 1 "gpc_reg_operand" "f"))))]
|
|
515 "TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
516 "fnabs %0,%1"
|
|
517 [(set_attr "type" "fp")])
|
|
518
|
|
519 (define_expand "movtd"
|
|
520 [(set (match_operand:TD 0 "general_operand" "")
|
|
521 (match_operand:TD 1 "any_operand" ""))]
|
|
522 "TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
523 "{ rs6000_emit_move (operands[0], operands[1], TDmode); DONE; }")
|
|
524
|
|
525 ; It's important to list the o->f and f->o moves before f->f because
|
|
526 ; otherwise reload, given m->f, will try to pick f->f and reload it,
|
|
527 ; which doesn't make progress. Likewise r->Y must be before r->r.
|
|
528 (define_insn_and_split "*movtd_internal"
|
|
529 [(set (match_operand:TD 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
|
|
530 (match_operand:TD 1 "input_operand" "f,o,f,YGHF,r,r"))]
|
|
531 "TARGET_HARD_FLOAT && TARGET_FPRS
|
|
532 && (gpc_reg_operand (operands[0], TDmode)
|
|
533 || gpc_reg_operand (operands[1], TDmode))"
|
|
534 "#"
|
|
535 "&& reload_completed"
|
|
536 [(pc)]
|
|
537 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
|
|
538 [(set_attr "length" "8,8,8,20,20,16")])
|
|
539
|
|
540 ;; Hardware support for decimal floating point operations.
|
|
541
|
|
542 (define_insn "extendddtd2"
|
|
543 [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
|
|
544 (float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "f")))]
|
|
545 "TARGET_DFP"
|
|
546 "dctqpq %0,%1"
|
|
547 [(set_attr "type" "fp")])
|
|
548
|
|
549 ;; The result of drdpq is an even/odd register pair with the converted
|
|
550 ;; value in the even register and zero in the odd register.
|
|
551 ;; FIXME: Avoid the register move by using a reload constraint to ensure
|
|
552 ;; that the result is the first of the pair receiving the result of drdpq.
|
|
553
|
|
554 (define_insn "trunctddd2"
|
|
555 [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
|
|
556 (float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "f")))
|
|
557 (clobber (match_scratch:TD 2 "=f"))]
|
|
558 "TARGET_DFP"
|
|
559 "drdpq %2,%1\;fmr %0,%2"
|
|
560 [(set_attr "type" "fp")])
|
|
561
|
|
562 (define_insn "adddd3"
|
|
563 [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
|
|
564 (plus:DD (match_operand:DD 1 "gpc_reg_operand" "%f")
|
|
565 (match_operand:DD 2 "gpc_reg_operand" "f")))]
|
|
566 "TARGET_DFP"
|
|
567 "dadd %0,%1,%2"
|
|
568 [(set_attr "type" "fp")])
|
|
569
|
|
570 (define_insn "addtd3"
|
|
571 [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
|
|
572 (plus:TD (match_operand:TD 1 "gpc_reg_operand" "%f")
|
|
573 (match_operand:TD 2 "gpc_reg_operand" "f")))]
|
|
574 "TARGET_DFP"
|
|
575 "daddq %0,%1,%2"
|
|
576 [(set_attr "type" "fp")])
|
|
577
|
|
578 (define_insn "subdd3"
|
|
579 [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
|
|
580 (minus:DD (match_operand:DD 1 "gpc_reg_operand" "f")
|
|
581 (match_operand:DD 2 "gpc_reg_operand" "f")))]
|
|
582 "TARGET_DFP"
|
|
583 "dsub %0,%1,%2"
|
|
584 [(set_attr "type" "fp")])
|
|
585
|
|
586 (define_insn "subtd3"
|
|
587 [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
|
|
588 (minus:TD (match_operand:TD 1 "gpc_reg_operand" "f")
|
|
589 (match_operand:TD 2 "gpc_reg_operand" "f")))]
|
|
590 "TARGET_DFP"
|
|
591 "dsubq %0,%1,%2"
|
|
592 [(set_attr "type" "fp")])
|
|
593
|
|
594 (define_insn "muldd3"
|
|
595 [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
|
|
596 (mult:DD (match_operand:DD 1 "gpc_reg_operand" "%f")
|
|
597 (match_operand:DD 2 "gpc_reg_operand" "f")))]
|
|
598 "TARGET_DFP"
|
|
599 "dmul %0,%1,%2"
|
|
600 [(set_attr "type" "fp")])
|
|
601
|
|
602 (define_insn "multd3"
|
|
603 [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
|
|
604 (mult:TD (match_operand:TD 1 "gpc_reg_operand" "%f")
|
|
605 (match_operand:TD 2 "gpc_reg_operand" "f")))]
|
|
606 "TARGET_DFP"
|
|
607 "dmulq %0,%1,%2"
|
|
608 [(set_attr "type" "fp")])
|
|
609
|
|
610 (define_insn "divdd3"
|
|
611 [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
|
|
612 (div:DD (match_operand:DD 1 "gpc_reg_operand" "f")
|
|
613 (match_operand:DD 2 "gpc_reg_operand" "f")))]
|
|
614 "TARGET_DFP"
|
|
615 "ddiv %0,%1,%2"
|
|
616 [(set_attr "type" "fp")])
|
|
617
|
|
618 (define_insn "divtd3"
|
|
619 [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
|
|
620 (div:TD (match_operand:TD 1 "gpc_reg_operand" "f")
|
|
621 (match_operand:TD 2 "gpc_reg_operand" "f")))]
|
|
622 "TARGET_DFP"
|
|
623 "ddivq %0,%1,%2"
|
|
624 [(set_attr "type" "fp")])
|
|
625
|
|
626 (define_insn "*cmpdd_internal1"
|
|
627 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
|
628 (compare:CCFP (match_operand:DD 1 "gpc_reg_operand" "f")
|
|
629 (match_operand:DD 2 "gpc_reg_operand" "f")))]
|
|
630 "TARGET_DFP"
|
|
631 "dcmpu %0,%1,%2"
|
|
632 [(set_attr "type" "fpcompare")])
|
|
633
|
|
634 (define_insn "*cmptd_internal1"
|
|
635 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
|
636 (compare:CCFP (match_operand:TD 1 "gpc_reg_operand" "f")
|
|
637 (match_operand:TD 2 "gpc_reg_operand" "f")))]
|
|
638 "TARGET_DFP"
|
|
639 "dcmpuq %0,%1,%2"
|
|
640 [(set_attr "type" "fpcompare")])
|
|
641
|
|
642 (define_insn "floatditd2"
|
|
643 [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
|
|
644 (float:TD (match_operand:DI 1 "gpc_reg_operand" "f")))]
|
|
645 "TARGET_DFP"
|
|
646 "dcffixq %0,%1"
|
|
647 [(set_attr "type" "fp")])
|
|
648
|
|
649 ;; Convert a decimal64 to a decimal64 whose value is an integer.
|
|
650 ;; This is the first stage of converting it to an integer type.
|
|
651
|
|
652 (define_insn "ftruncdd2"
|
|
653 [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
|
|
654 (fix:DD (match_operand:DD 1 "gpc_reg_operand" "f")))]
|
|
655 "TARGET_DFP"
|
|
656 "drintn. 0,%0,%1,1"
|
|
657 [(set_attr "type" "fp")])
|
|
658
|
|
659 ;; Convert a decimal64 whose value is an integer to an actual integer.
|
|
660 ;; This is the second stage of converting decimal float to integer type.
|
|
661
|
|
662 (define_insn "fixdddi2"
|
|
663 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
|
|
664 (fix:DI (match_operand:DD 1 "gpc_reg_operand" "f")))]
|
|
665 "TARGET_DFP"
|
|
666 "dctfix %0,%1"
|
|
667 [(set_attr "type" "fp")])
|
|
668
|
|
669 ;; Convert a decimal128 to a decimal128 whose value is an integer.
|
|
670 ;; This is the first stage of converting it to an integer type.
|
|
671
|
|
672 (define_insn "ftrunctd2"
|
|
673 [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
|
|
674 (fix:TD (match_operand:TD 1 "gpc_reg_operand" "f")))]
|
|
675 "TARGET_DFP"
|
|
676 "drintnq. 0,%0,%1,1"
|
|
677 [(set_attr "type" "fp")])
|
|
678
|
|
679 ;; Convert a decimal128 whose value is an integer to an actual integer.
|
|
680 ;; This is the second stage of converting decimal float to integer type.
|
|
681
|
|
682 (define_insn "fixtddi2"
|
|
683 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
|
|
684 (fix:DI (match_operand:TD 1 "gpc_reg_operand" "f")))]
|
|
685 "TARGET_DFP"
|
|
686 "dctfixq %0,%1"
|
|
687 [(set_attr "type" "fp")])
|