Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/bfin/predicates.md @ 55:77e2b8dfacca gcc-4.4.5
update it from 4.4.3 to 4.5.0
author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
---|---|
date | Fri, 12 Feb 2010 23:39:51 +0900 |
parents | a06113de4d67 |
children | 04ced10e8804 |
rev | line source |
---|---|
0 | 1 ;; Predicate definitions for the Blackfin. |
2 ;; Copyright (C) 2005, 2006, 2007, 2008 Free Software Foundation, Inc. | |
3 ;; Contributed by Analog Devices. | |
4 ;; | |
5 ;; This file is part of GCC. | |
6 ;; | |
7 ;; GCC is free software; you can redistribute it and/or modify | |
8 ;; it under the terms of the GNU General Public License as published by | |
9 ;; the Free Software Foundation; either version 3, or (at your option) | |
10 ;; any later version. | |
11 ;; | |
12 ;; GCC is distributed in the hope that it will be useful, | |
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 ;; GNU General Public License for more details. | |
16 ;; | |
17 ;; You should have received a copy of the GNU General Public License | |
18 ;; along with GCC; see the file COPYING3. If not see | |
19 ;; <http://www.gnu.org/licenses/>. | |
20 | |
21 ;; Return nonzero iff OP is one of the integer constants 1 or 2. | |
22 (define_predicate "pos_scale_operand" | |
23 (and (match_code "const_int") | |
24 (match_test "INTVAL (op) == 1 || INTVAL (op) == 2"))) | |
25 | |
26 ;; Return nonzero iff OP is one of the integer constants 2 or 4. | |
27 (define_predicate "scale_by_operand" | |
28 (and (match_code "const_int") | |
29 (match_test "INTVAL (op) == 2 || INTVAL (op) == 4"))) | |
30 | |
31 ;; Return nonzero if OP is a constant that consists of two parts; lower | |
32 ;; bits all zero and upper bits all ones. In this case, we can perform | |
33 ;; an AND operation with a sequence of two shifts. Don't return nonzero | |
34 ;; if the constant would be cheap to load. | |
35 (define_predicate "highbits_operand" | |
36 (and (match_code "const_int") | |
37 (match_test "log2constp (-INTVAL (op)) && !satisfies_constraint_Ks7 (op)"))) | |
38 | |
39 ;; Return nonzero if OP is suitable as a right-hand side operand for an | |
40 ;; andsi3 operation. | |
41 (define_predicate "rhs_andsi3_operand" | |
42 (ior (match_operand 0 "register_operand") | |
43 (and (match_code "const_int") | |
44 (match_test "log2constp (~INTVAL (op)) || INTVAL (op) == 255 || INTVAL (op) == 65535")))) | |
45 | |
46 ;; Return nonzero if OP is a register or a constant with exactly one bit | |
47 ;; set. | |
48 (define_predicate "regorlog2_operand" | |
49 (ior (match_operand 0 "register_operand") | |
50 (and (match_code "const_int") | |
51 (match_test "log2constp (INTVAL (op))")))) | |
52 | |
53 ;; Return nonzero if OP is a register or an integer constant. | |
54 (define_predicate "reg_or_const_int_operand" | |
55 (ior (match_operand 0 "register_operand") | |
56 (match_code "const_int"))) | |
57 | |
58 (define_predicate "const01_operand" | |
59 (and (match_code "const_int") | |
60 (match_test "op == const0_rtx || op == const1_rtx"))) | |
61 | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
62 (define_predicate "const1_operand" |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
63 (and (match_code "const_int") |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
64 (match_test "op == const1_rtx"))) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
65 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
66 (define_predicate "const3_operand" |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
67 (and (match_code "const_int") |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
68 (match_test "INTVAL (op) == 3"))) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
69 |
0 | 70 (define_predicate "vec_shift_operand" |
71 (ior (and (match_code "const_int") | |
72 (match_test "INTVAL (op) >= -16 && INTVAL (op) < 15")) | |
73 (match_operand 0 "register_operand"))) | |
74 | |
75 ;; Like register_operand, but make sure that hard regs have a valid mode. | |
76 (define_predicate "valid_reg_operand" | |
77 (match_operand 0 "register_operand") | |
78 { | |
79 if (GET_CODE (op) == SUBREG) | |
80 op = SUBREG_REG (op); | |
81 if (REGNO (op) < FIRST_PSEUDO_REGISTER) | |
82 return HARD_REGNO_MODE_OK (REGNO (op), mode); | |
83 return 1; | |
84 }) | |
85 | |
86 ;; Return nonzero if OP is a D register. | |
87 (define_predicate "d_register_operand" | |
88 (and (match_code "reg") | |
89 (match_test "D_REGNO_P (REGNO (op))"))) | |
90 | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
91 (define_predicate "p_register_operand" |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
92 (and (match_code "reg") |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
93 (match_test "P_REGNO_P (REGNO (op))"))) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
94 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
95 (define_predicate "dp_register_operand" |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
96 (and (match_code "reg") |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
97 (match_test "D_REGNO_P (REGNO (op)) || P_REGNO_P (REGNO (op))"))) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
98 |
0 | 99 ;; Return nonzero if OP is a LC register. |
100 (define_predicate "lc_register_operand" | |
101 (and (match_code "reg") | |
102 (match_test "REGNO (op) == REG_LC0 || REGNO (op) == REG_LC1"))) | |
103 | |
104 ;; Return nonzero if OP is a LT register. | |
105 (define_predicate "lt_register_operand" | |
106 (and (match_code "reg") | |
107 (match_test "REGNO (op) == REG_LT0 || REGNO (op) == REG_LT1"))) | |
108 | |
109 ;; Return nonzero if OP is a LB register. | |
110 (define_predicate "lb_register_operand" | |
111 (and (match_code "reg") | |
112 (match_test "REGNO (op) == REG_LB0 || REGNO (op) == REG_LB1"))) | |
113 | |
114 ;; Return nonzero if OP is a register or a 7-bit signed constant. | |
115 (define_predicate "reg_or_7bit_operand" | |
116 (ior (match_operand 0 "register_operand") | |
117 (and (match_code "const_int") | |
118 (match_test "satisfies_constraint_Ks7 (op)")))) | |
119 | |
120 ;; Return nonzero if OP is a register other than DREG and PREG. | |
121 (define_predicate "nondp_register_operand" | |
122 (match_operand 0 "register_operand") | |
123 { | |
124 unsigned int regno; | |
125 if (GET_CODE (op) == SUBREG) | |
126 op = SUBREG_REG (op); | |
127 | |
128 regno = REGNO (op); | |
129 return (regno >= FIRST_PSEUDO_REGISTER || !DP_REGNO_P (regno)); | |
130 }) | |
131 | |
132 ;; Return nonzero if OP is a register other than DREG and PREG, or MEM. | |
133 (define_predicate "nondp_reg_or_memory_operand" | |
134 (ior (match_operand 0 "nondp_register_operand") | |
135 (match_operand 0 "memory_operand"))) | |
136 | |
137 ;; Return nonzero if OP is a register or, when negated, a 7-bit signed | |
138 ;; constant. | |
139 (define_predicate "reg_or_neg7bit_operand" | |
140 (ior (match_operand 0 "register_operand") | |
141 (and (match_code "const_int") | |
142 (match_test "satisfies_constraint_KN7 (op)")))) | |
143 | |
144 ;; Used for secondary reloads, this function returns 1 if OP is of the | |
145 ;; form (plus (fp) (const_int)). | |
146 (define_predicate "fp_plus_const_operand" | |
147 (match_code "plus") | |
148 { | |
149 rtx op1, op2; | |
150 | |
151 op1 = XEXP (op, 0); | |
152 op2 = XEXP (op, 1); | |
153 return (REG_P (op1) | |
154 && (REGNO (op1) == FRAME_POINTER_REGNUM | |
155 || REGNO (op1) == STACK_POINTER_REGNUM) | |
156 && GET_CODE (op2) == CONST_INT); | |
157 }) | |
158 | |
159 ;; Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref, | |
160 ;; possibly with an offset. | |
161 (define_predicate "symbolic_operand" | |
162 (ior (match_code "symbol_ref,label_ref") | |
163 (and (match_code "const") | |
164 (match_test "GET_CODE (XEXP (op,0)) == PLUS | |
165 && (GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF | |
166 || GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF) | |
167 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT")))) | |
168 | |
169 ;; Returns 1 if OP is a plain constant or matched by symbolic_operand. | |
170 (define_predicate "symbolic_or_const_operand" | |
171 (ior (match_code "const_int,const_double") | |
172 (match_operand 0 "symbolic_operand"))) | |
173 | |
174 ;; Returns 1 if OP is a SYMBOL_REF. | |
175 (define_predicate "symbol_ref_operand" | |
176 (match_code "symbol_ref")) | |
177 | |
178 ;; True for any non-virtual or eliminable register. Used in places where | |
179 ;; instantiation of such a register may cause the pattern to not be recognized. | |
180 (define_predicate "register_no_elim_operand" | |
181 (match_operand 0 "register_operand") | |
182 { | |
183 if (GET_CODE (op) == SUBREG) | |
184 op = SUBREG_REG (op); | |
185 return !(op == arg_pointer_rtx | |
186 || op == frame_pointer_rtx | |
187 || (REGNO (op) >= FIRST_PSEUDO_REGISTER | |
188 && REGNO (op) <= LAST_VIRTUAL_REGISTER)); | |
189 }) | |
190 | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
191 ;; Test for an operator valid in a BImode conditional branch |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
192 (define_predicate "bfin_bimode_comparison_operator" |
0 | 193 (match_code "eq,ne")) |
194 | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
195 ;; Test for an operator whose result is accessible with movbisi. |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
196 (define_predicate "bfin_direct_comparison_operator" |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
197 (match_code "eq,lt,le,leu,ltu")) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
198 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
199 ;; The following three are used to compute the addrtype attribute. They return |
0 | 200 ;; true if passed a memory address usable for a 16-bit load or store using a |
201 ;; P or I register, respectively. If neither matches, we know we have a | |
202 ;; 32-bit instruction. | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
203 ;; We subdivide the P case into normal P registers, and SP/FP. We can assume |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
204 ;; that speculative loads through SP and FP are no problem, so this has |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
205 ;; an effect on the anomaly workaround code. |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
206 |
0 | 207 (define_predicate "mem_p_address_operand" |
208 (match_code "mem") | |
209 { | |
210 if (effective_address_32bit_p (op, mode)) | |
211 return 0; | |
212 op = XEXP (op, 0); | |
213 if (GET_CODE (op) == PLUS || GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC) | |
214 op = XEXP (op, 0); | |
215 gcc_assert (REG_P (op)); | |
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
216 return PREG_P (op) && op != stack_pointer_rtx && op != frame_pointer_rtx; |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
217 }) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
218 |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
219 (define_predicate "mem_spfp_address_operand" |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
220 (match_code "mem") |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
221 { |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
222 if (effective_address_32bit_p (op, mode)) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
223 return 0; |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
224 op = XEXP (op, 0); |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
225 if (GET_CODE (op) == PLUS || GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC) |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
226 op = XEXP (op, 0); |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
227 gcc_assert (REG_P (op)); |
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
228 return op == stack_pointer_rtx || op == frame_pointer_rtx; |
0 | 229 }) |
230 | |
231 (define_predicate "mem_i_address_operand" | |
232 (match_code "mem") | |
233 { | |
234 if (effective_address_32bit_p (op, mode)) | |
235 return 0; | |
236 op = XEXP (op, 0); | |
237 if (GET_CODE (op) == PLUS || GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC) | |
238 op = XEXP (op, 0); | |
239 gcc_assert (REG_P (op)); | |
240 return IREG_P (op); | |
241 }) |