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1 ;; AMD K6/K6-2 Scheduling
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2 ;; Copyright (C) 2002, 2004, 2007
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3 ;; Free Software Foundation, Inc.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify
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8 ;; it under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful,
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13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 ;; GNU General Public License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20 ;;
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21 ;; The K6 architecture is quite similar to PPro. Important difference is
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22 ;; that there are only two decoders and they seems to be much slower than
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23 ;; any of the execution units. So we have to pay much more attention to
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24 ;; proper scheduling for the decoders.
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25 ;; FIXME: We don't do that right now. A good start would be to sort the
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26 ;; instructions based on length.
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27 ;;
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28 ;; This description is based on data from the following documents:
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29 ;;
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30 ;; "AMD-K6 Processor Data Sheet (Preliminary information)"
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31 ;; Advanced Micro Devices, Inc., 1998.
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32 ;;
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33 ;; "AMD-K6 Processor Code Optimization Application Note"
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34 ;; Advanced Micro Devices, Inc., 2000.
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35 ;;
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36 ;; CPU execution units of the K6:
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37 ;;
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38 ;; store describes the Store unit. This unit is not modelled
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39 ;; completely and it is only used to model lea operation.
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40 ;; Otherwise it lies outside of any critical path.
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41 ;; load describes the Load unit
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42 ;; alux describes the Integer X unit
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43 ;; mm describes the Multimedia unit, which shares a pipe
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44 ;; with the Integer X unit. This unit is used for MMX,
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45 ;; which is not implemented for K6.
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46 ;; aluy describes the Integer Y unit
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47 ;; fpu describes the FPU unit
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48 ;; branch describes the Branch unit
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49 ;;
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50 ;; The fp unit is not pipelined, and it can only do one operation per two
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51 ;; cycles, including fxcg.
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52 ;;
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53 ;; Generally this is a very poor description, but at least no worse than
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54 ;; the old description, and a lot easier to extend to something more
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55 ;; reasonable if anyone still cares enough about this architecture in 2004.
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56 ;;
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57 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
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58
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59 (define_automaton "k6_decoder,k6_load_unit,k6_store_unit,k6_integer_units,k6_fpu_unit,k6_branch_unit")
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60
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61 ;; The K6 instruction decoding begins before the on-chip instruction cache is
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62 ;; filled. Depending on the length of the instruction, two simple instructions
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63 ;; can be decoded in two parallel short decoders, or one complex instruction can
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64 ;; be decoded in either the long or the vector decoder. For all practical
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65 ;; purposes, the long and vector decoder can be modelled as one decoder.
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66 (define_cpu_unit "k6_decode_short0" "k6_decoder")
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67 (define_cpu_unit "k6_decode_short1" "k6_decoder")
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68 (define_cpu_unit "k6_decode_long" "k6_decoder")
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69 (exclusion_set "k6_decode_long" "k6_decode_short0,k6_decode_short1")
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70 (define_reservation "k6_decode_short" "k6_decode_short0|k6_decode_short1")
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71 (define_reservation "k6_decode_vector" "k6_decode_long")
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72
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73 (define_cpu_unit "k6_store" "k6_store_unit")
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74 (define_cpu_unit "k6_load" "k6_load_unit")
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75 (define_cpu_unit "k6_alux,k6_aluy" "k6_integer_units")
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76 (define_cpu_unit "k6_fpu" "k6_fpu_unit")
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77 (define_cpu_unit "k6_branch" "k6_branch_unit")
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78
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79 ;; Shift instructions and certain arithmetic are issued only on Integer X.
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80 (define_insn_reservation "k6_alux_only" 1
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81 (and (eq_attr "cpu" "k6")
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82 (and (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot")
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83 (eq_attr "memory" "none")))
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84 "k6_decode_short,k6_alux")
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85
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86 (define_insn_reservation "k6_alux_only_load" 3
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87 (and (eq_attr "cpu" "k6")
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88 (and (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot")
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89 (eq_attr "memory" "load")))
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90 "k6_decode_short,k6_load,k6_alux")
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91
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92 (define_insn_reservation "k6_alux_only_store" 3
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93 (and (eq_attr "cpu" "k6")
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94 (and (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot")
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95 (eq_attr "memory" "store,both,unknown")))
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96 "k6_decode_long,k6_load,k6_alux,k6_store")
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97
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98 ;; Integer divide and multiply can only be issued on Integer X, too.
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99 (define_insn_reservation "k6_alu_imul" 2
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100 (and (eq_attr "cpu" "k6")
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101 (eq_attr "type" "imul"))
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102 "k6_decode_vector,k6_alux*3")
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103
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104 (define_insn_reservation "k6_alu_imul_load" 4
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105 (and (eq_attr "cpu" "k6")
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106 (and (eq_attr "type" "imul")
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107 (eq_attr "memory" "load")))
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108 "k6_decode_vector,k6_load,k6_alux*3")
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109
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110 (define_insn_reservation "k6_alu_imul_store" 4
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111 (and (eq_attr "cpu" "k6")
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112 (and (eq_attr "type" "imul")
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113 (eq_attr "memory" "store,both,unknown")))
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114 "k6_decode_vector,k6_load,k6_alux*3,k6_store")
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115
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116 ;; ??? Guessed latencies based on the old pipeline description.
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117 (define_insn_reservation "k6_alu_idiv" 17
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118 (and (eq_attr "cpu" "k6")
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119 (and (eq_attr "type" "idiv")
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120 (eq_attr "memory" "none")))
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121 "k6_decode_vector,k6_alux*17")
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122
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123 (define_insn_reservation "k6_alu_idiv_mem" 19
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124 (and (eq_attr "cpu" "k6")
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125 (and (eq_attr "type" "idiv")
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126 (eq_attr "memory" "!none")))
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127 "k6_decode_vector,k6_load,k6_alux*17")
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128
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129 ;; Basic word and doubleword ALU ops can be issued on both Integer units.
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130 (define_insn_reservation "k6_alu" 1
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131 (and (eq_attr "cpu" "k6")
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132 (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec,setcc")
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133 (eq_attr "memory" "none")))
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134 "k6_decode_short,k6_alux|k6_aluy")
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135
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136 (define_insn_reservation "k6_alu_load" 3
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137 (and (eq_attr "cpu" "k6")
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138 (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec,setcc")
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139 (eq_attr "memory" "load")))
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140 "k6_decode_short,k6_load,k6_alux|k6_aluy")
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141
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142 (define_insn_reservation "k6_alu_store" 3
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143 (and (eq_attr "cpu" "k6")
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144 (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec,setcc")
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145 (eq_attr "memory" "store,both,unknown")))
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146 "k6_decode_long,k6_load,k6_alux|k6_aluy,k6_store")
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147
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148 ;; A "load immediate" operation does not require execution at all,
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149 ;; it is available immediately after decoding. Special-case this.
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150 (define_insn_reservation "k6_alu_imov" 1
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151 (and (eq_attr "cpu" "k6")
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152 (and (eq_attr "type" "imov")
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153 (and (eq_attr "memory" "none")
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154 (match_operand 1 "nonimmediate_operand"))))
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155 "k6_decode_short,k6_alux|k6_aluy")
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156
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157 (define_insn_reservation "k6_alu_imov_imm" 0
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158 (and (eq_attr "cpu" "k6")
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159 (and (eq_attr "type" "imov")
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160 (and (eq_attr "memory" "none")
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161 (match_operand 1 "immediate_operand"))))
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162 "k6_decode_short")
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163
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164 (define_insn_reservation "k6_alu_imov_load" 2
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165 (and (eq_attr "cpu" "k6")
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166 (and (eq_attr "type" "imov")
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167 (eq_attr "memory" "load")))
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168 "k6_decode_short,k6_load")
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169
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170 (define_insn_reservation "k6_alu_imov_store" 1
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171 (and (eq_attr "cpu" "k6")
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172 (and (eq_attr "type" "imov")
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173 (eq_attr "memory" "store")))
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174 "k6_decode_short,k6_store")
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175
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176 (define_insn_reservation "k6_alu_imov_both" 2
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177 (and (eq_attr "cpu" "k6")
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178 (and (eq_attr "type" "imov")
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179 (eq_attr "memory" "both,unknown")))
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180 "k6_decode_long,k6_load,k6_alux|k6_aluy")
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181
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182 ;; The branch unit.
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183 (define_insn_reservation "k6_branch_call" 1
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184 (and (eq_attr "cpu" "k6")
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185 (eq_attr "type" "call,callv"))
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186 "k6_decode_vector,k6_branch")
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187
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188 (define_insn_reservation "k6_branch_branch" 1
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189 (and (eq_attr "cpu" "k6")
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190 (eq_attr "type" "ibr"))
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191 "k6_decode_short,k6_branch")
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192
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193 ;; The load and units have two pipeline stages. The load latency is
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194 ;; two cycles.
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195 (define_insn_reservation "k6_load_pop" 3
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196 (and (eq_attr "cpu" "k6")
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197 (ior (eq_attr "type" "pop")
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198 (eq_attr "memory" "load,both")))
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199 "k6_decode_short,k6_load")
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200
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201 (define_insn_reservation "k6_load_leave" 5
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202 (and (eq_attr "cpu" "k6")
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203 (eq_attr "type" "leave"))
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204 "k6_decode_long,k6_load,(k6_alux|k6_aluy)*2")
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205
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206 ;; ??? From the old pipeline description. Egad!
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207 ;; ??? Apparently we take care of this reservation in adjust_cost.
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208 (define_insn_reservation "k6_load_str" 10
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209 (and (eq_attr "cpu" "k6")
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210 (and (eq_attr "type" "str")
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211 (eq_attr "memory" "load,both")))
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212 "k6_decode_vector,k6_load*10")
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213
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214 ;; The store unit handles lea and push. It is otherwise unmodelled.
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215 (define_insn_reservation "k6_store_lea" 2
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216 (and (eq_attr "cpu" "k6")
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217 (eq_attr "type" "lea"))
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218 "k6_decode_short,k6_store,k6_alux|k6_aluy")
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219
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220 (define_insn_reservation "k6_store_push" 2
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221 (and (eq_attr "cpu" "k6")
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222 (ior (eq_attr "type" "push")
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223 (eq_attr "memory" "store,both")))
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224 "k6_decode_short,k6_store")
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225
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226 (define_insn_reservation "k6_store_str" 10
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227 (and (eq_attr "cpu" "k6")
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228 (eq_attr "type" "str"))
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229 "k6_store*10")
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230
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231 ;; Most FPU instructions have latency 2 and throughput 2.
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232 (define_insn_reservation "k6_fpu" 2
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233 (and (eq_attr "cpu" "k6")
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234 (and (eq_attr "type" "fop,fmov,fcmp,fistp")
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235 (eq_attr "memory" "none")))
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236 "k6_decode_vector,k6_fpu*2")
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237
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238 (define_insn_reservation "k6_fpu_load" 6
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239 (and (eq_attr "cpu" "k6")
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240 (and (eq_attr "type" "fop,fmov,fcmp,fistp")
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241 (eq_attr "memory" "load,both")))
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242 "k6_decode_short,k6_load,k6_fpu*2")
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243
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244 (define_insn_reservation "k6_fpu_store" 6
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245 (and (eq_attr "cpu" "k6")
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246 (and (eq_attr "type" "fop,fmov,fcmp,fistp")
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247 (eq_attr "memory" "store")))
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248 "k6_decode_short,k6_store,k6_fpu*2")
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249
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250 (define_insn_reservation "k6_fpu_fmul" 2
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251 (and (eq_attr "cpu" "k6")
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252 (and (eq_attr "type" "fmul")
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253 (eq_attr "memory" "none")))
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254 "k6_decode_short,k6_fpu*2")
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255
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256 (define_insn_reservation "k6_fpu_fmul_load" 2
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257 (and (eq_attr "cpu" "k6")
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258 (and (eq_attr "type" "fmul")
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259 (eq_attr "memory" "load,both")))
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260 "k6_decode_short,k6_load,k6_fpu*2")
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261
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262 ;; ??? Guessed latencies from the old pipeline description.
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263 (define_insn_reservation "k6_fpu_expensive" 56
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264 (and (eq_attr "cpu" "k6")
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265 (eq_attr "type" "fdiv,fpspc"))
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266 "k6_decode_short,k6_fpu*56")
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267
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