Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/ia64/ia64.opt @ 55:77e2b8dfacca gcc-4.4.5
update it from 4.4.3 to 4.5.0
author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
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date | Fri, 12 Feb 2010 23:39:51 +0900 |
parents | a06113de4d67 |
children | f6334be47118 |
rev | line source |
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77e2b8dfacca
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1 ; Copyright (C) 2005, 2006, 2008 Free Software Foundation, Inc. |
77e2b8dfacca
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2 ; |
77e2b8dfacca
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3 ; This file is part of GCC. |
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4 ; |
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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5 ; GCC is free software; you can redistribute it and/or modify it under |
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6 ; the terms of the GNU General Public License as published by the Free |
77e2b8dfacca
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7 ; Software Foundation; either version 3, or (at your option) any later |
77e2b8dfacca
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8 ; version. |
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9 ; |
77e2b8dfacca
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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10 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
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11 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or |
77e2b8dfacca
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12 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
77e2b8dfacca
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13 ; for more details. |
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14 ; |
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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15 ; You should have received a copy of the GNU General Public License |
77e2b8dfacca
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16 ; along with GCC; see the file COPYING3. If not see |
77e2b8dfacca
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17 ; <http://www.gnu.org/licenses/>. |
77e2b8dfacca
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18 |
0 | 19 mbig-endian |
20 Target Report RejectNegative Mask(BIG_ENDIAN) | |
21 Generate big endian code | |
22 | |
23 mlittle-endian | |
24 Target Report RejectNegative InverseMask(BIG_ENDIAN) | |
25 Generate little endian code | |
26 | |
27 mgnu-as | |
28 Target Report Mask(GNU_AS) | |
29 Generate code for GNU as | |
30 | |
31 mgnu-ld | |
32 Target Report Mask(GNU_LD) | |
33 Generate code for GNU ld | |
34 | |
35 mvolatile-asm-stop | |
36 Target Report Mask(VOL_ASM_STOP) | |
37 Emit stop bits before and after volatile extended asms | |
38 | |
39 mregister-names | |
40 Target Mask(REG_NAMES) | |
41 Use in/loc/out register names | |
42 | |
43 mno-sdata | |
44 Target Report RejectNegative Mask(NO_SDATA) | |
45 | |
46 msdata | |
47 Target Report RejectNegative InverseMask(NO_SDATA) | |
48 Enable use of sdata/scommon/sbss | |
49 | |
50 mno-pic | |
51 Target Report RejectNegative Mask(NO_PIC) | |
52 Generate code without GP reg | |
53 | |
54 mconstant-gp | |
55 Target Report RejectNegative Mask(CONST_GP) | |
56 gp is constant (but save/restore gp on indirect calls) | |
57 | |
58 mauto-pic | |
59 Target Report RejectNegative Mask(AUTO_PIC) | |
60 Generate self-relocatable code | |
61 | |
62 minline-float-divide-min-latency | |
63 Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 1) | |
64 Generate inline floating point division, optimize for latency | |
65 | |
66 minline-float-divide-max-throughput | |
67 Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 2) Init(2) | |
68 Generate inline floating point division, optimize for throughput | |
69 | |
70 mno-inline-float-divide | |
71 Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 0) | |
72 | |
73 minline-int-divide-min-latency | |
74 Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 1) | |
75 Generate inline integer division, optimize for latency | |
76 | |
77 minline-int-divide-max-throughput | |
78 Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 2) | |
79 Generate inline integer division, optimize for throughput | |
80 | |
81 mno-inline-int-divide | |
82 Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 0) | |
83 Do not inline integer division | |
84 | |
85 minline-sqrt-min-latency | |
86 Target Report RejectNegative Var(TARGET_INLINE_SQRT, 1) | |
87 Generate inline square root, optimize for latency | |
88 | |
89 minline-sqrt-max-throughput | |
90 Target Report RejectNegative Var(TARGET_INLINE_SQRT, 2) | |
91 Generate inline square root, optimize for throughput | |
92 | |
93 mno-inline-sqrt | |
94 Target Report RejectNegative Var(TARGET_INLINE_SQRT, 0) | |
95 Do not inline square root | |
96 | |
97 mdwarf2-asm | |
98 Target Report Mask(DWARF2_ASM) | |
99 Enable Dwarf 2 line debug info via GNU as | |
100 | |
101 mearly-stop-bits | |
102 Target Report Mask(EARLY_STOP_BITS) | |
103 Enable earlier placing stop bits for better scheduling | |
104 | |
105 mfixed-range= | |
106 Target RejectNegative Joined | |
107 Specify range of registers to make fixed | |
108 | |
109 mtls-size= | |
110 Target RejectNegative Joined UInteger Var(ia64_tls_size) Init(22) | |
111 Specify bit size of immediate TLS offsets | |
112 | |
113 mtune= | |
114 Target RejectNegative Joined | |
115 Schedule code for given CPU | |
116 | |
117 msched-br-data-spec | |
118 Target Report Var(mflag_sched_br_data_spec) Init(0) | |
119 Use data speculation before reload | |
120 | |
121 msched-ar-data-spec | |
122 Target Report Var(mflag_sched_ar_data_spec) Init(1) | |
123 Use data speculation after reload | |
124 | |
125 msched-control-spec | |
126 Target Report Var(mflag_sched_control_spec) Init(2) | |
127 Use control speculation | |
128 | |
129 msched-br-in-data-spec | |
130 Target Report Var(mflag_sched_br_in_data_spec) Init(1) | |
131 Use in block data speculation before reload | |
132 | |
133 msched-ar-in-data-spec | |
134 Target Report Var(mflag_sched_ar_in_data_spec) Init(1) | |
135 Use in block data speculation after reload | |
136 | |
137 msched-in-control-spec | |
138 Target Report Var(mflag_sched_in_control_spec) Init(1) | |
139 Use in block control speculation | |
140 | |
141 msched-spec-ldc | |
142 Target Report Var(mflag_sched_spec_ldc) Init(1) | |
143 Use simple data speculation check | |
144 | |
145 msched-spec-control-ldc | |
146 Target Report Var(mflag_sched_spec_control_ldc) Init(0) | |
147 Use simple data speculation check for control speculation | |
148 | |
149 msched-prefer-non-data-spec-insns | |
150 Target Report Var(mflag_sched_prefer_non_data_spec_insns) Init(0) | |
151 If set, data speculative instructions will be chosen for schedule only if there are no other choices at the moment | |
152 | |
153 msched-prefer-non-control-spec-insns | |
154 Target Report Var(mflag_sched_prefer_non_control_spec_insns) Init(0) | |
155 If set, control speculative instructions will be chosen for schedule only if there are no other choices at the moment | |
156 | |
157 msched-count-spec-in-critical-path | |
158 Target Report Var(mflag_sched_count_spec_in_critical_path) Init(0) | |
159 Count speculative dependencies while calculating priority of instructions | |
160 | |
161 msched-stop-bits-after-every-cycle | |
162 Target Report Var(mflag_sched_stop_bits_after_every_cycle) Init(1) | |
163 Place a stop bit after every cycle when scheduling | |
164 | |
165 msched-fp-mem-deps-zero-cost | |
166 Target Report Var(mflag_sched_fp_mem_deps_zero_cost) Init(0) | |
167 Assume that floating-point stores and loads are not likely to cause conflict when placed into one instruction group | |
168 | |
169 msched-max-memory-insns= | |
170 Target RejectNegative Joined UInteger Var(ia64_max_memory_insns) Init(1) | |
171 Soft limit on number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same insn group. Frequently useful to prevent cache bank conflicts. Default value is 1 | |
172 | |
173 msched-max-memory-insns-hard-limit | |
174 Target Report Var(mflag_sched_mem_insns_hard_limit) Init(0) | |
175 Disallow more than `msched-max-memory-insns' in instruction group. Otherwise, limit is `soft' (prefer non-memory operations when limit is reached) | |
176 | |
177 msel-sched-dont-check-control-spec | |
178 Target Report Var(mflag_sel_sched_dont_check_control_spec) Init(0) | |
179 Don't generate checks for control speculation in selective scheduling | |
180 | |
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77e2b8dfacca
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
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181 mfused-madd |
77e2b8dfacca
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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182 Target Report Mask(FUSED_MADD) |
77e2b8dfacca
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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183 Enable fused multiply/add and multiply/subtract instructions |
77e2b8dfacca
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184 |
0 | 185 ; This comment is to ensure we retain the blank line above. |