Mercurial > hg > CbC > CbC_gcc

annotate gcc/config/mips/5400.md @ 55:77e2b8dfacca gcc-4.4.5

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children 04ced10e8804
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55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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1 ;; Copyright (C) 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
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2 ;;
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3 ;; This file is part of GCC.
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4 ;;
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5 ;; GCC is free software; you can redistribute it and/or modify
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6 ;; it under the terms of the GNU General Public License as published by
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parents: 0
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7 ;; the Free Software Foundation; either version 3, or (at your option)
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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8 ;; any later version.
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9 ;;
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10 ;; GCC is distributed in the hope that it will be useful,
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11 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 ;; GNU General Public License for more details.
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14 ;;
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15 ;; You should have received a copy of the GNU General Public License
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16 ;; along with GCC; see the file COPYING3. If not see
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17 ;; <http://www.gnu.org/licenses/>.
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18 ;;
0
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19 ;; DFA-based pipeline description for 5400
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20 (define_automaton "vr54")
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21 (define_cpu_unit "vr54_dp0" "vr54")
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22 (define_cpu_unit "vr54_dp1" "vr54")
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23 (define_cpu_unit "vr54_mem" "vr54")
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24 (define_cpu_unit "vr54_mac" "vr54")
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25
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26 ;;
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27 ;; The ordering of the instruction-execution-path/resource-usage
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28 ;; descriptions (also known as reservation RTL) is roughly ordered
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29 ;; based on the define attribute RTL for the "type" classification.
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30 ;; When modifying, remember that the first test that matches is the
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31 ;; reservation used!
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32 ;;
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33
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34 (define_insn_reservation "ir_vr54_unknown" 1
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35 (and (eq_attr "cpu" "r5400")
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36 (eq_attr "type" "unknown"))
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37 "vr54_dp0+vr54_dp1+vr54_mem+vr54_mac")
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38
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39 ;; Assume prediction fails.
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40 (define_insn_reservation "ir_vr54_branch" 3
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41 (and (eq_attr "cpu" "r5400")
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42 (eq_attr "type" "branch,jump,call"))
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43 "vr54_dp0|vr54_dp1")
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44
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45 (define_insn_reservation "ir_vr54_load" 2
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46 (and (eq_attr "cpu" "r5400")
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47 (eq_attr "type" "load,fpload,fpidxload"))
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48 "vr54_mem")
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49
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50 (define_insn_reservation "ir_vr54_store" 1
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51 (and (eq_attr "cpu" "r5400")
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52 (eq_attr "type" "store"))
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53 "vr54_mem")
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54
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55 (define_insn_reservation "ir_vr54_fstore" 1
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56 (and (eq_attr "cpu" "r5400")
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57 (eq_attr "type" "fpstore,fpidxstore"))
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58 "vr54_mem")
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59
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60
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61 ;; This reservation is for conditional move based on integer
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62 ;; or floating point CC.
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63 (define_insn_reservation "ir_vr54_condmove" 4
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64 (and (eq_attr "cpu" "r5400")
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65 (eq_attr "type" "condmove"))
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66 "vr54_dp0|vr54_dp1")
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67
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68 ;; Move to/from FPU registers
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69 (define_insn_reservation "ir_vr54_xfer" 2
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70 (and (eq_attr "cpu" "r5400")
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71 (eq_attr "type" "mfc,mtc"))
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72 "vr54_dp0|vr54_dp1")
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73
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74 (define_insn_reservation "ir_vr54_hilo" 1
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75 (and (eq_attr "cpu" "r5400")
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76 (eq_attr "type" "mthilo,mfhilo"))
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77 "vr54_dp0|vr54_dp1")
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78
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79 (define_insn_reservation "ir_vr54_arith" 1
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80 (and (eq_attr "cpu" "r5400")
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81 (eq_attr "type" "arith,shift,signext,slt,clz,const,logical,move,nop,trap"))
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82 "vr54_dp0|vr54_dp1")
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83
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84 (define_insn_reservation "ir_vr54_imul_si" 3
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85 (and (eq_attr "cpu" "r5400")
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86 (and (eq_attr "type" "imul,imul3")
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87 (eq_attr "mode" "SI")))
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88 "vr54_dp0|vr54_dp1")
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89
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90 (define_insn_reservation "ir_vr54_imul_di" 4
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91 (and (eq_attr "cpu" "r5400")
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92 (and (eq_attr "type" "imul,imul3")
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93 (eq_attr "mode" "DI")))
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94 "vr54_dp0|vr54_dp1")
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95
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96 (define_insn_reservation "ir_vr54_imadd_si" 3
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97 (and (eq_attr "cpu" "r5400")
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98 (eq_attr "type" "imul,imul3"))
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99 "vr54_mac")
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100
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101 (define_insn_reservation "ir_vr54_idiv_si" 42
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102 (and (eq_attr "cpu" "r5400")
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103 (and (eq_attr "type" "idiv")
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104 (eq_attr "mode" "SI")))
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105 "vr54_dp0|vr54_dp1")
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106
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107 (define_insn_reservation "ir_vr54_idiv_di" 74
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108 (and (eq_attr "cpu" "r5400")
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109 (and (eq_attr "type" "idiv")
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110 (eq_attr "mode" "DI")))
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111 "vr54_dp0|vr54_dp1")
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112
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113 (define_insn_reservation "ir_vr54_fadd" 4
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114 (and (eq_attr "cpu" "r5400")
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115 (eq_attr "type" "fadd"))
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116 "vr54_dp0|vr54_dp1")
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117
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118 (define_insn_reservation "ir_vr54_fmul_sf" 5
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119 (and (eq_attr "cpu" "r5400")
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120 (and (eq_attr "type" "fmul")
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121 (eq_attr "mode" "SF")))
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122 "vr54_dp0|vr54_dp1")
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123
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124 (define_insn_reservation "ir_vr54_fmul_df" 6
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125 (and (eq_attr "cpu" "r5400")
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126 (and (eq_attr "type" "fmul")
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127 (eq_attr "mode" "DF")))
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128 "vr54_dp0|vr54_dp1")
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129
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130 (define_insn_reservation "ir_vr54_fmadd_sf" 9
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131 (and (eq_attr "cpu" "r5400")
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132 (and (eq_attr "type" "fmadd")
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133 (eq_attr "mode" "SF")))
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134 "vr54_dp0|vr54_dp1")
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135
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136 (define_insn_reservation "ir_vr54_fmadd_df" 10
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137 (and (eq_attr "cpu" "r5400")
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138 (and (eq_attr "type" "fmadd")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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139 (eq_attr "mode" "DF")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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140 "vr54_dp0|vr54_dp1")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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141
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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142 (define_insn_reservation "ir_vr54_fdiv_sf" 42
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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143 (and (eq_attr "cpu" "r5400")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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144 (and (eq_attr "type" "fdiv,frdiv,fsqrt")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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145 (eq_attr "mode" "SF")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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146 "vr54_dp0|vr54_dp1")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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147
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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148 (define_insn_reservation "ir_vr54_fdiv_df" 72
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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149 (and (eq_attr "cpu" "r5400")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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150 (and (eq_attr "type" "fdiv,frdiv,fsqrt")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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151 (eq_attr "mode" "DF")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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152 "vr54_dp0|vr54_dp1")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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153
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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154 (define_insn_reservation "ir_vr54_fabs" 2
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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155 (and (eq_attr "cpu" "r5400")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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156 (eq_attr "type" "fabs,fneg,fmove"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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157 "vr54_dp0|vr54_dp1")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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158
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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159 (define_insn_reservation "ir_vr54_fcmp" 2
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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160 (and (eq_attr "cpu" "r5400")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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161 (eq_attr "type" "fcmp"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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162 "vr54_dp0|vr54_dp1")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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163
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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164 (define_insn_reservation "ir_vr54_fcvt" 6
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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165 (and (eq_attr "cpu" "r5400")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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166 (eq_attr "type" "fcvt"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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167 "vr54_dp0|vr54_dp1")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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168
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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169 (define_insn_reservation "ir_vr54_frsqrt_sf" 61
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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170 (and (eq_attr "cpu" "r5400")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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171 (and (eq_attr "type" "frsqrt")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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172 (eq_attr "mode" "SF")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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173 "vr54_dp0|vr54_dp1")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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174
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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175 (define_insn_reservation "ir_vr54_frsqrt_df" 121
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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176 (and (eq_attr "cpu" "r5400")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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177 (and (eq_attr "type" "frsqrt")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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178 (eq_attr "mode" "DF")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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179 "vr54_dp0|vr54_dp1")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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180
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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181 (define_insn_reservation "ir_vr54_multi" 1
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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182 (and (eq_attr "cpu" "r5400")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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183 (eq_attr "type" "multi"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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184 "vr54_dp0+vr54_dp1+vr54_mem+vr54_mac")