Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/pa/constraints.md @ 55:77e2b8dfacca gcc-4.4.5
update it from 4.4.3 to 4.5.0
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Fri, 12 Feb 2010 23:39:51 +0900 |
| parents | a06113de4d67 |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
| 0 | 1 ;; Constraint definitions for pa |
| 2 ;; Copyright (C) 2007 Free Software Foundation, Inc. | |
| 3 | |
| 4 ;; This file is part of GCC. | |
| 5 | |
| 6 ;; GCC is free software; you can redistribute it and/or modify it | |
| 7 ;; under the terms of the GNU General Public License as published | |
| 8 ;; by the Free Software Foundation; either version 3, or (at your | |
| 9 ;; option) any later version. | |
| 10 | |
| 11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
| 12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 14 ;; License for more details. | |
| 15 | |
| 16 ;; You should have received a copy of the GNU General Public License | |
| 17 ;; along with GCC; see the file COPYING3. If not see | |
| 18 ;; <http://www.gnu.org/licenses/>. | |
| 19 | |
| 20 ;;; Unused letters: | |
| 21 ;;; ABCDEF H V Y | |
| 22 ;;; bcde ghijklmnop stuvw z | |
| 23 | |
| 24 ;; Register constraints. | |
| 25 (define_register_constraint "a" "R1_REGS" | |
| 26 "General register 1.") | |
| 27 | |
| 28 (define_register_constraint "f" "FP_REGS" | |
| 29 "Floating-point register.") | |
| 30 | |
| 31 (define_register_constraint "q" "SHIFT_REGS" | |
| 32 "Shift amount register.") | |
| 33 | |
| 34 ;; Keep 'x' for backward compatibility with user asm. | |
| 35 (define_register_constraint "x" "FP_REGS" | |
| 36 "Floating-point register.") | |
| 37 | |
| 38 (define_register_constraint "y" "TARGET_64BIT ? FP_REGS : FPUPPER_REGS" | |
| 39 "Upper floating-point register.") | |
| 40 | |
| 41 (define_register_constraint "Z" "ALL_REGS" | |
| 42 "Any register.") | |
| 43 | |
| 44 ;; Integer constant constraints. | |
| 45 (define_constraint "I" | |
| 46 "Signed 11-bit integer constant." | |
| 47 (and (match_code "const_int") | |
| 48 (match_test "VAL_11_BITS_P (ival)"))) | |
| 49 | |
| 50 (define_constraint "J" | |
| 51 "Signed 14-bit integer constant." | |
| 52 (and (match_code "const_int") | |
| 53 (match_test "VAL_14_BITS_P (ival)"))) | |
| 54 | |
| 55 (define_constraint "K" | |
| 56 "Integer constant that can be deposited with a zdepi instruction." | |
| 57 (and (match_code "const_int") | |
| 58 (match_test "zdepi_cint_p (ival)"))) | |
| 59 | |
| 60 (define_constraint "L" | |
| 61 "Signed 5-bit integer constant." | |
| 62 (and (match_code "const_int") | |
| 63 (match_test "VAL_5_BITS_P (ival)"))) | |
| 64 | |
| 65 (define_constraint "M" | |
| 66 "Integer constant 0." | |
| 67 (and (match_code "const_int") | |
| 68 (match_test "ival == 0"))) | |
| 69 | |
| 70 (define_constraint "N" | |
| 71 "Integer constant that can be loaded with a ldil instruction." | |
| 72 (and (match_code "const_int") | |
| 73 (match_test "ldil_cint_p (ival)"))) | |
| 74 | |
| 75 (define_constraint "O" | |
| 76 "Integer constant such that ival+1 is a power of 2." | |
| 77 (and (match_code "const_int") | |
| 78 (match_test "(ival & (ival + 1)) == 0"))) | |
| 79 | |
| 80 (define_constraint "P" | |
| 81 "Integer constant that can be used as an and mask in depi and | |
| 82 extru instructions." | |
| 83 (and (match_code "const_int") | |
| 84 (match_test "and_mask_p (ival)"))) | |
| 85 | |
| 86 (define_constraint "S" | |
| 87 "Integer constant 31." | |
| 88 (and (match_code "const_int") | |
| 89 (match_test "ival == 31"))) | |
| 90 | |
| 91 (define_constraint "U" | |
| 92 "Integer constant 63." | |
| 93 (and (match_code "const_int") | |
| 94 (match_test "ival == 63"))) | |
| 95 | |
| 96 ;; Floating-point constant constraints. | |
| 97 (define_constraint "G" | |
| 98 "Floating-point constant 0." | |
| 99 (and (match_code "const_double") | |
| 100 (match_test "GET_MODE_CLASS (mode) == MODE_FLOAT | |
| 101 && op == CONST0_RTX (mode)"))) | |
| 102 | |
| 103 ;; Extra constraints. | |
| 104 (define_constraint "A" | |
| 105 "A LO_SUM DLT memory operand." | |
| 106 (and (match_code "mem") | |
| 107 (match_test "IS_LO_SUM_DLT_ADDR_P (XEXP (op, 0))"))) | |
| 108 | |
| 109 (define_constraint "Q" | |
| 110 "A memory operand that can be used as the destination operand of an | |
| 111 integer store, or the source operand of an integer load. That is | |
| 112 any memory operand that isn't a symbolic, indexed or lo_sum memory | |
| 113 operand. Note that an unassigned pseudo register is such a memory | |
| 114 operand. We accept unassigned pseudo registers because reload | |
| 115 generates them and then doesn't re-recognize the insn, causing | |
| 116 constrain_operands to fail." | |
| 117 (match_test "integer_store_memory_operand (op, mode)")) | |
| 118 | |
| 119 (define_constraint "R" | |
| 120 "A scaled or unscaled indexed memory operand that can be used as the | |
| 121 source address in integer and floating-point loads." | |
| 122 (and (match_code "mem") | |
| 123 (match_test "IS_INDEX_ADDR_P (XEXP (op, 0))"))) | |
| 124 | |
| 125 (define_constraint "T" | |
| 126 "A memory operand for floating-point loads and stores." | |
| 127 (and (match_code "mem") | |
| 128 (match_test "!IS_LO_SUM_DLT_ADDR_P (XEXP (op, 0)) | |
| 129 && !IS_INDEX_ADDR_P (XEXP (op, 0)) | |
| 130 && memory_address_p ((GET_MODE_SIZE (mode) == 4 | |
| 131 ? SFmode : DFmode), | |
| 132 XEXP (op, 0))"))) | |
| 133 | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
134 ;; We could allow short displacements but TARGET_LEGITIMATE_ADDRESS_P |
| 0 | 135 ;; can't tell when a long displacement is valid. |
| 136 (define_constraint "W" | |
| 137 "A register indirect memory operand." | |
| 138 (and (match_code "mem") | |
| 139 (match_test "REG_P (XEXP (op, 0)) | |
| 140 && REG_OK_FOR_BASE_P (XEXP (op, 0))"))) |