|
0
|
1 /* Configuration for GCC-compiler for PA-RISC.
|
|
|
2 Copyright (C) 1999, 2000, 2003, 2004, 2007, 2008
|
|
|
3 Free Software Foundation, Inc.
|
|
|
4
|
|
|
5 This file is part of GCC.
|
|
|
6
|
|
|
7 GCC is free software; you can redistribute it and/or modify
|
|
|
8 it under the terms of the GNU General Public License as published by
|
|
|
9 the Free Software Foundation; either version 3, or (at your option)
|
|
|
10 any later version.
|
|
|
11
|
|
|
12 GCC is distributed in the hope that it will be useful,
|
|
|
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
15 GNU General Public License for more details.
|
|
|
16
|
|
|
17 You should have received a copy of the GNU General Public License
|
|
|
18 along with GCC; see the file COPYING3. If not see
|
|
|
19 <http://www.gnu.org/licenses/>. */
|
|
|
20
|
|
|
21 /* Standard register usage.
|
|
|
22
|
|
|
23 It is safe to refer to actual register numbers in this file. */
|
|
|
24
|
|
|
25 /* Number of actual hardware registers.
|
|
|
26 The hardware registers are assigned numbers for the compiler
|
|
|
27 from 0 to just below FIRST_PSEUDO_REGISTER.
|
|
|
28 All registers that the compiler knows about must be given numbers,
|
|
|
29 even those that are not normally considered general registers.
|
|
|
30
|
|
|
31 HP-PA 2.0w has 32 fullword registers and 32 floating point
|
|
|
32 registers. However, the floating point registers behave
|
|
|
33 differently: the left and right halves of registers are addressable
|
|
|
34 as 32-bit registers.
|
|
|
35
|
|
|
36 Due to limitations within GCC itself, we do not expose the left/right
|
|
|
37 half addressability when in wide mode. This is not a major performance
|
|
|
38 issue as using the halves independently triggers false dependency stalls
|
|
|
39 anyway. */
|
|
|
40
|
|
|
41 #define FIRST_PSEUDO_REGISTER 61 /* 32 general regs + 28 fp regs +
|
|
|
42 + 1 shift reg */
|
|
|
43
|
|
|
44 /* 1 for registers that have pervasive standard uses
|
|
|
45 and are not available for the register allocator.
|
|
|
46
|
|
|
47 On the HP-PA, these are:
|
|
|
48 Reg 0 = 0 (hardware). However, 0 is used for condition code,
|
|
|
49 so is not fixed.
|
|
|
50 Reg 1 = ADDIL target/Temporary (hardware).
|
|
|
51 Reg 2 = Return Pointer
|
|
|
52 Reg 3 = Frame Pointer
|
|
|
53 Reg 4 = Frame Pointer (>8k varying frame with HP compilers only)
|
|
|
54 Reg 4-18 = Preserved Registers
|
|
|
55 Reg 19 = Linkage Table Register in HPUX 8.0 shared library scheme.
|
|
|
56 Reg 20-22 = Temporary Registers
|
|
|
57 Reg 23-26 = Temporary/Parameter Registers
|
|
|
58 Reg 27 = Global Data Pointer (hp)
|
|
|
59 Reg 28 = Temporary/Return Value register
|
|
|
60 Reg 29 = Temporary/Static Chain/Return Value register #2
|
|
|
61 Reg 30 = stack pointer
|
|
|
62 Reg 31 = Temporary/Millicode Return Pointer (hp)
|
|
|
63
|
|
|
64 Freg 0-3 = Status Registers -- Not known to the compiler.
|
|
|
65 Freg 4-7 = Arguments/Return Value
|
|
|
66 Freg 8-11 = Temporary Registers
|
|
|
67 Freg 12-21 = Preserved Registers
|
|
|
68 Freg 22-31 = Temporary Registers
|
|
|
69
|
|
|
70 */
|
|
|
71
|
|
|
72 #define FIXED_REGISTERS \
|
|
|
73 {0, 0, 0, 0, 0, 0, 0, 0, \
|
|
|
74 0, 0, 0, 0, 0, 0, 0, 0, \
|
|
|
75 0, 0, 0, 0, 0, 0, 0, 0, \
|
|
|
76 0, 0, 0, 1, 0, 0, 1, 0, \
|
|
|
77 /* fp registers */ \
|
|
|
78 0, 0, 0, 0, 0, 0, 0, 0, \
|
|
|
79 0, 0, 0, 0, 0, 0, 0, 0, \
|
|
|
80 0, 0, 0, 0, 0, 0, 0, 0, \
|
|
|
81 0, 0, 0, 0, \
|
|
|
82 /* shift register */ \
|
|
|
83 0}
|
|
|
84
|
|
|
85 /* 1 for registers not available across function calls.
|
|
|
86 These must include the FIXED_REGISTERS and also any
|
|
|
87 registers that can be used without being saved.
|
|
|
88 The latter must include the registers where values are returned
|
|
|
89 and the register where structure-value addresses are passed.
|
|
|
90 Aside from that, you can include as many other registers as you like. */
|
|
|
91 #define CALL_USED_REGISTERS \
|
|
|
92 {1, 1, 1, 0, 0, 0, 0, 0, \
|
|
|
93 0, 0, 0, 0, 0, 0, 0, 0, \
|
|
|
94 0, 0, 0, 1, 1, 1, 1, 1, \
|
|
|
95 1, 1, 1, 1, 1, 1, 1, 1, \
|
|
|
96 /* fp registers */ \
|
|
|
97 1, 1, 1, 1, 1, 1, 1, 1, \
|
|
|
98 0, 0, 0, 0, 0, 0, 0, 0, \
|
|
|
99 0, 0, 1, 1, 1, 1, 1, 1, \
|
|
|
100 1, 1, 1, 1, \
|
|
|
101 /* shift register */ \
|
|
|
102 1}
|
|
|
103
|
|
|
104 #define CONDITIONAL_REGISTER_USAGE \
|
|
|
105 { \
|
|
|
106 int i; \
|
|
|
107 if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\
|
|
|
108 { \
|
|
|
109 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)\
|
|
|
110 fixed_regs[i] = call_used_regs[i] = 1; \
|
|
|
111 } \
|
|
|
112 if (flag_pic) \
|
|
|
113 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
|
|
|
114 }
|
|
|
115
|
|
|
116 /* Allocate the call used registers first. This should minimize
|
|
|
117 the number of registers that need to be saved (as call used
|
|
|
118 registers will generally not be allocated across a call).
|
|
|
119
|
|
|
120 Experimentation has shown slightly better results by allocating
|
|
|
121 FP registers first. We allocate the caller-saved registers more
|
|
|
122 or less in reverse order to their allocation as arguments. */
|
|
|
123
|
|
|
124 #define REG_ALLOC_ORDER \
|
|
|
125 { \
|
|
|
126 /* caller-saved fp regs. */ \
|
|
|
127 50, 51, 52, 53, 54, 55, 56, 57, \
|
|
|
128 58, 59, 39, 38, 37, 36, 35, 34, \
|
|
|
129 33, 32, \
|
|
|
130 /* caller-saved general regs. */ \
|
|
|
131 28, 31, 19, 20, 21, 22, 23, 24, \
|
|
|
132 25, 26, 29, 2, \
|
|
|
133 /* callee-saved fp regs. */ \
|
|
|
134 40, 41, 42, 43, 44, 45, 46, 47, \
|
|
|
135 48, 49, \
|
|
|
136 /* callee-saved general regs. */ \
|
|
|
137 3, 4, 5, 6, 7, 8, 9, 10, \
|
|
|
138 11, 12, 13, 14, 15, 16, 17, 18, \
|
|
|
139 /* special registers. */ \
|
|
|
140 1, 27, 30, 0, 60}
|
|
|
141
|
|
|
142
|
|
|
143 /* Return number of consecutive hard regs needed starting at reg REGNO
|
|
|
144 to hold something of mode MODE.
|
|
|
145 This is ordinarily the length in words of a value of mode MODE
|
|
|
146 but can be less for certain modes in special long registers.
|
|
|
147
|
|
|
148 For PA64, GPRs and FPRs hold 64 bits worth. We ignore the 32-bit
|
|
|
149 addressability of the FPRs and pretend each register holds precisely
|
|
|
150 WORD_SIZE bits. Note that SCmode values are placed in a single FPR.
|
|
|
151 Thus, any patterns defined to operate on these values would have to
|
|
|
152 use the 32-bit addressability of the FPR registers. */
|
|
|
153 #define HARD_REGNO_NREGS(REGNO, MODE) \
|
|
|
154 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
|
|
|
155
|
|
|
156 /* These are the valid FP modes. */
|
|
|
157 #define VALID_FP_MODE_P(MODE) \
|
|
|
158 ((MODE) == SFmode || (MODE) == DFmode \
|
|
|
159 || (MODE) == SCmode || (MODE) == DCmode \
|
|
|
160 || (MODE) == SImode || (MODE) == DImode)
|
|
|
161
|
|
|
162 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
|
|
|
163 On the HP-PA, the cpu registers can hold any mode. We
|
|
|
164 force this to be an even register is it cannot hold the full mode. */
|
|
|
165 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
|
|
|
166 ((REGNO) == 0 \
|
|
|
167 ? (MODE) == CCmode || (MODE) == CCFPmode \
|
|
|
168 /* Make wide modes be in aligned registers. */ \
|
|
|
169 : FP_REGNO_P (REGNO) \
|
|
|
170 ? (VALID_FP_MODE_P (MODE) \
|
|
|
171 && (GET_MODE_SIZE (MODE) <= 8 \
|
|
|
172 || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 1) == 0) \
|
|
|
173 || (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 3) == 0))) \
|
|
|
174 : (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \
|
|
|
175 || (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD \
|
|
|
176 && ((((REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28)) \
|
|
|
177 || (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD \
|
|
|
178 && ((REGNO) & 3) == 3 && (REGNO) <= 23)))
|
|
|
179
|
|
|
180 /* How to renumber registers for dbx and gdb.
|
|
|
181
|
|
|
182 Registers 0 - 31 remain unchanged.
|
|
|
183
|
|
|
184 Registers 32 - 59 are mapped to 72, 74, 76 ...
|
|
|
185
|
|
|
186 Register 60 is mapped to 32. */
|
|
|
187 #define DBX_REGISTER_NUMBER(REGNO) \
|
|
|
188 ((REGNO) <= 31 ? (REGNO) : ((REGNO) < 60 ? (REGNO - 32) * 2 + 72 : 32))
|
|
|
189
|
|
|
190 /* We must not use the DBX register numbers for the DWARF 2 CFA column
|
|
|
191 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
|
|
|
192 Instead use the identity mapping. */
|
|
|
193 #define DWARF_FRAME_REGNUM(REG) REG
|
|
|
194
|
|
|
195 /* Define the classes of registers for register constraints in the
|
|
|
196 machine description. Also define ranges of constants.
|
|
|
197
|
|
|
198 One of the classes must always be named ALL_REGS and include all hard regs.
|
|
|
199 If there is more than one class, another class must be named NO_REGS
|
|
|
200 and contain no registers.
|
|
|
201
|
|
|
202 The name GENERAL_REGS must be the name of a class (or an alias for
|
|
|
203 another name such as ALL_REGS). This is the class of registers
|
|
|
204 that is allowed by "g" or "r" in a register constraint.
|
|
|
205 Also, registers outside this class are allocated only when
|
|
|
206 instructions express preferences for them.
|
|
|
207
|
|
|
208 The classes must be numbered in nondecreasing order; that is,
|
|
|
209 a larger-numbered class must never be contained completely
|
|
|
210 in a smaller-numbered class.
|
|
|
211
|
|
|
212 For any two classes, it is very desirable that there be another
|
|
|
213 class that represents their union. */
|
|
|
214
|
|
|
215 /* The HP-PA has four kinds of registers: general regs, 1.0 fp regs,
|
|
|
216 1.1 fp regs, and the high 1.1 fp regs, to which the operands of
|
|
|
217 fmpyadd and fmpysub are restricted. */
|
|
|
218
|
|
|
219 enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
|
|
|
220 GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES};
|
|
|
221
|
|
|
222 #define N_REG_CLASSES (int) LIM_REG_CLASSES
|
|
|
223
|
|
|
224 /* Give names of register classes as strings for dump file. */
|
|
|
225
|
|
|
226 #define REG_CLASS_NAMES \
|
|
|
227 {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
|
|
|
228 "GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"}
|
|
|
229
|
|
|
230 /* Define which registers fit in which classes.
|
|
|
231 This is an initializer for a vector of HARD_REG_SET
|
|
|
232 of length N_REG_CLASSES. Register 0, the "condition code" register,
|
|
|
233 is in no class. */
|
|
|
234
|
|
|
235 #define REG_CLASS_CONTENTS \
|
|
|
236 {{0x00000000, 0x00000000}, /* NO_REGS */ \
|
|
|
237 {0x00000002, 0x00000000}, /* R1_REGS */ \
|
|
|
238 {0xfffffffe, 0x00000000}, /* GENERAL_REGS */ \
|
|
|
239 {0x00000000, 0x00000000}, /* FPUPPER_REGS */ \
|
|
|
240 {0x00000000, 0x0fffffff}, /* FP_REGS */ \
|
|
|
241 {0xfffffffe, 0x0fffffff}, /* GENERAL_OR_FP_REGS */ \
|
|
|
242 {0x00000000, 0x10000000}, /* SHIFT_REGS */ \
|
|
|
243 {0xfffffffe, 0x1fffffff}} /* ALL_REGS */
|
|
|
244
|
|
|
245 /* The following macro defines cover classes for Integrated Register
|
|
|
246 Allocator. Cover classes is a set of non-intersected register
|
|
|
247 classes covering all hard registers used for register allocation
|
|
|
248 purpose. Any move between two registers of a cover class should be
|
|
|
249 cheaper than load or store of the registers. The macro value is
|
|
|
250 array of register classes with LIM_REG_CLASSES used as the end
|
|
|
251 marker. */
|
|
|
252
|
|
|
253 #define IRA_COVER_CLASSES \
|
|
|
254 { \
|
|
|
255 GENERAL_REGS, FP_REGS, SHIFT_REGS, LIM_REG_CLASSES \
|
|
|
256 }
|
|
|
257
|
|
|
258 /* Defines invalid mode changes. */
|
|
|
259
|
|
|
260 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
|
|
|
261 pa_cannot_change_mode_class (FROM, TO, CLASS)
|
|
|
262
|
|
|
263 /* Return the class number of the smallest class containing
|
|
|
264 reg number REGNO. This could be a conditional expression
|
|
|
265 or could index an array. */
|
|
|
266
|
|
|
267 #define REGNO_REG_CLASS(REGNO) \
|
|
|
268 ((REGNO) == 0 ? NO_REGS \
|
|
|
269 : (REGNO) == 1 ? R1_REGS \
|
|
|
270 : (REGNO) < 32 ? GENERAL_REGS \
|
|
|
271 : (REGNO) < 60 ? FP_REGS \
|
|
|
272 : SHIFT_REGS)
|
|
|
273
|
|
|
274 /* Return the maximum number of consecutive registers
|
|
|
275 needed to represent mode MODE in a register of class CLASS. */
|
|
|
276 #define CLASS_MAX_NREGS(CLASS, MODE) \
|
|
|
277 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
|
|
|
278
|
|
|
279 /* 1 if N is a possible register number for function argument passing. */
|
|
|
280
|
|
|
281 #define FUNCTION_ARG_REGNO_P(N) \
|
|
|
282 ((((N) >= 19) && (N) <= 26) \
|
|
|
283 || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39))
|
|
|
284
|
|
|
285 /* How to refer to registers in assembler output.
|
|
|
286 This sequence is indexed by compiler's hard-register-number (see above). */
|
|
|
287
|
|
|
288 #define REGISTER_NAMES \
|
|
|
289 {"%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \
|
|
|
290 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \
|
|
|
291 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", \
|
|
|
292 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", \
|
|
|
293 "%fr4", "%fr5", "%fr6", "%fr7", "%fr8", "%fr9", "%fr10", "%fr11", \
|
|
|
294 "%fr12", "%fr13", "%fr14", "%fr15", "%fr16", "%fr17", "%fr18", "%fr19", \
|
|
|
295 "%fr20", "%fr21", "%fr22", "%fr23", "%fr24", "%fr25", "%fr26", "%fr27", \
|
|
|
296 "%fr28", "%fr29", "%fr30", "%fr31", "SAR"}
|
|
|
297
|
|
|
298 #define ADDITIONAL_REGISTER_NAMES \
|
|
|
299 {{"%cr11",60}}
|
|
|
300
|
|
|
301 #define FP_SAVED_REG_LAST 49
|
|
|
302 #define FP_SAVED_REG_FIRST 40
|
|
|
303 #define FP_REG_STEP 1
|
|
|
304 #define FP_REG_FIRST 32
|
|
|
305 #define FP_REG_LAST 59
|
