Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/rs6000/8540.md @ 55:77e2b8dfacca gcc-4.4.5
update it from 4.4.3 to 4.5.0
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Fri, 12 Feb 2010 23:39:51 +0900 |
| parents | a06113de4d67 |
| children | 04ced10e8804 |
| rev | line source |
|---|---|
| 0 | 1 ;; Pipeline description for Motorola PowerPC 8540 processor. |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
2 ;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc. |
| 0 | 3 ;; |
| 4 ;; This file is part of GCC. | |
| 5 | |
| 6 ;; GCC is free software; you can redistribute it and/or modify it | |
| 7 ;; under the terms of the GNU General Public License as published | |
| 8 ;; by the Free Software Foundation; either version 3, or (at your | |
| 9 ;; option) any later version. | |
| 10 | |
| 11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
| 12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 14 ;; License for more details. | |
| 15 | |
| 16 ;; You should have received a copy of the GNU General Public License | |
| 17 ;; along with GCC; see the file COPYING3. If not see | |
| 18 ;; <http://www.gnu.org/licenses/>. | |
| 19 | |
| 20 (define_automaton "ppc8540_most,ppc8540_long,ppc8540_retire") | |
| 21 (define_cpu_unit "ppc8540_decode_0,ppc8540_decode_1" "ppc8540_most") | |
| 22 | |
| 23 ;; We don't simulate general issue queue (GIC). If we have SU insn | |
| 24 ;; and then SU1 insn, they cannot be issued on the same cycle | |
| 25 ;; (although SU1 insn and then SU insn can be issued) because the SU | |
| 26 ;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle | |
| 27 ;; multipass insn scheduling will find the situation and issue the SU1 | |
| 28 ;; insn and then the SU insn. | |
| 29 (define_cpu_unit "ppc8540_issue_0,ppc8540_issue_1" "ppc8540_most") | |
| 30 | |
| 31 ;; We could describe completion buffers slots in combination with the | |
| 32 ;; retirement units and the order of completion but the result | |
| 33 ;; automaton would behave in the same way because we cannot describe | |
| 34 ;; real latency time with taking in order completion into account. | |
| 35 ;; Actually we could define the real latency time by querying reserved | |
| 36 ;; automaton units but the current scheduler uses latency time before | |
| 37 ;; issuing insns and making any reservations. | |
| 38 ;; | |
| 39 ;; So our description is aimed to achieve a insn schedule in which the | |
| 40 ;; insns would not wait in the completion buffer. | |
| 41 (define_cpu_unit "ppc8540_retire_0,ppc8540_retire_1" "ppc8540_retire") | |
| 42 | |
| 43 ;; Branch unit: | |
| 44 (define_cpu_unit "ppc8540_bu" "ppc8540_most") | |
| 45 | |
| 46 ;; SU: | |
| 47 (define_cpu_unit "ppc8540_su0_stage0,ppc8540_su1_stage0" "ppc8540_most") | |
| 48 | |
| 49 ;; We could describe here MU subunits for float multiply, float add | |
| 50 ;; etc. But the result automaton would behave the same way as the | |
| 51 ;; described one pipeline below because MU can start only one insn | |
| 52 ;; per cycle. Actually we could simplify the automaton more not | |
| 53 ;; describing stages 1-3, the result automata would be the same. | |
| 54 (define_cpu_unit "ppc8540_mu_stage0,ppc8540_mu_stage1" "ppc8540_most") | |
| 55 (define_cpu_unit "ppc8540_mu_stage2,ppc8540_mu_stage3" "ppc8540_most") | |
| 56 | |
| 57 ;; The following unit is used to describe non-pipelined division. | |
| 58 (define_cpu_unit "ppc8540_mu_div" "ppc8540_long") | |
| 59 | |
| 60 ;; Here we simplified LSU unit description not describing the stages. | |
| 61 (define_cpu_unit "ppc8540_lsu" "ppc8540_most") | |
| 62 | |
| 63 ;; The following units are used to make automata deterministic | |
| 64 (define_cpu_unit "present_ppc8540_decode_0" "ppc8540_most") | |
| 65 (define_cpu_unit "present_ppc8540_issue_0" "ppc8540_most") | |
| 66 (define_cpu_unit "present_ppc8540_retire_0" "ppc8540_retire") | |
| 67 (define_cpu_unit "present_ppc8540_su0_stage0" "ppc8540_most") | |
| 68 | |
| 69 ;; The following sets to make automata deterministic when option ndfa is used. | |
| 70 (presence_set "present_ppc8540_decode_0" "ppc8540_decode_0") | |
| 71 (presence_set "present_ppc8540_issue_0" "ppc8540_issue_0") | |
| 72 (presence_set "present_ppc8540_retire_0" "ppc8540_retire_0") | |
| 73 (presence_set "present_ppc8540_su0_stage0" "ppc8540_su0_stage0") | |
| 74 | |
| 75 ;; Some useful abbreviations. | |
| 76 (define_reservation "ppc8540_decode" | |
| 77 "ppc8540_decode_0|ppc8540_decode_1+present_ppc8540_decode_0") | |
| 78 (define_reservation "ppc8540_issue" | |
| 79 "ppc8540_issue_0|ppc8540_issue_1+present_ppc8540_issue_0") | |
| 80 (define_reservation "ppc8540_retire" | |
| 81 "ppc8540_retire_0|ppc8540_retire_1+present_ppc8540_retire_0") | |
| 82 (define_reservation "ppc8540_su_stage0" | |
| 83 "ppc8540_su0_stage0|ppc8540_su1_stage0+present_ppc8540_su0_stage0") | |
| 84 | |
| 85 ;; Simple SU insns | |
| 86 (define_insn_reservation "ppc8540_su" 1 | |
| 87 (and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\ | |
| 88 delayed_compare,var_delayed_compare,fast_compare,\ | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
89 shift,trap,var_shift_rotate,cntlz,exts,isel") |
| 0 | 90 (eq_attr "cpu" "ppc8540")) |
| 91 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") | |
| 92 | |
| 93 (define_insn_reservation "ppc8540_two" 1 | |
| 94 (and (eq_attr "type" "two") | |
| 95 (eq_attr "cpu" "ppc8540")) | |
| 96 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\ | |
| 97 ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") | |
| 98 | |
| 99 (define_insn_reservation "ppc8540_three" 1 | |
| 100 (and (eq_attr "type" "three") | |
| 101 (eq_attr "cpu" "ppc8540")) | |
| 102 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\ | |
| 103 ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\ | |
| 104 ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") | |
| 105 | |
| 106 ;; Branch. Actually this latency time is not used by the scheduler. | |
| 107 (define_insn_reservation "ppc8540_branch" 1 | |
| 108 (and (eq_attr "type" "jmpreg,branch,isync") | |
| 109 (eq_attr "cpu" "ppc8540")) | |
| 110 "ppc8540_decode,ppc8540_bu,ppc8540_retire") | |
| 111 | |
| 112 ;; Multiply | |
| 113 (define_insn_reservation "ppc8540_multiply" 4 | |
| 114 (and (eq_attr "type" "imul,imul2,imul3,imul_compare") | |
| 115 (eq_attr "cpu" "ppc8540")) | |
| 116 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\ | |
| 117 ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire") | |
| 118 | |
| 119 ;; Divide. We use the average latency time here. We omit reserving a | |
| 120 ;; retire unit because of the result automata will be huge. We ignore | |
| 121 ;; reservation of miu_stage3 here because we use the average latency | |
| 122 ;; time. | |
| 123 (define_insn_reservation "ppc8540_divide" 14 | |
| 124 (and (eq_attr "type" "idiv") | |
| 125 (eq_attr "cpu" "ppc8540")) | |
| 126 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\ | |
| 127 ppc8540_mu_div*13") | |
| 128 | |
| 129 ;; CR logical | |
| 130 (define_insn_reservation "ppc8540_cr_logical" 1 | |
| 131 (and (eq_attr "type" "cr_logical,delayed_cr") | |
| 132 (eq_attr "cpu" "ppc8540")) | |
| 133 "ppc8540_decode,ppc8540_bu,ppc8540_retire") | |
| 134 | |
| 135 ;; Mfcr | |
| 136 (define_insn_reservation "ppc8540_mfcr" 1 | |
| 137 (and (eq_attr "type" "mfcr") | |
| 138 (eq_attr "cpu" "ppc8540")) | |
| 139 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire") | |
| 140 | |
| 141 ;; Mtcrf | |
| 142 (define_insn_reservation "ppc8540_mtcrf" 1 | |
| 143 (and (eq_attr "type" "mtcr") | |
| 144 (eq_attr "cpu" "ppc8540")) | |
| 145 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire") | |
| 146 | |
| 147 ;; Mtjmpr | |
| 148 (define_insn_reservation "ppc8540_mtjmpr" 1 | |
| 149 (and (eq_attr "type" "mtjmpr,mfjmpr") | |
| 150 (eq_attr "cpu" "ppc8540")) | |
| 151 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") | |
| 152 | |
| 153 ;; Loads | |
| 154 (define_insn_reservation "ppc8540_load" 3 | |
| 155 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ | |
| 156 load_l,sync") | |
| 157 (eq_attr "cpu" "ppc8540")) | |
| 158 "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire") | |
| 159 | |
| 160 ;; Stores. | |
| 161 (define_insn_reservation "ppc8540_store" 3 | |
| 162 (and (eq_attr "type" "store,store_ux,store_u,store_c") | |
| 163 (eq_attr "cpu" "ppc8540")) | |
| 164 "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire") | |
| 165 | |
| 166 ;; Simple FP | |
| 167 (define_insn_reservation "ppc8540_simple_float" 1 | |
| 168 (and (eq_attr "type" "fpsimple") | |
| 169 (eq_attr "cpu" "ppc8540")) | |
| 170 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") | |
| 171 | |
| 172 ;; FP | |
| 173 (define_insn_reservation "ppc8540_float" 4 | |
| 174 (and (eq_attr "type" "fp") | |
| 175 (eq_attr "cpu" "ppc8540")) | |
| 176 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\ | |
| 177 ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire") | |
| 178 | |
| 179 ;; float divides. We omit reserving a retire unit and miu_stage3 | |
| 180 ;; because of the result automata will be huge. | |
| 181 (define_insn_reservation "ppc8540_float_vector_divide" 29 | |
| 182 (and (eq_attr "type" "vecfdiv") | |
| 183 (eq_attr "cpu" "ppc8540")) | |
| 184 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\ | |
| 185 ppc8540_mu_div*28") | |
| 186 | |
| 187 ;; Brinc | |
| 188 (define_insn_reservation "ppc8540_brinc" 1 | |
| 189 (and (eq_attr "type" "brinc") | |
| 190 (eq_attr "cpu" "ppc8540")) | |
| 191 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") | |
| 192 | |
| 193 ;; Simple vector | |
| 194 (define_insn_reservation "ppc8540_simple_vector" 1 | |
| 195 (and (eq_attr "type" "vecsimple") | |
| 196 (eq_attr "cpu" "ppc8540")) | |
| 197 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire") | |
| 198 | |
| 199 ;; Simple vector compare | |
| 200 (define_insn_reservation "ppc8540_simple_vector_compare" 1 | |
| 201 (and (eq_attr "type" "veccmpsimple") | |
| 202 (eq_attr "cpu" "ppc8540")) | |
| 203 "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") | |
| 204 | |
| 205 ;; Vector compare | |
| 206 (define_insn_reservation "ppc8540_vector_compare" 1 | |
| 207 (and (eq_attr "type" "veccmp") | |
| 208 (eq_attr "cpu" "ppc8540")) | |
| 209 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire") | |
| 210 | |
| 211 ;; evsplatfi evsplati | |
| 212 (define_insn_reservation "ppc8540_vector_perm" 1 | |
| 213 (and (eq_attr "type" "vecperm") | |
| 214 (eq_attr "cpu" "ppc8540")) | |
| 215 "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire") | |
| 216 | |
| 217 ;; Vector float | |
| 218 (define_insn_reservation "ppc8540_float_vector" 4 | |
| 219 (and (eq_attr "type" "vecfloat") | |
| 220 (eq_attr "cpu" "ppc8540")) | |
| 221 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\ | |
| 222 ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire") | |
| 223 | |
| 224 ;; Vector divides: Use the average. We omit reserving a retire unit | |
| 225 ;; because of the result automata will be huge. We ignore reservation | |
| 226 ;; of miu_stage3 here because we use the average latency time. | |
| 227 (define_insn_reservation "ppc8540_vector_divide" 14 | |
| 228 (and (eq_attr "type" "vecdiv") | |
| 229 (eq_attr "cpu" "ppc8540")) | |
| 230 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\ | |
| 231 ppc8540_mu_div*13") | |
| 232 | |
| 233 ;; Complex vector. | |
| 234 (define_insn_reservation "ppc8540_complex_vector" 4 | |
| 235 (and (eq_attr "type" "veccomplex") | |
| 236 (eq_attr "cpu" "ppc8540")) | |
| 237 "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\ | |
| 238 ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire") | |
| 239 | |
| 240 ;; Vector load | |
| 241 (define_insn_reservation "ppc8540_vector_load" 3 | |
| 242 (and (eq_attr "type" "vecload") | |
| 243 (eq_attr "cpu" "ppc8540")) | |
| 244 "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire") | |
| 245 | |
| 246 ;; Vector store | |
| 247 (define_insn_reservation "ppc8540_vector_store" 3 | |
| 248 (and (eq_attr "type" "vecstore") | |
| 249 (eq_attr "cpu" "ppc8540")) | |
| 250 "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire") |