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1 /* Machine description patterns for PowerPC running Darwin (Mac OS X).
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2 Copyright (C) 2004, 2005, 2007 Free Software Foundation, Inc.
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3 Contributed by Apple Computer Inc.
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4
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5 This file is part of GCC.
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6
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7 GNU CC is free software; you can redistribute it and/or modify
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8 it under the terms of the GNU General Public License as published by
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9 the Free Software Foundation; either version 3, or (at your option)
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10 any later version.
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11
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12 GNU CC is distributed in the hope that it will be useful,
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13 but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 GNU General Public License for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>. */
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20
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21 (define_insn "adddi3_high"
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22 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
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23 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b")
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24 (high:DI (match_operand 2 "" ""))))]
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25 "TARGET_MACHO && TARGET_64BIT"
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26 "{cau|addis} %0,%1,ha16(%2)"
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27 [(set_attr "length" "4")])
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28
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29 (define_insn "movdf_low_si"
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30 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
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31 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
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32 (match_operand 2 "" ""))))]
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33 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_64BIT"
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34 "*
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35 {
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36 switch (which_alternative)
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37 {
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38 case 0:
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39 return \"lfd %0,lo16(%2)(%1)\";
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40 case 1:
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41 {
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42 if (TARGET_POWERPC64 && TARGET_32BIT)
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43 /* Note, old assemblers didn't support relocation here. */
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44 return \"ld %0,lo16(%2)(%1)\";
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45 else
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46 {
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47 output_asm_insn (\"{cal|la} %0,lo16(%2)(%1)\", operands);
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48 output_asm_insn (\"{l|lwz} %L0,4(%0)\", operands);
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49 return (\"{l|lwz} %0,0(%0)\");
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50 }
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51 }
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52 default:
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53 gcc_unreachable ();
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54 }
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55 }"
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56 [(set_attr "type" "load")
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57 (set_attr "length" "4,12")])
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58
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59
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60 (define_insn "movdf_low_di"
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61 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
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62 (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
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63 (match_operand 2 "" ""))))]
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64 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
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65 "*
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66 {
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67 switch (which_alternative)
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68 {
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69 case 0:
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70 return \"lfd %0,lo16(%2)(%1)\";
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71 case 1:
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72 return \"ld %0,lo16(%2)(%1)\";
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73 default:
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74 gcc_unreachable ();
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75 }
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76 }"
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77 [(set_attr "type" "load")
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78 (set_attr "length" "4,4")])
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79
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80 (define_insn "movdf_low_st_si"
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81 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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82 (match_operand 2 "" "")))
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83 (match_operand:DF 0 "gpc_reg_operand" "f"))]
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84 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
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85 "stfd %0,lo16(%2)(%1)"
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86 [(set_attr "type" "store")
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87 (set_attr "length" "4")])
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88
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89 (define_insn "movdf_low_st_di"
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90 [(set (mem:DF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
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91 (match_operand 2 "" "")))
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92 (match_operand:DF 0 "gpc_reg_operand" "f"))]
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93 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
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94 "stfd %0,lo16(%2)(%1)"
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95 [(set_attr "type" "store")
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96 (set_attr "length" "4")])
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97
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98 (define_insn "movsf_low_si"
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99 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
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100 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
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101 (match_operand 2 "" ""))))]
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102 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
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103 "@
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104 lfs %0,lo16(%2)(%1)
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105 {l|lwz} %0,lo16(%2)(%1)"
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106 [(set_attr "type" "load")
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107 (set_attr "length" "4")])
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108
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109 (define_insn "movsf_low_di"
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110 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
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111 (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
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112 (match_operand 2 "" ""))))]
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113 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
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114 "@
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115 lfs %0,lo16(%2)(%1)
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116 {l|lwz} %0,lo16(%2)(%1)"
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117 [(set_attr "type" "load")
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118 (set_attr "length" "4")])
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119
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120 (define_insn "movsf_low_st_si"
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121 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
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122 (match_operand 2 "" "")))
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123 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
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124 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
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125 "@
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126 stfs %0,lo16(%2)(%1)
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127 {st|stw} %0,lo16(%2)(%1)"
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128 [(set_attr "type" "store")
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129 (set_attr "length" "4")])
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130
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131 (define_insn "movsf_low_st_di"
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132 [(set (mem:SF (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,b")
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133 (match_operand 2 "" "")))
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134 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
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135 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_64BIT"
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136 "@
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137 stfs %0,lo16(%2)(%1)
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138 {st|stw} %0,lo16(%2)(%1)"
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139 [(set_attr "type" "store")
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140 (set_attr "length" "4")])
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141
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142 ;; 64-bit MachO load/store support
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143 (define_insn "movdi_low"
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144 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
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145 (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
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146 (match_operand 2 "" ""))))]
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147 "TARGET_MACHO && TARGET_64BIT"
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148 "{l|ld} %0,lo16(%2)(%1)"
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149 [(set_attr "type" "load")
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150 (set_attr "length" "4")])
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151
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152 (define_insn "movsi_low_st"
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153 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
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154 (match_operand 2 "" "")))
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155 (match_operand:SI 0 "gpc_reg_operand" "r"))]
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156 "TARGET_MACHO && ! TARGET_64BIT"
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157 "{st|stw} %0,lo16(%2)(%1)"
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158 [(set_attr "type" "store")
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159 (set_attr "length" "4")])
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160
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161 (define_insn "movdi_low_st"
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162 [(set (mem:DI (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
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163 (match_operand 2 "" "")))
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164 (match_operand:DI 0 "gpc_reg_operand" "r"))]
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165 "TARGET_MACHO && TARGET_64BIT"
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166 "{st|std} %0,lo16(%2)(%1)"
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167 [(set_attr "type" "store")
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168 (set_attr "length" "4")])
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169
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170 ;; Mach-O PIC trickery.
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171 (define_expand "macho_high"
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172 [(set (match_operand 0 "" "")
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173 (high (match_operand 1 "" "")))]
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174 "TARGET_MACHO"
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175 {
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176 if (TARGET_64BIT)
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177 emit_insn (gen_macho_high_di (operands[0], operands[1]));
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178 else
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179 emit_insn (gen_macho_high_si (operands[0], operands[1]));
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180
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181 DONE;
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182 })
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183
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184 (define_insn "macho_high_si"
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185 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
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186 (high:SI (match_operand 1 "" "")))]
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187 "TARGET_MACHO && ! TARGET_64BIT"
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188 "{liu|lis} %0,ha16(%1)")
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189
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190
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191 (define_insn "macho_high_di"
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192 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
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193 (high:DI (match_operand 1 "" "")))]
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194 "TARGET_MACHO && TARGET_64BIT"
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195 "{liu|lis} %0,ha16(%1)")
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196
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197 (define_expand "macho_low"
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198 [(set (match_operand 0 "" "")
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199 (lo_sum (match_operand 1 "" "")
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200 (match_operand 2 "" "")))]
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201 "TARGET_MACHO"
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202 {
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203 if (TARGET_64BIT)
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204 emit_insn (gen_macho_low_di (operands[0], operands[1], operands[2]));
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205 else
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206 emit_insn (gen_macho_low_si (operands[0], operands[1], operands[2]));
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207
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208 DONE;
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209 })
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210
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211 (define_insn "macho_low_si"
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212 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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213 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
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214 (match_operand 2 "" "")))]
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215 "TARGET_MACHO && ! TARGET_64BIT"
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216 "@
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217 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
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218 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
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219
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220 (define_insn "macho_low_di"
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221 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
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222 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
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223 (match_operand 2 "" "")))]
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224 "TARGET_MACHO && TARGET_64BIT"
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225 "@
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226 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
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227 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
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228
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229 (define_split
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230 [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")
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231 (match_operand:DI 1 "short_cint_operand" "")))
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232 (match_operand:V4SI 2 "register_operand" ""))
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233 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
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234 "TARGET_MACHO && TARGET_64BIT"
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235 [(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1)))
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236 (set (mem:V4SI (match_dup 3))
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237 (match_dup 2))]
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238 "")
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239
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240 (define_expand "load_macho_picbase"
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241 [(set (reg:SI 65)
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242 (unspec [(match_operand 0 "" "")]
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243 UNSPEC_LD_MPIC))]
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244 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
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245 {
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246 if (TARGET_32BIT)
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247 emit_insn (gen_load_macho_picbase_si (operands[0]));
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248 else
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249 emit_insn (gen_load_macho_picbase_di (operands[0]));
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250
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251 DONE;
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252 })
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253
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254 (define_insn "load_macho_picbase_si"
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255 [(set (reg:SI 65)
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256 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
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257 (pc)] UNSPEC_LD_MPIC))]
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258 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
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259 "bcl 20,31,%0\\n%0:"
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260 [(set_attr "type" "branch")
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261 (set_attr "length" "4")])
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262
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263 (define_insn "load_macho_picbase_di"
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264 [(set (reg:DI 65)
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265 (unspec:DI [(match_operand:DI 0 "immediate_operand" "s")
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266 (pc)] UNSPEC_LD_MPIC))]
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267 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic && TARGET_64BIT"
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268 "bcl 20,31,%0\\n%0:"
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269 [(set_attr "type" "branch")
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270 (set_attr "length" "4")])
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271
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272 (define_expand "macho_correct_pic"
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273 [(set (match_operand 0 "" "")
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274 (plus (match_operand 1 "" "")
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275 (unspec [(match_operand 2 "" "")
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276 (match_operand 3 "" "")]
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277 UNSPEC_MPIC_CORRECT)))]
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278 "DEFAULT_ABI == ABI_DARWIN"
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279 {
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280 if (TARGET_32BIT)
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281 emit_insn (gen_macho_correct_pic_si (operands[0], operands[1], operands[2],
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282 operands[3]));
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283 else
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284 emit_insn (gen_macho_correct_pic_di (operands[0], operands[1], operands[2],
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285 operands[3]));
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286
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287 DONE;
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288 })
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289
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290 (define_insn "macho_correct_pic_si"
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291 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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292 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
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293 (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
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294 (match_operand:SI 3 "immediate_operand" "s")]
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295 UNSPEC_MPIC_CORRECT)))]
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296 "DEFAULT_ABI == ABI_DARWIN"
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297 "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
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298 [(set_attr "length" "8")])
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299
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300 (define_insn "macho_correct_pic_di"
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301 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
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302 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
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303 (unspec:DI [(match_operand:DI 2 "immediate_operand" "s")
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304 (match_operand:DI 3 "immediate_operand" "s")]
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305 16)))]
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306 "DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
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307 "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
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308 [(set_attr "length" "8")])
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309
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310 (define_insn "*call_indirect_nonlocal_darwin64"
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311 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l,c,*l"))
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312 (match_operand 1 "" "g,g,g,g"))
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313 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
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314 (clobber (reg:SI 65))]
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315 "DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT"
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316 {
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317 return "b%T0l";
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318 }
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319 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
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320 (set_attr "length" "4,4,8,8")])
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321
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322 (define_insn "*call_nonlocal_darwin64"
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323 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
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324 (match_operand 1 "" "g,g"))
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325 (use (match_operand:SI 2 "immediate_operand" "O,n"))
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326 (clobber (reg:SI 65))]
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327 "(DEFAULT_ABI == ABI_DARWIN)
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328 && (INTVAL (operands[2]) & CALL_LONG) == 0"
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329 {
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330 #if TARGET_MACHO
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331 return output_call(insn, operands, 0, 2);
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332 #else
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333 gcc_unreachable ();
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334 #endif
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335 }
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336 [(set_attr "type" "branch,branch")
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337 (set_attr "length" "4,8")])
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338
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339 (define_insn "*call_value_indirect_nonlocal_darwin64"
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340 [(set (match_operand 0 "" "")
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341 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l,c,*l"))
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342 (match_operand 2 "" "g,g,g,g")))
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343 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
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344 (clobber (reg:SI 65))]
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345 "DEFAULT_ABI == ABI_DARWIN"
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346 {
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347 return "b%T1l";
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348 }
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349 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
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350 (set_attr "length" "4,4,8,8")])
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351
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352 (define_insn "*call_value_nonlocal_darwin64"
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353 [(set (match_operand 0 "" "")
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354 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
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355 (match_operand 2 "" "g,g")))
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356 (use (match_operand:SI 3 "immediate_operand" "O,n"))
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357 (clobber (reg:SI 65))]
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358 "(DEFAULT_ABI == ABI_DARWIN)
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359 && (INTVAL (operands[3]) & CALL_LONG) == 0"
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360 {
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361 #if TARGET_MACHO
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362 return output_call(insn, operands, 1, 3);
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363 #else
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364 gcc_unreachable ();
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365 #endif
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366 }
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367 [(set_attr "type" "branch,branch")
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368 (set_attr "length" "4,8")])
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369
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370 (define_insn "*sibcall_nonlocal_darwin64"
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371 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s,s"))
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372 (match_operand 1 "" ""))
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373 (use (match_operand 2 "immediate_operand" "O,n"))
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374 (use (reg:SI 65))
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375 (return)]
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376 "(DEFAULT_ABI == ABI_DARWIN)
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377 && (INTVAL (operands[2]) & CALL_LONG) == 0"
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378 {
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379 return "b %z0";
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380 }
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381 [(set_attr "type" "branch,branch")
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382 (set_attr "length" "4,8")])
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383
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384 (define_insn "*sibcall_value_nonlocal_darwin64"
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385 [(set (match_operand 0 "" "")
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386 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s,s"))
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387 (match_operand 2 "" "")))
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388 (use (match_operand:SI 3 "immediate_operand" "O,n"))
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389 (use (reg:SI 65))
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390 (return)]
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391 "(DEFAULT_ABI == ABI_DARWIN)
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392 && (INTVAL (operands[3]) & CALL_LONG) == 0"
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393 "*
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394 {
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395 return \"b %z1\";
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396 }"
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397 [(set_attr "type" "branch,branch")
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398 (set_attr "length" "4,8")])
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399
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400
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401 (define_insn "*sibcall_symbolic_64"
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402 [(call (mem:SI (match_operand:DI 0 "call_operand" "s,c")) ; 64
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403 (match_operand 1 "" ""))
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404 (use (match_operand 2 "" ""))
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405 (use (reg:SI 65))
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406 (return)]
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407 "TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN"
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408 "*
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409 {
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410 switch (which_alternative)
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411 {
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412 case 0: return \"b %z0\";
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413 case 1: return \"b%T0\";
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414 default: gcc_unreachable ();
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415 }
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416 }"
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417 [(set_attr "type" "branch")
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418 (set_attr "length" "4")])
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419
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420 (define_insn "*sibcall_value_symbolic_64"
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421 [(set (match_operand 0 "" "")
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422 (call (mem:SI (match_operand:DI 1 "call_operand" "s,c"))
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423 (match_operand 2 "" "")))
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424 (use (match_operand:SI 3 "" ""))
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425 (use (reg:SI 65))
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426 (return)]
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427 "TARGET_64BIT && DEFAULT_ABI == ABI_DARWIN"
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428 "*
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429 {
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430 switch (which_alternative)
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431 {
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432 case 0: return \"b %z1\";
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433 case 1: return \"b%T1\";
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434 default: gcc_unreachable ();
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435 }
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436 }"
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437 [(set_attr "type" "branch")
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438 (set_attr "length" "4")])
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