Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/rs6000/rs6000.opt @ 55:77e2b8dfacca gcc-4.4.5
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author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
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date | Fri, 12 Feb 2010 23:39:51 +0900 |
parents | a06113de4d67 |
children | f6334be47118 |
rev | line source |
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0 | 1 ; Options for the rs6000 port of the compiler |
2 ; | |
3 ; Copyright (C) 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. | |
4 ; Contributed by Aldy Hernandez <aldy@quesejoda.com>. | |
5 ; | |
6 ; This file is part of GCC. | |
7 ; | |
8 ; GCC is free software; you can redistribute it and/or modify it under | |
9 ; the terms of the GNU General Public License as published by the Free | |
10 ; Software Foundation; either version 3, or (at your option) any later | |
11 ; version. | |
12 ; | |
13 ; GCC is distributed in the hope that it will be useful, but WITHOUT | |
14 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 ; License for more details. | |
17 ; | |
18 ; You should have received a copy of the GNU General Public License | |
19 ; along with GCC; see the file COPYING3. If not see | |
20 ; <http://www.gnu.org/licenses/>. | |
21 | |
22 mpower | |
23 Target Report RejectNegative Mask(POWER) | |
24 Use POWER instruction set | |
25 | |
26 mno-power | |
27 Target Report RejectNegative | |
28 Do not use POWER instruction set | |
29 | |
30 mpower2 | |
31 Target Report Mask(POWER2) | |
32 Use POWER2 instruction set | |
33 | |
34 mpowerpc | |
35 Target Report RejectNegative Mask(POWERPC) | |
36 Use PowerPC instruction set | |
37 | |
38 mno-powerpc | |
39 Target Report RejectNegative | |
40 Do not use PowerPC instruction set | |
41 | |
42 mpowerpc64 | |
43 Target Report Mask(POWERPC64) | |
44 Use PowerPC-64 instruction set | |
45 | |
46 mpowerpc-gpopt | |
47 Target Report Mask(PPC_GPOPT) | |
48 Use PowerPC General Purpose group optional instructions | |
49 | |
50 mpowerpc-gfxopt | |
51 Target Report Mask(PPC_GFXOPT) | |
52 Use PowerPC Graphics group optional instructions | |
53 | |
54 mmfcrf | |
55 Target Report Mask(MFCRF) | |
56 Use PowerPC V2.01 single field mfcr instruction | |
57 | |
58 mpopcntb | |
59 Target Report Mask(POPCNTB) | |
60 Use PowerPC V2.02 popcntb instruction | |
61 | |
62 mfprnd | |
63 Target Report Mask(FPRND) | |
64 Use PowerPC V2.02 floating point rounding instructions | |
65 | |
66 mcmpb | |
67 Target Report Mask(CMPB) | |
68 Use PowerPC V2.05 compare bytes instruction | |
69 | |
70 mmfpgpr | |
71 Target Report Mask(MFPGPR) | |
72 Use extended PowerPC V2.05 move floating point to/from GPR instructions | |
73 | |
74 maltivec | |
75 Target Report Mask(ALTIVEC) | |
76 Use AltiVec instructions | |
77 | |
78 mhard-dfp | |
79 Target Report Mask(DFP) | |
80 Use decimal floating point instructions | |
81 | |
82 mmulhw | |
83 Target Report Mask(MULHW) | |
84 Use 4xx half-word multiply instructions | |
85 | |
86 mdlmzb | |
87 Target Report Mask(DLMZB) | |
88 Use 4xx string-search dlmzb instruction | |
89 | |
90 mmultiple | |
91 Target Report Mask(MULTIPLE) | |
92 Generate load/store multiple instructions | |
93 | |
94 mstring | |
95 Target Report Mask(STRING) | |
96 Generate string instructions for block moves | |
97 | |
98 mnew-mnemonics | |
99 Target Report RejectNegative Mask(NEW_MNEMONICS) | |
100 Use new mnemonics for PowerPC architecture | |
101 | |
102 mold-mnemonics | |
103 Target Report RejectNegative InverseMask(NEW_MNEMONICS) | |
104 Use old mnemonics for PowerPC architecture | |
105 | |
106 msoft-float | |
107 Target Report RejectNegative Mask(SOFT_FLOAT) | |
108 Do not use hardware floating point | |
109 | |
110 mhard-float | |
111 Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) | |
112 Use hardware floating point | |
113 | |
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114 mpopcntd |
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115 Target Report Mask(POPCNTD) |
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116 Use PowerPC V2.06 popcntd instruction |
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117 |
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118 mvsx |
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119 Target Report Mask(VSX) |
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120 Use vector/scalar (VSX) instructions |
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121 |
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122 mvsx-scalar-double |
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123 Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(-1) |
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124 ; If -mvsx, use VSX arithmetic instructions for scalar double (on by default) |
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125 |
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126 mvsx-scalar-memory |
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127 Target Undocumented Report Var(TARGET_VSX_SCALAR_MEMORY) |
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128 ; If -mvsx, use VSX scalar memory reference instructions for scalar double (off by default) |
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129 |
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130 mvsx-align-128 |
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131 Target Undocumented Report Var(TARGET_VSX_ALIGN_128) |
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132 ; If -mvsx, set alignment to 128 bits instead of 32/64 |
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133 |
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134 mallow-movmisalign |
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135 Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) |
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136 ; Allow/disallow the movmisalign in DF/DI vectors |
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137 |
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138 mallow-df-permute |
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139 Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE) |
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140 ; Allow/disallow permutation of DF/DI vectors |
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141 |
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142 msched-groups |
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143 Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) |
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144 ; Explicitly set/unset whether rs6000_sched_groups is set |
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145 |
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146 malways-hint |
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147 Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) |
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148 ; Explicitly set/unset whether rs6000_always_hint is set |
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149 |
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150 malign-branch-targets |
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151 Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) |
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152 ; Explicitly set/unset whether rs6000_align_branch_targets is set |
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153 |
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154 mvectorize-builtins |
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155 Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1) |
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156 ; Explicitly control whether we vectorize the builtins or not. |
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157 |
0 | 158 mno-update |
159 Target Report RejectNegative Mask(NO_UPDATE) | |
160 Do not generate load/store with update instructions | |
161 | |
162 mupdate | |
163 Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) | |
164 Generate load/store with update instructions | |
165 | |
166 mavoid-indexed-addresses | |
167 Target Report Var(TARGET_AVOID_XFORM) Init(-1) | |
168 Avoid generation of indexed load/store instructions when possible | |
169 | |
170 mfused-madd | |
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171 Target Report Var(TARGET_FUSED_MADD) Init(1) |
0 | 172 Generate fused multiply/add instructions |
173 | |
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174 mtls-markers |
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175 Target Report Var(tls_markers) Init(1) |
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176 Mark __tls_get_addr calls with argument info |
0 | 177 |
178 msched-epilog | |
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179 Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) |
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180 |
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181 msched-prolog |
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182 Target Report Var(TARGET_SCHED_PROLOG) VarExists |
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183 Schedule the start and end of the procedure |
0 | 184 |
185 maix-struct-return | |
186 Target Report RejectNegative Var(aix_struct_return) | |
187 Return all structures in memory (AIX default) | |
188 | |
189 msvr4-struct-return | |
190 Target Report RejectNegative Var(aix_struct_return,0) VarExists | |
191 Return small structures in registers (SVR4 default) | |
192 | |
193 mxl-compat | |
194 Target Report Var(TARGET_XL_COMPAT) | |
195 Conform more closely to IBM XLC semantics | |
196 | |
197 mrecip | |
198 Target Report Var(TARGET_RECIP) | |
199 Generate software reciprocal sqrt for better throughput | |
200 | |
201 mno-fp-in-toc | |
202 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) | |
203 Do not place floating point constants in TOC | |
204 | |
205 mfp-in-toc | |
206 Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) | |
207 Place floating point constants in TOC | |
208 | |
209 mno-sum-in-toc | |
210 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) | |
211 Do not place symbol+offset constants in TOC | |
212 | |
213 msum-in-toc | |
214 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) VarExists | |
215 Place symbol+offset constants in TOC | |
216 | |
217 ; Output only one TOC entry per module. Normally linking fails if | |
218 ; there are more than 16K unique variables/constants in an executable. With | |
219 ; this option, linking fails only if there are more than 16K modules, or | |
220 ; if there are more than 16K unique variables/constant in a single module. | |
221 ; | |
222 ; This is at the cost of having 2 extra loads and one extra store per | |
223 ; function, and one less allocable register. | |
224 mminimal-toc | |
225 Target Report Mask(MINIMAL_TOC) | |
226 Use only one TOC entry per procedure | |
227 | |
228 mfull-toc | |
229 Target Report | |
230 Put everything in the regular TOC | |
231 | |
232 mvrsave | |
233 Target Report Var(TARGET_ALTIVEC_VRSAVE) | |
234 Generate VRSAVE instructions when generating AltiVec code | |
235 | |
236 mvrsave= | |
237 Target RejectNegative Joined | |
238 -mvrsave=yes/no Deprecated option. Use -mvrsave/-mno-vrsave instead | |
239 | |
240 misel | |
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241 Target Report Mask(ISEL) |
0 | 242 Generate isel instructions |
243 | |
244 misel= | |
245 Target RejectNegative Joined | |
246 -misel=yes/no Deprecated option. Use -misel/-mno-isel instead | |
247 | |
248 mspe | |
249 Target | |
250 Generate SPE SIMD instructions on E500 | |
251 | |
252 mpaired | |
253 Target Var(rs6000_paired_float) | |
254 Generate PPC750CL paired-single instructions | |
255 | |
256 mspe= | |
257 Target RejectNegative Joined | |
258 -mspe=yes/no Deprecated option. Use -mspe/-mno-spe instead | |
259 | |
260 mdebug= | |
261 Target RejectNegative Joined | |
262 -mdebug= Enable debug output | |
263 | |
264 mabi= | |
265 Target RejectNegative Joined | |
266 -mabi= Specify ABI to use | |
267 | |
268 mcpu= | |
269 Target RejectNegative Joined | |
270 -mcpu= Use features of and schedule code for given CPU | |
271 | |
272 mtune= | |
273 Target RejectNegative Joined | |
274 -mtune= Schedule code for given CPU | |
275 | |
276 mtraceback= | |
277 Target RejectNegative Joined | |
278 -mtraceback= Select full, part, or no traceback table | |
279 | |
280 mlongcall | |
281 Target Report Var(rs6000_default_long_calls) | |
282 Avoid all range limits on call instructions | |
283 | |
284 mgen-cell-microcode | |
285 Target Report Var(rs6000_gen_cell_microcode) Init(-1) | |
286 Generate Cell microcode | |
287 | |
288 mwarn-cell-microcode | |
289 Target Var(rs6000_warn_cell_microcode) Init(0) Warning | |
290 Warn when a Cell microcoded instruction is emitted | |
291 | |
292 mwarn-altivec-long | |
293 Target Var(rs6000_warn_altivec_long) Init(1) | |
294 Warn about deprecated 'vector long ...' AltiVec type usage | |
295 | |
296 mfloat-gprs= | |
297 Target RejectNegative Joined | |
298 -mfloat-gprs= Select GPR floating point method | |
299 | |
300 mlong-double- | |
301 Target RejectNegative Joined UInteger | |
302 -mlong-double-<n> Specify size of long double (64 or 128 bits) | |
303 | |
304 msched-costly-dep= | |
305 Target RejectNegative Joined | |
306 Determine which dependences between insns are considered costly | |
307 | |
308 minsert-sched-nops= | |
309 Target RejectNegative Joined | |
310 Specify which post scheduling nop insertion scheme to apply | |
311 | |
312 malign- | |
313 Target RejectNegative Joined | |
314 Specify alignment of structure fields default/natural | |
315 | |
316 mprioritize-restricted-insns= | |
317 Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) | |
318 Specify scheduling priority for dispatch slot restricted insns | |
319 | |
320 msingle-float | |
321 Target RejectNegative Var(rs6000_single_float) | |
322 Single-precision floating point unit | |
323 | |
324 mdouble-float | |
325 Target RejectNegative Var(rs6000_double_float) | |
326 Double-precision floating point unit | |
327 | |
328 msimple-fpu | |
329 Target RejectNegative Var(rs6000_simple_fpu) | |
330 Floating point unit does not support divide & sqrt | |
331 | |
332 mfpu= | |
333 Target RejectNegative Joined | |
334 -mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu) | |
335 | |
336 mxilinx-fpu | |
337 Target Var(rs6000_xilinx_fpu) | |
338 Specify Xilinx FPU. | |
339 | |
340 |