Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/s390/2084.md @ 55:77e2b8dfacca gcc-4.4.5
update it from 4.4.3 to 4.5.0
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Fri, 12 Feb 2010 23:39:51 +0900 |
| parents | 855418dad1a3 |
| children | f6334be47118 |
| rev | line source |
|---|---|
| 0 | 1 ;; Scheduling description for z990 (cpu 2084). |
| 2 ;; Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008 | |
| 3 ;; Free Software Foundation, Inc. | |
| 4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and | |
| 5 ;; Ulrich Weigand (uweigand@de.ibm.com). | |
| 6 | |
| 7 ;; This file is part of GCC. | |
| 8 | |
| 9 ;; GCC is free software; you can redistribute it and/or modify it under | |
| 10 ;; the terms of the GNU General Public License as published by the Free | |
| 11 ;; Software Foundation; either version 3, or (at your option) any later | |
| 12 ;; version. | |
| 13 | |
| 14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
| 15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 17 ;; for more details. | |
| 18 | |
| 19 ;; You should have received a copy of the GNU General Public License | |
| 20 ;; along with GCC; see the file COPYING3. If not see | |
| 21 ;; <http://www.gnu.org/licenses/>. | |
| 22 | |
| 23 (define_automaton "x_ipu") | |
| 24 | |
| 25 (define_cpu_unit "x_e1_r,x_e1_s,x_e1_t" "x_ipu") | |
| 26 (define_cpu_unit "x_wr_r,x_wr_s,x_wr_t,x_wr_fp" "x_ipu") | |
| 27 (define_cpu_unit "x_s1,x_s2,x_s3,x_s4" "x_ipu") | |
| 28 (define_cpu_unit "x_t1,x_t2,x_t3,x_t4" "x_ipu") | |
| 29 (define_cpu_unit "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6" "x_ipu") | |
| 30 (define_cpu_unit "x_store_tok" "x_ipu") | |
| 31 (define_cpu_unit "x_ms,x_mt" "x_ipu") | |
| 32 | |
| 33 (define_reservation "x-e1-st" "(x_e1_s | x_e1_t)") | |
| 34 | |
| 35 (define_reservation "x-e1-np" "(x_e1_r + x_e1_s + x_e1_t)") | |
| 36 | |
| 37 (absence_set "x_e1_r" "x_e1_s,x_e1_t") | |
| 38 (absence_set "x_e1_s" "x_e1_t") | |
| 39 | |
| 40 ;; Try to avoid int <-> fp transitions. | |
| 41 | |
| 42 (define_reservation "x-x" "x_s1|x_t1,x_s2|x_t2,x_s3|x_t3,x_s4|x_t4") | |
| 43 (define_reservation "x-f" "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6") | |
| 44 (define_reservation "x-wr-st" "((x_wr_s | x_wr_t),x-x)") | |
| 45 (define_reservation "x-wr-np" "((x_wr_r + x_wr_s + x_wr_t),x-x)") | |
| 46 (define_reservation "x-wr-fp" "x_wr_fp,x-f") | |
| 47 (define_reservation "x-mem" "x_ms|x_mt") | |
| 48 | |
| 49 (absence_set "x_wr_fp" | |
| 50 "x_s1,x_s2,x_s3,x_s4,x_t1,x_t2,x_t3,x_t4,x_wr_s,x_wr_t") | |
| 51 | |
| 52 (absence_set "x_e1_r,x_wr_r,x_wr_s,x_wr_t" | |
| 53 "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6,x_wr_fp") | |
| 54 | |
| 55 ;; Don't have any load type insn in same group as store | |
| 56 | |
| 57 (absence_set "x_ms,x_mt" "x_store_tok") | |
| 58 | |
| 59 | |
| 60 ;; | |
| 61 ;; Simple insns | |
| 62 ;; | |
| 63 | |
| 64 (define_insn_reservation "x_int" 1 | |
| 65 (and (eq_attr "cpu" "z990,z9_109") | |
| 66 (and (eq_attr "type" "integer") | |
| 67 (eq_attr "atype" "reg"))) | |
| 68 "x-e1-st,x-wr-st") | |
| 69 | |
| 70 (define_insn_reservation "x_agen" 1 | |
| 71 (and (eq_attr "cpu" "z990,z9_109") | |
| 72 (and (eq_attr "type" "integer") | |
| 73 (eq_attr "atype" "agen"))) | |
| 74 "x-e1-st,x-wr-st") | |
| 75 | |
| 76 (define_insn_reservation "x_lr" 1 | |
| 77 (and (eq_attr "cpu" "z990,z9_109") | |
| 78 (eq_attr "type" "lr")) | |
|
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79 "x-e1-st,x-wr-st") |
| 0 | 80 |
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81 (define_insn_reservation "x_la" 1 |
| 0 | 82 (and (eq_attr "cpu" "z990,z9_109") |
| 83 (eq_attr "type" "la")) | |
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84 "x-e1-st,x-wr-st") |
| 0 | 85 |
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86 (define_insn_reservation "x_larl" 1 |
| 0 | 87 (and (eq_attr "cpu" "z990,z9_109") |
| 88 (eq_attr "type" "larl")) | |
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89 "x-e1-st,x-wr-st") |
| 0 | 90 |
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91 (define_insn_reservation "x_load" 1 |
| 0 | 92 (and (eq_attr "cpu" "z990,z9_109") |
| 93 (eq_attr "type" "load")) | |
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94 "x-e1-st+x-mem,x-wr-st") |
| 0 | 95 |
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96 (define_insn_reservation "x_store" 1 |
| 0 | 97 (and (eq_attr "cpu" "z990,z9_109") |
| 98 (eq_attr "type" "store")) | |
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99 "x-e1-st+x_store_tok,x-wr-st") |
| 0 | 100 |
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101 (define_insn_reservation "x_branch" 1 |
| 0 | 102 (and (eq_attr "cpu" "z990,z9_109") |
| 103 (eq_attr "type" "branch")) | |
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104 "x_e1_r,x_wr_r") |
| 0 | 105 |
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106 (define_insn_reservation "x_call" 5 |
| 0 | 107 (and (eq_attr "cpu" "z990,z9_109") |
| 108 (eq_attr "type" "jsr")) | |
| 109 "x-e1-np*5,x-wr-np") | |
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110 |
| 0 | 111 (define_insn_reservation "x_mul_hi" 2 |
| 112 (and (eq_attr "cpu" "z990,z9_109") | |
| 113 (eq_attr "type" "imulhi")) | |
| 114 "x-e1-np*2,x-wr-np") | |
| 115 | |
| 116 (define_insn_reservation "x_mul_sidi" 4 | |
| 117 (and (eq_attr "cpu" "z990,z9_109") | |
| 118 (eq_attr "type" "imulsi,imuldi")) | |
| 119 "x-e1-np*4,x-wr-np") | |
| 120 | |
| 121 (define_insn_reservation "x_div" 10 | |
| 122 (and (eq_attr "cpu" "z990,z9_109") | |
| 123 (eq_attr "type" "idiv")) | |
| 124 "x-e1-np*10,x-wr-np") | |
| 125 | |
|
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126 (define_insn_reservation "x_sem" 17 |
| 0 | 127 (and (eq_attr "cpu" "z990,z9_109") |
| 128 (eq_attr "type" "sem")) | |
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129 "x-e1-np+x-mem,x-e1-np*16,x-wr-st") |
| 0 | 130 |
| 131 ;; | |
| 132 ;; Multicycle insns | |
| 133 ;; | |
| 134 | |
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135 (define_insn_reservation "x_cs" 1 |
| 0 | 136 (and (eq_attr "cpu" "z990,z9_109") |
| 137 (eq_attr "type" "cs")) | |
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138 "x-e1-np,x-wr-np") |
| 0 | 139 |
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140 (define_insn_reservation "x_vs" 1 |
| 0 | 141 (and (eq_attr "cpu" "z990,z9_109") |
| 142 (eq_attr "type" "vs")) | |
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143 "x-e1-np*10,x-wr-np") |
| 0 | 144 |
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145 (define_insn_reservation "x_stm" 1 |
| 0 | 146 (and (eq_attr "cpu" "z990,z9_109") |
| 147 (eq_attr "type" "stm")) | |
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148 "(x-e1-np+x_store_tok)*10,x-wr-np") |
| 0 | 149 |
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150 (define_insn_reservation "x_lm" 1 |
| 0 | 151 (and (eq_attr "cpu" "z990,z9_109") |
| 152 (eq_attr "type" "lm")) | |
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153 "x-e1-np*10,x-wr-np") |
| 0 | 154 |
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155 (define_insn_reservation "x_other" 1 |
| 0 | 156 (and (eq_attr "cpu" "z990,z9_109") |
| 157 (eq_attr "type" "other")) | |
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158 "x-e1-np,x-wr-np") |
| 0 | 159 |
| 160 ;; | |
| 161 ;; Floating point insns | |
| 162 ;; | |
| 163 | |
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164 (define_insn_reservation "x_fsimptf" 7 |
| 0 | 165 (and (eq_attr "cpu" "z990,z9_109") |
| 36 | 166 (eq_attr "type" "fsimptf,fhex")) |
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167 "x_e1_t*2,x-wr-fp") |
| 0 | 168 |
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169 (define_insn_reservation "x_fsimpdf" 6 |
| 0 | 170 (and (eq_attr "cpu" "z990,z9_109") |
| 36 | 171 (eq_attr "type" "fsimpdf,fmuldf,fhex")) |
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172 "x_e1_t,x-wr-fp") |
| 0 | 173 |
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174 (define_insn_reservation "x_fsimpsf" 6 |
| 0 | 175 (and (eq_attr "cpu" "z990,z9_109") |
| 36 | 176 (eq_attr "type" "fsimpsf,fmulsf,fhex")) |
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177 "x_e1_t,x-wr-fp") |
| 0 | 178 |
| 179 | |
| 180 (define_insn_reservation "x_fmultf" 33 | |
| 181 (and (eq_attr "cpu" "z990,z9_109") | |
| 182 (eq_attr "type" "fmultf")) | |
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183 "x_e1_t*27,x-wr-fp") |
| 0 | 184 |
| 185 | |
| 186 (define_insn_reservation "x_fdivtf" 82 | |
| 187 (and (eq_attr "cpu" "z990,z9_109") | |
| 188 (eq_attr "type" "fdivtf,fsqrttf")) | |
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189 "x_e1_t*76,x-wr-fp") |
| 0 | 190 |
| 191 (define_insn_reservation "x_fdivdf" 36 | |
| 192 (and (eq_attr "cpu" "z990,z9_109") | |
| 193 (eq_attr "type" "fdivdf,fsqrtdf")) | |
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194 "x_e1_t*30,x-wr-fp") |
| 0 | 195 |
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196 (define_insn_reservation "x_fdivsf" 36 |
| 0 | 197 (and (eq_attr "cpu" "z990,z9_109") |
| 198 (eq_attr "type" "fdivsf,fsqrtsf")) | |
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199 "x_e1_t*30,x-wr-fp") |
| 0 | 200 |
| 201 | |
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202 (define_insn_reservation "x_floadtf" 6 |
| 0 | 203 (and (eq_attr "cpu" "z990,z9_109") |
| 204 (eq_attr "type" "floadtf")) | |
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205 "x_e1_t,x-wr-fp") |
| 0 | 206 |
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207 (define_insn_reservation "x_floaddf" 6 |
| 0 | 208 (and (eq_attr "cpu" "z990,z9_109") |
| 209 (eq_attr "type" "floaddf")) | |
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210 "x_e1_t,x-wr-fp") |
| 0 | 211 |
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212 (define_insn_reservation "x_floadsf" 6 |
| 0 | 213 (and (eq_attr "cpu" "z990,z9_109") |
| 214 (eq_attr "type" "floadsf")) | |
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215 "x_e1_t,x-wr-fp") |
| 0 | 216 |
| 217 | |
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218 (define_insn_reservation "x_fstoredf" 1 |
| 0 | 219 (and (eq_attr "cpu" "z990,z9_109") |
| 220 (eq_attr "type" "fstoredf")) | |
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221 "x_e1_t,x-wr-fp") |
| 0 | 222 |
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223 (define_insn_reservation "x_fstoresf" 1 |
| 0 | 224 (and (eq_attr "cpu" "z990,z9_109") |
| 225 (eq_attr "type" "fstoresf")) | |
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226 "x_e1_t,x-wr-fp") |
| 0 | 227 |
| 228 | |
| 229 (define_insn_reservation "x_ftrunctf" 16 | |
| 230 (and (eq_attr "cpu" "z990,z9_109") | |
| 231 (eq_attr "type" "ftrunctf")) | |
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232 "x_e1_t*10,x-wr-fp") |
| 0 | 233 |
| 234 (define_insn_reservation "x_ftruncdf" 11 | |
| 235 (and (eq_attr "cpu" "z990,z9_109") | |
| 236 (eq_attr "type" "ftruncdf")) | |
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237 "x_e1_t*5,x-wr-fp") |
| 0 | 238 |
| 239 | |
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240 (define_insn_reservation "x_ftoi" 1 |
| 0 | 241 (and (eq_attr "cpu" "z990,z9_109") |
| 242 (eq_attr "type" "ftoi")) | |
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243 "x_e1_t*3,x-wr-fp") |
| 0 | 244 |
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245 (define_insn_reservation "x_itof" 7 |
| 0 | 246 (and (eq_attr "cpu" "z990,z9_109") |
| 247 (eq_attr "type" "itoftf,itofdf,itofsf")) | |
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248 "x_e1_t*3,x-wr-fp") |
| 0 | 249 |
| 250 (define_bypass 1 "x_fsimpdf" "x_fstoredf") | |
| 251 | |
| 252 (define_bypass 1 "x_fsimpsf" "x_fstoresf") | |
| 253 | |
| 254 (define_bypass 1 "x_floaddf" "x_fsimpdf,x_fstoredf,x_floaddf") | |
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255 |
| 0 | 256 (define_bypass 1 "x_floadsf" "x_fsimpsf,x_fstoresf,x_floadsf") |
| 257 | |
| 258 ;; | |
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259 ;; s390_agen_dep_p returns 1, if a register is set in the |
| 0 | 260 ;; first insn and used in the dependent insn to form a address. |
| 261 ;; | |
| 262 | |
| 263 ;; | |
| 264 ;; If an instruction uses a register to address memory, it needs | |
| 265 ;; to be set 5 cycles in advance. | |
|
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266 ;; |
| 0 | 267 |
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268 (define_bypass 5 "x_int,x_agen,x_lr" |
| 0 | 269 "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other" |
| 270 "s390_agen_dep_p") | |
| 271 | |
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272 (define_bypass 9 "x_int,x_agen,x_lr" |
| 0 | 273 "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\ |
| 274 x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf" | |
| 275 "s390_agen_dep_p") | |
| 276 ;; | |
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277 ;; A load type instruction uses a bypass to feed the result back |
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278 ;; to the address generation pipeline stage. |
| 0 | 279 ;; |
| 280 | |
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281 (define_bypass 4 "x_load" |
| 0 | 282 "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other" |
| 283 "s390_agen_dep_p") | |
| 284 | |
| 285 (define_bypass 5 "x_load" | |
| 286 "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\ | |
| 287 x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf" | |
| 288 "s390_agen_dep_p") | |
| 289 | |
| 290 ;; | |
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291 ;; A load address type instruction uses a bypass to feed the |
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292 ;; result back to the address generation pipeline stage. |
| 0 | 293 ;; |
| 294 | |
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295 (define_bypass 3 "x_larl,x_la" |
| 0 | 296 "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other" |
| 297 "s390_agen_dep_p") | |
| 298 | |
| 299 (define_bypass 5 "x_larl, x_la" | |
| 300 "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\ | |
| 301 x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf" | |
| 302 "s390_agen_dep_p") | |
| 303 | |
| 304 ;; | |
| 305 ;; Operand forwarding | |
| 306 ;; | |
| 307 | |
| 308 (define_bypass 0 "x_lr,x_la,x_load" "x_int,x_lr") | |
| 309 | |
| 310 |