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1 ;; Predicate definitions for NEC V850.
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2 ;; Copyright (C) 2005, 2007 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; Return true if OP is either a register or 0.
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21
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22 (define_predicate "reg_or_0_operand"
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23 (match_code "reg,subreg,const_int,const_double")
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24 {
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25 if (GET_CODE (op) == CONST_INT)
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26 return INTVAL (op) == 0;
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27
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28 else if (GET_CODE (op) == CONST_DOUBLE)
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29 return CONST_DOUBLE_OK_FOR_G (op);
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30
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31 else
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32 return register_operand (op, mode);
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33 })
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34
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35 ;; Return true if OP is either a register or a signed five bit
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36 ;; integer.
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37
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38 (define_predicate "reg_or_int5_operand"
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39 (match_code "reg,subreg,const_int")
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40 {
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41 if (GET_CODE (op) == CONST_INT)
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42 return CONST_OK_FOR_J (INTVAL (op));
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43
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44 else
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45 return register_operand (op, mode);
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46 })
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47
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48 ;; Return true if OP is either a register or a signed nine bit
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49 ;; integer.
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50
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51 (define_predicate "reg_or_int9_operand"
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52 (match_code "reg,subreg,const_int")
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53 {
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54 if (GET_CODE (op) == CONST_INT)
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55 return CONST_OK_FOR_O (INTVAL (op));
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56
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57 return register_operand (op, mode);
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58 })
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59
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60 ;; Return true if OP is either a register or a const integer.
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61
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62 (define_predicate "reg_or_const_operand"
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63 (match_code "reg,const_int")
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64 {
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65 if (GET_CODE (op) == CONST_INT)
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66 return TRUE;
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67
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68 return register_operand (op, mode);
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69 })
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70
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71 ;; Return true if OP is a valid call operand.
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72
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73 (define_predicate "call_address_operand"
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74 (match_code "reg,symbol_ref")
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75 {
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76 /* Only registers are valid call operands if TARGET_LONG_CALLS. */
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77 if (TARGET_LONG_CALLS)
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78 return GET_CODE (op) == REG;
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79 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
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80 })
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81
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82 ;; TODO: Add a comment here.
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83
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84 (define_predicate "movsi_source_operand"
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85 (match_code "label_ref,symbol_ref,const_int,const_double,const,high,mem,reg,subreg")
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86 {
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87 /* Some constants, as well as symbolic operands
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88 must be done with HIGH & LO_SUM patterns. */
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89 if (CONSTANT_P (op)
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90 && GET_CODE (op) != HIGH
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91 && !(GET_CODE (op) == CONST_INT
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92 && (CONST_OK_FOR_J (INTVAL (op))
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93 || CONST_OK_FOR_K (INTVAL (op))
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94 || CONST_OK_FOR_L (INTVAL (op)))))
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95 return special_symbolref_operand (op, mode);
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96 else
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97 return general_operand (op, mode);
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98 })
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99
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100 ;; TODO: Add a comment here.
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101
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102 (define_predicate "special_symbolref_operand"
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103 (match_code "symbol_ref")
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104 {
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105 if (GET_CODE (op) == CONST
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106 && GET_CODE (XEXP (op, 0)) == PLUS
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107 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
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108 && CONST_OK_FOR_K (INTVAL (XEXP (XEXP (op, 0), 1))))
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109 op = XEXP (XEXP (op, 0), 0);
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110
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111 if (GET_CODE (op) == SYMBOL_REF)
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112 return (SYMBOL_REF_FLAGS (op)
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113 & (SYMBOL_FLAG_ZDA | SYMBOL_FLAG_TDA | SYMBOL_FLAG_SDA)) != 0;
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114
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115 return FALSE;
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116 })
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117
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118 ;; TODO: Add a comment here.
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119
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120 (define_predicate "power_of_two_operand"
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121 (match_code "const_int")
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122 {
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123 if (GET_CODE (op) != CONST_INT)
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124 return 0;
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125
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126 if (exact_log2 (INTVAL (op)) == -1)
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127 return 0;
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128 return 1;
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129 })
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130
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131 ;; Return nonzero if the given RTX is suitable for collapsing into a
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132 ;; jump to a function prologue.
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133
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134 (define_predicate "pattern_is_ok_for_prologue"
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135 (match_code "parallel")
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136 {
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137 int count = XVECLEN (op, 0);
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138 int i;
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139 rtx vector_element;
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140
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141 /* If there are no registers to save then the function prologue
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142 is not suitable. */
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143 if (count <= 2)
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144 return 0;
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145
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146 /* The pattern matching has already established that we are adjusting the
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147 stack and pushing at least one register. We must now check that the
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148 remaining entries in the vector to make sure that they are also register
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149 pushes, except for the last entry which should be a CLOBBER of r10.
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150
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151 The test below performs the C equivalent of this machine description
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152 pattern match:
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153
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154 (set (mem:SI (plus:SI (reg:SI 3)
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155 (match_operand:SI 2 "immediate_operand" "i")))
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156 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))
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157
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158 */
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159
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160 for (i = 2; i < count - (TARGET_LONG_CALLS ? 2: 1); i++)
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161 {
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162 rtx dest;
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163 rtx src;
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164 rtx plus;
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165
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166 vector_element = XVECEXP (op, 0, i);
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167
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168 if (GET_CODE (vector_element) != SET)
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169 return 0;
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170
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171 dest = SET_DEST (vector_element);
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172 src = SET_SRC (vector_element);
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173
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174 if (GET_CODE (dest) != MEM
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175 || GET_MODE (dest) != SImode
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176 || GET_CODE (src) != REG
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177 || GET_MODE (src) != SImode
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178 || ! register_is_ok_for_epilogue (src, SImode))
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179 return 0;
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180
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181 plus = XEXP (dest, 0);
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182
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183 if ( GET_CODE (plus) != PLUS
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184 || GET_CODE (XEXP (plus, 0)) != REG
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185 || GET_MODE (XEXP (plus, 0)) != SImode
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186 || REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
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187 || GET_CODE (XEXP (plus, 1)) != CONST_INT)
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188 return 0;
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189
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190 /* If the register is being pushed somewhere other than the stack
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191 space just acquired by the first operand then abandon this quest.
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192 Note: the test is <= because both values are negative. */
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193 if (INTVAL (XEXP (plus, 1))
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194 <= INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)))
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195 {
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196 return 0;
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197 }
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198 }
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199
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200 /* Make sure that the last entries in the vector are clobbers. */
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201 for (; i < count; i++)
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202 {
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203 vector_element = XVECEXP (op, 0, i);
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204
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205 if (GET_CODE (vector_element) != CLOBBER
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206 || GET_CODE (XEXP (vector_element, 0)) != REG
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207 || !(REGNO (XEXP (vector_element, 0)) == 10
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208 || (TARGET_LONG_CALLS ? (REGNO (XEXP (vector_element, 0)) == 11) : 0 )))
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209 return 0;
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210 }
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211
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212 return 1;
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213 })
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214
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215 ;; Return nonzero if the given RTX is suitable for collapsing into
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216 ;; jump to a function epilogue.
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217
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218 (define_predicate "pattern_is_ok_for_epilogue"
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219 (match_code "parallel")
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220 {
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221 int count = XVECLEN (op, 0);
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222 int i;
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223
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224 /* If there are no registers to restore then the function epilogue
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225 is not suitable. */
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226 if (count <= 2)
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227 return 0;
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228
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229 /* The pattern matching has already established that we are performing a
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230 function epilogue and that we are popping at least one register. We must
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231 now check the remaining entries in the vector to make sure that they are
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232 also register pops. There is no good reason why there should ever be
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233 anything else in this vector, but being paranoid always helps...
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234
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235 The test below performs the C equivalent of this machine description
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236 pattern match:
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237
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238 (set (match_operand:SI n "register_is_ok_for_epilogue" "r")
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239 (mem:SI (plus:SI (reg:SI 3) (match_operand:SI n "immediate_operand" "i"))))
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240 */
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241
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242 for (i = 3; i < count; i++)
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243 {
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244 rtx vector_element = XVECEXP (op, 0, i);
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245 rtx dest;
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246 rtx src;
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247 rtx plus;
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248
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249 if (GET_CODE (vector_element) != SET)
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250 return 0;
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251
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252 dest = SET_DEST (vector_element);
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253 src = SET_SRC (vector_element);
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254
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255 if (GET_CODE (dest) != REG
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256 || GET_MODE (dest) != SImode
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257 || ! register_is_ok_for_epilogue (dest, SImode)
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258 || GET_CODE (src) != MEM
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259 || GET_MODE (src) != SImode)
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260 return 0;
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261
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262 plus = XEXP (src, 0);
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263
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264 if (GET_CODE (plus) != PLUS
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265 || GET_CODE (XEXP (plus, 0)) != REG
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266 || GET_MODE (XEXP (plus, 0)) != SImode
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267 || REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
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268 || GET_CODE (XEXP (plus, 1)) != CONST_INT)
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269 return 0;
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270 }
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271
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272 return 1;
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273 })
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274
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275 ;; Return true if the given RTX is a register which can be restored by
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276 ;; a function epilogue.
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277
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278 (define_predicate "register_is_ok_for_epilogue"
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279 (match_code "reg")
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280 {
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281 /* The save/restore routines can only cope with registers 20 - 31. */
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282 return ((GET_CODE (op) == REG)
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283 && (((REGNO (op) >= 20) && REGNO (op) <= 31)));
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284 })
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285
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286 ;; Return nonzero if the given RTX is suitable for collapsing into a
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287 ;; DISPOSE instruction.
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288
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289 (define_predicate "pattern_is_ok_for_dispose"
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290 (match_code "parallel")
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291 {
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292 int count = XVECLEN (op, 0);
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293 int i;
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294
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295 /* If there are no registers to restore then
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296 the dispose instruction is not suitable. */
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297 if (count <= 2)
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298 return 0;
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299
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300 /* The pattern matching has already established that we are performing a
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301 function epilogue and that we are popping at least one register. We must
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302 now check the remaining entries in the vector to make sure that they are
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303 also register pops. There is no good reason why there should ever be
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304 anything else in this vector, but being paranoid always helps...
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305
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306 The test below performs the C equivalent of this machine description
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307 pattern match:
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308
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309 (set (match_operand:SI n "register_is_ok_for_epilogue" "r")
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310 (mem:SI (plus:SI (reg:SI 3)
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311 (match_operand:SI n "immediate_operand" "i"))))
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312 */
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313
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314 for (i = 3; i < count; i++)
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315 {
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316 rtx vector_element = XVECEXP (op, 0, i);
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317 rtx dest;
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318 rtx src;
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319 rtx plus;
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320
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321 if (GET_CODE (vector_element) != SET)
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322 return 0;
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323
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324 dest = SET_DEST (vector_element);
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325 src = SET_SRC (vector_element);
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326
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327 if ( GET_CODE (dest) != REG
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328 || GET_MODE (dest) != SImode
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329 || ! register_is_ok_for_epilogue (dest, SImode)
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330 || GET_CODE (src) != MEM
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331 || GET_MODE (src) != SImode)
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332 return 0;
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333
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334 plus = XEXP (src, 0);
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335
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336 if ( GET_CODE (plus) != PLUS
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337 || GET_CODE (XEXP (plus, 0)) != REG
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338 || GET_MODE (XEXP (plus, 0)) != SImode
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339 || REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
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340 || GET_CODE (XEXP (plus, 1)) != CONST_INT)
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341 return 0;
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342 }
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343
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344 return 1;
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345 })
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346
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347 ;; Return nonzero if the given RTX is suitable for collapsing into a
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348 ;; PREPARE instruction.
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349
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350 (define_predicate "pattern_is_ok_for_prepare"
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351 (match_code "parallel")
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352 {
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353 int count = XVECLEN (op, 0);
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354 int i;
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355
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356 /* If there are no registers to restore then the prepare instruction
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357 is not suitable. */
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358 if (count <= 1)
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359 return 0;
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360
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361 /* The pattern matching has already established that we are adjusting the
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362 stack and pushing at least one register. We must now check that the
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363 remaining entries in the vector to make sure that they are also register
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364 pushes.
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365
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366 The test below performs the C equivalent of this machine description
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367 pattern match:
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368
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369 (set (mem:SI (plus:SI (reg:SI 3)
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370 (match_operand:SI 2 "immediate_operand" "i")))
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371 (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))
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372
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373 */
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374
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375 for (i = 2; i < count; i++)
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376 {
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377 rtx vector_element = XVECEXP (op, 0, i);
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378 rtx dest;
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379 rtx src;
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380 rtx plus;
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381
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382 if (GET_CODE (vector_element) != SET)
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383 return 0;
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384
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385 dest = SET_DEST (vector_element);
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386 src = SET_SRC (vector_element);
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387
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388 if ( GET_CODE (dest) != MEM
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389 || GET_MODE (dest) != SImode
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390 || GET_CODE (src) != REG
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391 || GET_MODE (src) != SImode
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392 || ! register_is_ok_for_epilogue (src, SImode)
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393 )
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394 return 0;
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395
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396 plus = XEXP (dest, 0);
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397
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398 if ( GET_CODE (plus) != PLUS
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399 || GET_CODE (XEXP (plus, 0)) != REG
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400 || GET_MODE (XEXP (plus, 0)) != SImode
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401 || REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
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402 || GET_CODE (XEXP (plus, 1)) != CONST_INT)
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403 return 0;
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404
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405 /* If the register is being pushed somewhere other than the stack
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406 space just acquired by the first operand then abandon this quest.
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407 Note: the test is <= because both values are negative. */
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408 if (INTVAL (XEXP (plus, 1))
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409 <= INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)))
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410 return 0;
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411 }
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412
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413 return 1;
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414 })
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415
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416 ;; TODO: Add a comment here.
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417
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418 (define_predicate "not_power_of_two_operand"
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419 (match_code "const_int")
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420 {
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421 unsigned int mask;
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422
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423 if (mode == QImode)
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424 mask = 0xff;
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425 else if (mode == HImode)
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426 mask = 0xffff;
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427 else if (mode == SImode)
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428 mask = 0xffffffff;
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429 else
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430 return 0;
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431
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432 if (GET_CODE (op) != CONST_INT)
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433 return 0;
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434
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435 if (exact_log2 (~INTVAL (op) & mask) == -1)
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436 return 0;
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437 return 1;
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438 })
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