Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/vax/vax.c @ 55:77e2b8dfacca gcc-4.4.5
update it from 4.4.3 to 4.5.0
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Fri, 12 Feb 2010 23:39:51 +0900 |
| parents | 58ad6c70ea60 |
| children | b7f97abdc517 |
| rev | line source |
|---|---|
| 0 | 1 /* Subroutines for insn-output.c for VAX. |
| 2 Copyright (C) 1987, 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, | |
|
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3 2004, 2005, 2006, 2007, 2008, 2009 |
| 0 | 4 Free Software Foundation, Inc. |
| 5 | |
| 6 This file is part of GCC. | |
| 7 | |
| 8 GCC is free software; you can redistribute it and/or modify | |
| 9 it under the terms of the GNU General Public License as published by | |
| 10 the Free Software Foundation; either version 3, or (at your option) | |
| 11 any later version. | |
| 12 | |
| 13 GCC is distributed in the hope that it will be useful, | |
| 14 but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 GNU General Public License for more details. | |
| 17 | |
| 18 You should have received a copy of the GNU General Public License | |
| 19 along with GCC; see the file COPYING3. If not see | |
| 20 <http://www.gnu.org/licenses/>. */ | |
| 21 | |
| 22 #include "config.h" | |
| 23 #include "system.h" | |
| 24 #include "coretypes.h" | |
| 25 #include "tm.h" | |
| 26 #include "rtl.h" | |
|
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27 #include "df.h" |
| 0 | 28 #include "tree.h" |
| 29 #include "regs.h" | |
| 30 #include "hard-reg-set.h" | |
| 31 #include "real.h" | |
| 32 #include "insn-config.h" | |
| 33 #include "conditions.h" | |
| 34 #include "function.h" | |
| 35 #include "output.h" | |
| 36 #include "insn-attr.h" | |
| 37 #include "recog.h" | |
| 38 #include "expr.h" | |
| 39 #include "optabs.h" | |
| 40 #include "flags.h" | |
| 41 #include "debug.h" | |
| 42 #include "toplev.h" | |
|
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43 #include "tm-preds.h" |
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44 #include "tm-constrs.h" |
| 0 | 45 #include "tm_p.h" |
| 46 #include "target.h" | |
| 47 #include "target-def.h" | |
| 48 | |
|
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49 static bool vax_legitimate_address_p (enum machine_mode, rtx, bool); |
| 0 | 50 static void vax_output_function_prologue (FILE *, HOST_WIDE_INT); |
| 51 static void vax_file_start (void); | |
| 52 static void vax_init_libfuncs (void); | |
| 53 static void vax_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, | |
| 54 HOST_WIDE_INT, tree); | |
| 55 static int vax_address_cost_1 (rtx); | |
| 56 static int vax_address_cost (rtx, bool); | |
| 57 static bool vax_rtx_costs (rtx, int, int, int *, bool); | |
| 58 static rtx vax_struct_value_rtx (tree, int); | |
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59 static rtx vax_builtin_setjmp_frame_value (void); |
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60 static void vax_asm_trampoline_template (FILE *); |
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61 static void vax_trampoline_init (rtx, tree, rtx); |
| 0 | 62 |
| 63 /* Initialize the GCC target structure. */ | |
| 64 #undef TARGET_ASM_ALIGNED_HI_OP | |
| 65 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
| 66 | |
| 67 #undef TARGET_ASM_FUNCTION_PROLOGUE | |
| 68 #define TARGET_ASM_FUNCTION_PROLOGUE vax_output_function_prologue | |
| 69 | |
| 70 #undef TARGET_ASM_FILE_START | |
| 71 #define TARGET_ASM_FILE_START vax_file_start | |
| 72 #undef TARGET_ASM_FILE_START_APP_OFF | |
| 73 #define TARGET_ASM_FILE_START_APP_OFF true | |
| 74 | |
| 75 #undef TARGET_INIT_LIBFUNCS | |
| 76 #define TARGET_INIT_LIBFUNCS vax_init_libfuncs | |
| 77 | |
| 78 #undef TARGET_ASM_OUTPUT_MI_THUNK | |
| 79 #define TARGET_ASM_OUTPUT_MI_THUNK vax_output_mi_thunk | |
| 80 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
| 81 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall | |
| 82 | |
| 83 #undef TARGET_DEFAULT_TARGET_FLAGS | |
| 84 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT | |
| 85 | |
| 86 #undef TARGET_RTX_COSTS | |
| 87 #define TARGET_RTX_COSTS vax_rtx_costs | |
| 88 #undef TARGET_ADDRESS_COST | |
| 89 #define TARGET_ADDRESS_COST vax_address_cost | |
| 90 | |
| 91 #undef TARGET_PROMOTE_PROTOTYPES | |
| 92 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true | |
| 93 | |
| 94 #undef TARGET_STRUCT_VALUE_RTX | |
| 95 #define TARGET_STRUCT_VALUE_RTX vax_struct_value_rtx | |
| 96 | |
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97 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE |
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98 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE vax_builtin_setjmp_frame_value |
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99 |
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100 #undef TARGET_LEGITIMATE_ADDRESS_P |
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101 #define TARGET_LEGITIMATE_ADDRESS_P vax_legitimate_address_p |
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102 |
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103 #undef TARGET_FRAME_POINTER_REQUIRED |
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104 #define TARGET_FRAME_POINTER_REQUIRED hook_bool_void_true |
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105 |
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106 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE |
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107 #define TARGET_ASM_TRAMPOLINE_TEMPLATE vax_asm_trampoline_template |
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108 #undef TARGET_TRAMPOLINE_INIT |
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109 #define TARGET_TRAMPOLINE_INIT vax_trampoline_init |
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110 |
| 0 | 111 struct gcc_target targetm = TARGET_INITIALIZER; |
| 112 | |
| 113 /* Set global variables as needed for the options enabled. */ | |
| 114 | |
| 115 void | |
| 116 override_options (void) | |
| 117 { | |
| 118 /* We're VAX floating point, not IEEE floating point. */ | |
| 119 if (TARGET_G_FLOAT) | |
| 120 REAL_MODE_FORMAT (DFmode) = &vax_g_format; | |
| 121 } | |
| 122 | |
| 123 /* Generate the assembly code for function entry. FILE is a stdio | |
| 124 stream to output the code to. SIZE is an int: how many units of | |
| 125 temporary storage to allocate. | |
| 126 | |
| 127 Refer to the array `regs_ever_live' to determine which registers to | |
| 128 save; `regs_ever_live[I]' is nonzero if register number I is ever | |
| 129 used in the function. This function is responsible for knowing | |
| 130 which registers should not be saved even if used. */ | |
| 131 | |
| 132 static void | |
| 133 vax_output_function_prologue (FILE * file, HOST_WIDE_INT size) | |
| 134 { | |
| 135 int regno; | |
| 136 int mask = 0; | |
| 137 | |
| 138 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
| 139 if (df_regs_ever_live_p (regno) && !call_used_regs[regno]) | |
| 140 mask |= 1 << regno; | |
| 141 | |
| 142 fprintf (file, "\t.word 0x%x\n", mask); | |
| 143 | |
| 144 if (dwarf2out_do_frame ()) | |
| 145 { | |
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146 const char *label = dwarf2out_cfi_label (false); |
| 0 | 147 int offset = 0; |
| 148 | |
| 149 for (regno = FIRST_PSEUDO_REGISTER-1; regno >= 0; --regno) | |
| 150 if (df_regs_ever_live_p (regno) && !call_used_regs[regno]) | |
| 151 dwarf2out_reg_save (label, regno, offset -= 4); | |
| 152 | |
| 153 dwarf2out_reg_save (label, PC_REGNUM, offset -= 4); | |
| 154 dwarf2out_reg_save (label, FRAME_POINTER_REGNUM, offset -= 4); | |
| 155 dwarf2out_reg_save (label, ARG_POINTER_REGNUM, offset -= 4); | |
| 156 dwarf2out_def_cfa (label, FRAME_POINTER_REGNUM, -(offset - 4)); | |
| 157 } | |
| 158 | |
| 159 size -= STARTING_FRAME_OFFSET; | |
| 160 if (size >= 64) | |
| 161 asm_fprintf (file, "\tmovab %wd(%Rsp),%Rsp\n", -size); | |
| 162 else if (size) | |
| 163 asm_fprintf (file, "\tsubl2 $%wd,%Rsp\n", size); | |
| 164 } | |
| 165 | |
| 166 /* When debugging with stabs, we want to output an extra dummy label | |
| 167 so that gas can distinguish between D_float and G_float prior to | |
| 168 processing the .stabs directive identifying type double. */ | |
| 169 static void | |
| 170 vax_file_start (void) | |
| 171 { | |
| 172 default_file_start (); | |
| 173 | |
| 174 if (write_symbols == DBX_DEBUG) | |
| 175 fprintf (asm_out_file, "___vax_%c_doubles:\n", ASM_DOUBLE_CHAR); | |
| 176 } | |
| 177 | |
| 178 /* We can use the BSD C library routines for the libgcc calls that are | |
| 179 still generated, since that's what they boil down to anyways. When | |
| 180 ELF, avoid the user's namespace. */ | |
| 181 | |
| 182 static void | |
| 183 vax_init_libfuncs (void) | |
| 184 { | |
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185 if (TARGET_BSD_DIVMOD) |
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186 { |
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187 set_optab_libfunc (udiv_optab, SImode, TARGET_ELF ? "*__udiv" : "*udiv"); |
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188 set_optab_libfunc (umod_optab, SImode, TARGET_ELF ? "*__urem" : "*urem"); |
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189 } |
| 0 | 190 } |
| 191 | |
| 192 /* This is like nonimmediate_operand with a restriction on the type of MEM. */ | |
| 193 | |
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194 static void |
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195 split_quadword_operands (rtx insn, enum rtx_code code, rtx * operands, |
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196 rtx * low, int n) |
| 0 | 197 { |
| 198 int i; | |
| 199 | |
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200 for (i = 0; i < n; i++) |
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201 low[i] = 0; |
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202 |
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203 for (i = 0; i < n; i++) |
| 0 | 204 { |
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205 if (MEM_P (operands[i]) |
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206 && (GET_CODE (XEXP (operands[i], 0)) == PRE_DEC |
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207 || GET_CODE (XEXP (operands[i], 0)) == POST_INC)) |
| 0 | 208 { |
| 209 rtx addr = XEXP (operands[i], 0); | |
| 210 operands[i] = low[i] = gen_rtx_MEM (SImode, addr); | |
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211 } |
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212 else if (optimize_size && MEM_P (operands[i]) |
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213 && REG_P (XEXP (operands[i], 0)) |
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214 && (code != MINUS || operands[1] != const0_rtx) |
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215 && find_regno_note (insn, REG_DEAD, |
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216 REGNO (XEXP (operands[i], 0)))) |
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217 { |
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218 low[i] = gen_rtx_MEM (SImode, |
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219 gen_rtx_POST_INC (Pmode, |
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220 XEXP (operands[i], 0))); |
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221 operands[i] = gen_rtx_MEM (SImode, XEXP (operands[i], 0)); |
| 0 | 222 } |
| 223 else | |
| 224 { | |
| 225 low[i] = operand_subword (operands[i], 0, 0, DImode); | |
| 226 operands[i] = operand_subword (operands[i], 1, 0, DImode); | |
| 227 } | |
| 228 } | |
| 229 } | |
| 230 | |
| 231 void | |
| 232 print_operand_address (FILE * file, rtx addr) | |
| 233 { | |
|
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234 rtx orig = addr; |
| 0 | 235 rtx reg1, breg, ireg; |
| 236 rtx offset; | |
| 237 | |
| 238 retry: | |
| 239 switch (GET_CODE (addr)) | |
| 240 { | |
| 241 case MEM: | |
| 242 fprintf (file, "*"); | |
| 243 addr = XEXP (addr, 0); | |
| 244 goto retry; | |
| 245 | |
| 246 case REG: | |
| 247 fprintf (file, "(%s)", reg_names[REGNO (addr)]); | |
| 248 break; | |
| 249 | |
| 250 case PRE_DEC: | |
| 251 fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); | |
| 252 break; | |
| 253 | |
| 254 case POST_INC: | |
| 255 fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); | |
| 256 break; | |
| 257 | |
| 258 case PLUS: | |
| 259 /* There can be either two or three things added here. One must be a | |
| 260 REG. One can be either a REG or a MULT of a REG and an appropriate | |
| 261 constant, and the third can only be a constant or a MEM. | |
| 262 | |
| 263 We get these two or three things and put the constant or MEM in | |
| 264 OFFSET, the MULT or REG in IREG, and the REG in BREG. If we have | |
| 265 a register and can't tell yet if it is a base or index register, | |
| 266 put it into REG1. */ | |
| 267 | |
| 268 reg1 = 0; ireg = 0; breg = 0; offset = 0; | |
| 269 | |
| 270 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)) | |
| 271 || MEM_P (XEXP (addr, 0))) | |
| 272 { | |
| 273 offset = XEXP (addr, 0); | |
| 274 addr = XEXP (addr, 1); | |
| 275 } | |
| 276 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)) | |
| 277 || MEM_P (XEXP (addr, 1))) | |
| 278 { | |
| 279 offset = XEXP (addr, 1); | |
| 280 addr = XEXP (addr, 0); | |
| 281 } | |
| 282 else if (GET_CODE (XEXP (addr, 1)) == MULT) | |
| 283 { | |
| 284 ireg = XEXP (addr, 1); | |
| 285 addr = XEXP (addr, 0); | |
| 286 } | |
| 287 else if (GET_CODE (XEXP (addr, 0)) == MULT) | |
| 288 { | |
| 289 ireg = XEXP (addr, 0); | |
| 290 addr = XEXP (addr, 1); | |
| 291 } | |
| 292 else if (REG_P (XEXP (addr, 1))) | |
| 293 { | |
| 294 reg1 = XEXP (addr, 1); | |
| 295 addr = XEXP (addr, 0); | |
| 296 } | |
| 297 else if (REG_P (XEXP (addr, 0))) | |
| 298 { | |
| 299 reg1 = XEXP (addr, 0); | |
| 300 addr = XEXP (addr, 1); | |
| 301 } | |
| 302 else | |
| 303 gcc_unreachable (); | |
| 304 | |
| 305 if (REG_P (addr)) | |
| 306 { | |
| 307 if (reg1) | |
| 308 ireg = addr; | |
| 309 else | |
| 310 reg1 = addr; | |
| 311 } | |
| 312 else if (GET_CODE (addr) == MULT) | |
| 313 ireg = addr; | |
| 314 else | |
| 315 { | |
| 316 gcc_assert (GET_CODE (addr) == PLUS); | |
| 317 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)) | |
| 318 || MEM_P (XEXP (addr, 0))) | |
| 319 { | |
| 320 if (offset) | |
| 321 { | |
| 322 if (CONST_INT_P (offset)) | |
| 323 offset = plus_constant (XEXP (addr, 0), INTVAL (offset)); | |
| 324 else | |
| 325 { | |
| 326 gcc_assert (CONST_INT_P (XEXP (addr, 0))); | |
| 327 offset = plus_constant (offset, INTVAL (XEXP (addr, 0))); | |
| 328 } | |
| 329 } | |
| 330 offset = XEXP (addr, 0); | |
| 331 } | |
| 332 else if (REG_P (XEXP (addr, 0))) | |
| 333 { | |
| 334 if (reg1) | |
| 335 ireg = reg1, breg = XEXP (addr, 0), reg1 = 0; | |
| 336 else | |
| 337 reg1 = XEXP (addr, 0); | |
| 338 } | |
| 339 else | |
| 340 { | |
| 341 gcc_assert (GET_CODE (XEXP (addr, 0)) == MULT); | |
| 342 gcc_assert (!ireg); | |
| 343 ireg = XEXP (addr, 0); | |
| 344 } | |
| 345 | |
| 346 if (CONSTANT_ADDRESS_P (XEXP (addr, 1)) | |
| 347 || MEM_P (XEXP (addr, 1))) | |
| 348 { | |
| 349 if (offset) | |
| 350 { | |
| 351 if (CONST_INT_P (offset)) | |
| 352 offset = plus_constant (XEXP (addr, 1), INTVAL (offset)); | |
| 353 else | |
| 354 { | |
| 355 gcc_assert (CONST_INT_P (XEXP (addr, 1))); | |
| 356 offset = plus_constant (offset, INTVAL (XEXP (addr, 1))); | |
| 357 } | |
| 358 } | |
| 359 offset = XEXP (addr, 1); | |
| 360 } | |
| 361 else if (REG_P (XEXP (addr, 1))) | |
| 362 { | |
| 363 if (reg1) | |
| 364 ireg = reg1, breg = XEXP (addr, 1), reg1 = 0; | |
| 365 else | |
| 366 reg1 = XEXP (addr, 1); | |
| 367 } | |
| 368 else | |
| 369 { | |
| 370 gcc_assert (GET_CODE (XEXP (addr, 1)) == MULT); | |
| 371 gcc_assert (!ireg); | |
| 372 ireg = XEXP (addr, 1); | |
| 373 } | |
| 374 } | |
| 375 | |
| 376 /* If REG1 is nonzero, figure out if it is a base or index register. */ | |
| 377 if (reg1) | |
| 378 { | |
|
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379 if (breg |
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380 || (flag_pic && GET_CODE (addr) == SYMBOL_REF) |
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381 || (offset |
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382 && (MEM_P (offset) |
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383 || (flag_pic && symbolic_operand (offset, SImode))))) |
| 0 | 384 { |
| 385 gcc_assert (!ireg); | |
| 386 ireg = reg1; | |
| 387 } | |
| 388 else | |
| 389 breg = reg1; | |
| 390 } | |
| 391 | |
| 392 if (offset != 0) | |
|
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393 { |
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394 if (flag_pic && symbolic_operand (offset, SImode)) |
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395 { |
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396 if (breg && ireg) |
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397 { |
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398 debug_rtx (orig); |
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399 output_operand_lossage ("symbol used with both base and indexed registers"); |
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400 } |
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401 |
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402 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS |
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403 if (flag_pic > 1 && GET_CODE (offset) == CONST |
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404 && GET_CODE (XEXP (XEXP (offset, 0), 0)) == SYMBOL_REF |
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405 && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (offset, 0), 0))) |
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406 { |
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407 debug_rtx (orig); |
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408 output_operand_lossage ("symbol with offset used in PIC mode"); |
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409 } |
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410 #endif |
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411 |
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412 /* symbol(reg) isn't PIC, but symbol[reg] is. */ |
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413 if (breg) |
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414 { |
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415 ireg = breg; |
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416 breg = 0; |
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417 } |
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418 |
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419 } |
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420 |
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421 output_address (offset); |
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422 } |
| 0 | 423 |
| 424 if (breg != 0) | |
| 425 fprintf (file, "(%s)", reg_names[REGNO (breg)]); | |
| 426 | |
| 427 if (ireg != 0) | |
| 428 { | |
| 429 if (GET_CODE (ireg) == MULT) | |
| 430 ireg = XEXP (ireg, 0); | |
| 431 gcc_assert (REG_P (ireg)); | |
| 432 fprintf (file, "[%s]", reg_names[REGNO (ireg)]); | |
| 433 } | |
| 434 break; | |
| 435 | |
| 436 default: | |
| 437 output_addr_const (file, addr); | |
| 438 } | |
| 439 } | |
|
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440 |
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441 void |
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442 print_operand (FILE *file, rtx x, int code) |
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443 { |
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444 if (code == '#') |
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445 fputc (ASM_DOUBLE_CHAR, file); |
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446 else if (code == '|') |
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447 fputs (REGISTER_PREFIX, file); |
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448 else if (code == 'c') |
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449 fputs (cond_name (x), file); |
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450 else if (code == 'C') |
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451 fputs (rev_cond_name (x), file); |
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452 else if (code == 'D' && CONST_INT_P (x) && INTVAL (x) < 0) |
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453 fprintf (file, "$" NEG_HWI_PRINT_HEX16, INTVAL (x)); |
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454 else if (code == 'P' && CONST_INT_P (x)) |
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455 fprintf (file, "$" HOST_WIDE_INT_PRINT_DEC, INTVAL (x) + 1); |
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456 else if (code == 'N' && CONST_INT_P (x)) |
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457 fprintf (file, "$" HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x)); |
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458 /* rotl instruction cannot deal with negative arguments. */ |
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459 else if (code == 'R' && CONST_INT_P (x)) |
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460 fprintf (file, "$" HOST_WIDE_INT_PRINT_DEC, 32 - INTVAL (x)); |
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461 else if (code == 'H' && CONST_INT_P (x)) |
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462 fprintf (file, "$%d", (int) (0xffff & ~ INTVAL (x))); |
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463 else if (code == 'h' && CONST_INT_P (x)) |
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464 fprintf (file, "$%d", (short) - INTVAL (x)); |
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465 else if (code == 'B' && CONST_INT_P (x)) |
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466 fprintf (file, "$%d", (int) (0xff & ~ INTVAL (x))); |
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467 else if (code == 'b' && CONST_INT_P (x)) |
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468 fprintf (file, "$%d", (int) (0xff & - INTVAL (x))); |
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469 else if (code == 'M' && CONST_INT_P (x)) |
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470 fprintf (file, "$%d", ~((1 << INTVAL (x)) - 1)); |
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471 else if (REG_P (x)) |
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472 fprintf (file, "%s", reg_names[REGNO (x)]); |
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473 else if (MEM_P (x)) |
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474 output_address (XEXP (x, 0)); |
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475 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) |
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476 { |
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477 char dstr[30]; |
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478 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), |
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479 sizeof (dstr), 0, 1); |
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480 fprintf (file, "$0f%s", dstr); |
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481 } |
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482 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) |
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483 { |
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484 char dstr[30]; |
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485 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), |
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486 sizeof (dstr), 0, 1); |
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487 fprintf (file, "$0%c%s", ASM_DOUBLE_CHAR, dstr); |
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488 } |
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489 else |
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490 { |
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491 if (flag_pic > 1 && symbolic_operand (x, SImode)) |
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492 { |
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493 debug_rtx (x); |
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494 output_operand_lossage ("symbol used as immediate operand"); |
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495 } |
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496 putc ('$', file); |
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497 output_addr_const (file, x); |
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498 } |
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499 } |
| 0 | 500 |
| 501 const char * | |
|
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502 cond_name (rtx op) |
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503 { |
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504 switch (GET_CODE (op)) |
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505 { |
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506 case NE: |
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507 return "neq"; |
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508 case EQ: |
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509 return "eql"; |
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510 case GE: |
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511 return "geq"; |
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512 case GT: |
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513 return "gtr"; |
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514 case LE: |
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515 return "leq"; |
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516 case LT: |
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517 return "lss"; |
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518 case GEU: |
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519 return "gequ"; |
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520 case GTU: |
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521 return "gtru"; |
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522 case LEU: |
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523 return "lequ"; |
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524 case LTU: |
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525 return "lssu"; |
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526 |
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527 default: |
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528 gcc_unreachable (); |
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529 } |
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530 } |
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531 |
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532 const char * |
| 0 | 533 rev_cond_name (rtx op) |
| 534 { | |
| 535 switch (GET_CODE (op)) | |
| 536 { | |
| 537 case EQ: | |
| 538 return "neq"; | |
| 539 case NE: | |
| 540 return "eql"; | |
| 541 case LT: | |
| 542 return "geq"; | |
| 543 case LE: | |
| 544 return "gtr"; | |
| 545 case GT: | |
| 546 return "leq"; | |
| 547 case GE: | |
| 548 return "lss"; | |
| 549 case LTU: | |
| 550 return "gequ"; | |
| 551 case LEU: | |
| 552 return "gtru"; | |
| 553 case GTU: | |
| 554 return "lequ"; | |
| 555 case GEU: | |
| 556 return "lssu"; | |
| 557 | |
| 558 default: | |
| 559 gcc_unreachable (); | |
| 560 } | |
| 561 } | |
| 562 | |
|
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563 static bool |
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564 vax_float_literal (rtx c) |
| 0 | 565 { |
| 566 enum machine_mode mode; | |
| 567 REAL_VALUE_TYPE r, s; | |
| 568 int i; | |
| 569 | |
| 570 if (GET_CODE (c) != CONST_DOUBLE) | |
|
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571 return false; |
| 0 | 572 |
| 573 mode = GET_MODE (c); | |
| 574 | |
| 575 if (c == const_tiny_rtx[(int) mode][0] | |
| 576 || c == const_tiny_rtx[(int) mode][1] | |
| 577 || c == const_tiny_rtx[(int) mode][2]) | |
|
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578 return true; |
| 0 | 579 |
| 580 REAL_VALUE_FROM_CONST_DOUBLE (r, c); | |
| 581 | |
| 582 for (i = 0; i < 7; i++) | |
| 583 { | |
| 584 int x = 1 << i; | |
| 585 bool ok; | |
| 586 REAL_VALUE_FROM_INT (s, x, 0, mode); | |
| 587 | |
| 588 if (REAL_VALUES_EQUAL (r, s)) | |
|
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589 return true; |
| 0 | 590 ok = exact_real_inverse (mode, &s); |
| 591 gcc_assert (ok); | |
| 592 if (REAL_VALUES_EQUAL (r, s)) | |
|
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593 return true; |
| 0 | 594 } |
|
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595 return false; |
| 0 | 596 } |
| 597 | |
| 598 | |
| 599 /* Return the cost in cycles of a memory address, relative to register | |
| 600 indirect. | |
| 601 | |
| 602 Each of the following adds the indicated number of cycles: | |
| 603 | |
| 604 1 - symbolic address | |
| 605 1 - pre-decrement | |
| 606 1 - indexing and/or offset(register) | |
| 607 2 - indirect */ | |
| 608 | |
| 609 | |
| 610 static int | |
| 611 vax_address_cost_1 (rtx addr) | |
| 612 { | |
| 613 int reg = 0, indexed = 0, indir = 0, offset = 0, predec = 0; | |
| 614 rtx plus_op0 = 0, plus_op1 = 0; | |
| 615 restart: | |
| 616 switch (GET_CODE (addr)) | |
| 617 { | |
| 618 case PRE_DEC: | |
| 619 predec = 1; | |
| 620 case REG: | |
| 621 case SUBREG: | |
| 622 case POST_INC: | |
| 623 reg = 1; | |
| 624 break; | |
| 625 case MULT: | |
| 626 indexed = 1; /* 2 on VAX 2 */ | |
| 627 break; | |
| 628 case CONST_INT: | |
| 629 /* byte offsets cost nothing (on a VAX 2, they cost 1 cycle) */ | |
| 630 if (offset == 0) | |
| 631 offset = (unsigned HOST_WIDE_INT)(INTVAL(addr)+128) > 256; | |
| 632 break; | |
| 633 case CONST: | |
| 634 case SYMBOL_REF: | |
| 635 offset = 1; /* 2 on VAX 2 */ | |
| 636 break; | |
| 637 case LABEL_REF: /* this is probably a byte offset from the pc */ | |
| 638 if (offset == 0) | |
| 639 offset = 1; | |
| 640 break; | |
| 641 case PLUS: | |
| 642 if (plus_op0) | |
| 643 plus_op1 = XEXP (addr, 0); | |
| 644 else | |
| 645 plus_op0 = XEXP (addr, 0); | |
| 646 addr = XEXP (addr, 1); | |
| 647 goto restart; | |
| 648 case MEM: | |
| 649 indir = 2; /* 3 on VAX 2 */ | |
| 650 addr = XEXP (addr, 0); | |
| 651 goto restart; | |
| 652 default: | |
| 653 break; | |
| 654 } | |
| 655 | |
| 656 /* Up to 3 things can be added in an address. They are stored in | |
| 657 plus_op0, plus_op1, and addr. */ | |
| 658 | |
| 659 if (plus_op0) | |
| 660 { | |
| 661 addr = plus_op0; | |
| 662 plus_op0 = 0; | |
| 663 goto restart; | |
| 664 } | |
| 665 if (plus_op1) | |
| 666 { | |
| 667 addr = plus_op1; | |
| 668 plus_op1 = 0; | |
| 669 goto restart; | |
| 670 } | |
| 671 /* Indexing and register+offset can both be used (except on a VAX 2) | |
| 672 without increasing execution time over either one alone. */ | |
| 673 if (reg && indexed && offset) | |
| 674 return reg + indir + offset + predec; | |
| 675 return reg + indexed + indir + offset + predec; | |
| 676 } | |
| 677 | |
| 678 static int | |
| 679 vax_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED) | |
| 680 { | |
| 681 return (1 + (REG_P (x) ? 0 : vax_address_cost_1 (x))); | |
| 682 } | |
| 683 | |
| 684 /* Cost of an expression on a VAX. This version has costs tuned for the | |
| 685 CVAX chip (found in the VAX 3 series) with comments for variations on | |
| 686 other models. | |
| 687 | |
| 688 FIXME: The costs need review, particularly for TRUNCATE, FLOAT_EXTEND | |
| 689 and FLOAT_TRUNCATE. We need a -mcpu option to allow provision of | |
| 690 costs on a per cpu basis. */ | |
| 691 | |
| 692 static bool | |
| 693 vax_rtx_costs (rtx x, int code, int outer_code, int *total, | |
| 694 bool speed ATTRIBUTE_UNUSED) | |
| 695 { | |
| 696 enum machine_mode mode = GET_MODE (x); | |
| 697 int i = 0; /* may be modified in switch */ | |
| 698 const char *fmt = GET_RTX_FORMAT (code); /* may be modified in switch */ | |
| 699 | |
| 700 switch (code) | |
| 701 { | |
| 702 /* On a VAX, constants from 0..63 are cheap because they can use the | |
| 703 1 byte literal constant format. Compare to -1 should be made cheap | |
| 704 so that decrement-and-branch insns can be formed more easily (if | |
| 705 the value -1 is copied to a register some decrement-and-branch | |
| 706 patterns will not match). */ | |
| 707 case CONST_INT: | |
| 708 if (INTVAL (x) == 0) | |
|
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709 { |
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710 *total = 0; |
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711 return true; |
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712 } |
| 0 | 713 if (outer_code == AND) |
| 714 { | |
|
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715 *total = ((unsigned HOST_WIDE_INT) ~INTVAL (x) <= 077) ? 1 : 2; |
| 0 | 716 return true; |
| 717 } | |
| 718 if ((unsigned HOST_WIDE_INT) INTVAL (x) <= 077 | |
| 719 || (outer_code == COMPARE | |
| 720 && INTVAL (x) == -1) | |
| 721 || ((outer_code == PLUS || outer_code == MINUS) | |
| 722 && (unsigned HOST_WIDE_INT) -INTVAL (x) <= 077)) | |
| 723 { | |
| 724 *total = 1; | |
| 725 return true; | |
| 726 } | |
| 727 /* FALLTHRU */ | |
| 728 | |
| 729 case CONST: | |
| 730 case LABEL_REF: | |
| 731 case SYMBOL_REF: | |
| 732 *total = 3; | |
| 733 return true; | |
| 734 | |
| 735 case CONST_DOUBLE: | |
| 736 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) | |
| 737 *total = vax_float_literal (x) ? 5 : 8; | |
| 738 else | |
|
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739 *total = ((CONST_DOUBLE_HIGH (x) == 0 |
| 0 | 740 && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (x) < 64) |
| 741 || (outer_code == PLUS | |
| 742 && CONST_DOUBLE_HIGH (x) == -1 | |
| 743 && (unsigned HOST_WIDE_INT)-CONST_DOUBLE_LOW (x) < 64)) | |
| 744 ? 2 : 5; | |
| 745 return true; | |
| 746 | |
| 747 case POST_INC: | |
| 748 *total = 2; | |
| 749 return true; /* Implies register operand. */ | |
| 750 | |
| 751 case PRE_DEC: | |
| 752 *total = 3; | |
| 753 return true; /* Implies register operand. */ | |
| 754 | |
| 755 case MULT: | |
| 756 switch (mode) | |
| 757 { | |
| 758 case DFmode: | |
| 759 *total = 16; /* 4 on VAX 9000 */ | |
| 760 break; | |
| 761 case SFmode: | |
| 762 *total = 9; /* 4 on VAX 9000, 12 on VAX 2 */ | |
| 763 break; | |
| 764 case DImode: | |
| 765 *total = 16; /* 6 on VAX 9000, 28 on VAX 2 */ | |
| 766 break; | |
| 767 case SImode: | |
| 768 case HImode: | |
| 769 case QImode: | |
| 770 *total = 10; /* 3-4 on VAX 9000, 20-28 on VAX 2 */ | |
| 771 break; | |
| 772 default: | |
| 773 *total = MAX_COST; /* Mode is not supported. */ | |
| 774 return true; | |
| 775 } | |
| 776 break; | |
| 777 | |
| 778 case UDIV: | |
| 779 if (mode != SImode) | |
| 780 { | |
| 781 *total = MAX_COST; /* Mode is not supported. */ | |
| 782 return true; | |
| 783 } | |
| 784 *total = 17; | |
| 785 break; | |
| 786 | |
| 787 case DIV: | |
| 788 if (mode == DImode) | |
| 789 *total = 30; /* Highly variable. */ | |
| 790 else if (mode == DFmode) | |
| 791 /* divide takes 28 cycles if the result is not zero, 13 otherwise */ | |
| 792 *total = 24; | |
| 793 else | |
| 794 *total = 11; /* 25 on VAX 2 */ | |
| 795 break; | |
| 796 | |
| 797 case MOD: | |
| 798 *total = 23; | |
| 799 break; | |
| 800 | |
| 801 case UMOD: | |
| 802 if (mode != SImode) | |
| 803 { | |
| 804 *total = MAX_COST; /* Mode is not supported. */ | |
| 805 return true; | |
| 806 } | |
| 807 *total = 29; | |
| 808 break; | |
| 809 | |
| 810 case FLOAT: | |
| 811 *total = (6 /* 4 on VAX 9000 */ | |
| 812 + (mode == DFmode) + (GET_MODE (XEXP (x, 0)) != SImode)); | |
| 813 break; | |
| 814 | |
| 815 case FIX: | |
| 816 *total = 7; /* 17 on VAX 2 */ | |
| 817 break; | |
| 818 | |
| 819 case ASHIFT: | |
| 820 case LSHIFTRT: | |
| 821 case ASHIFTRT: | |
| 822 if (mode == DImode) | |
| 823 *total = 12; | |
| 824 else | |
| 825 *total = 10; /* 6 on VAX 9000 */ | |
| 826 break; | |
| 827 | |
| 828 case ROTATE: | |
| 829 case ROTATERT: | |
| 830 *total = 6; /* 5 on VAX 2, 4 on VAX 9000 */ | |
| 831 if (CONST_INT_P (XEXP (x, 1))) | |
| 832 fmt = "e"; /* all constant rotate counts are short */ | |
| 833 break; | |
| 834 | |
| 835 case PLUS: | |
| 836 case MINUS: | |
| 837 *total = (mode == DFmode) ? 13 : 8; /* 6/8 on VAX 9000, 16/15 on VAX 2 */ | |
| 838 /* Small integer operands can use subl2 and addl2. */ | |
| 839 if ((CONST_INT_P (XEXP (x, 1))) | |
| 840 && (unsigned HOST_WIDE_INT)(INTVAL (XEXP (x, 1)) + 63) < 127) | |
| 841 fmt = "e"; | |
| 842 break; | |
| 843 | |
| 844 case IOR: | |
| 845 case XOR: | |
| 846 *total = 3; | |
| 847 break; | |
| 848 | |
| 849 case AND: | |
| 850 /* AND is special because the first operand is complemented. */ | |
| 851 *total = 3; | |
| 852 if (CONST_INT_P (XEXP (x, 0))) | |
| 853 { | |
| 854 if ((unsigned HOST_WIDE_INT)~INTVAL (XEXP (x, 0)) > 63) | |
| 855 *total = 4; | |
| 856 fmt = "e"; | |
| 857 i = 1; | |
| 858 } | |
| 859 break; | |
| 860 | |
| 861 case NEG: | |
| 862 if (mode == DFmode) | |
| 863 *total = 9; | |
| 864 else if (mode == SFmode) | |
| 865 *total = 6; | |
| 866 else if (mode == DImode) | |
| 867 *total = 4; | |
| 868 else | |
| 869 *total = 2; | |
| 870 break; | |
| 871 | |
| 872 case NOT: | |
| 873 *total = 2; | |
| 874 break; | |
| 875 | |
| 876 case ZERO_EXTRACT: | |
| 877 case SIGN_EXTRACT: | |
| 878 *total = 15; | |
| 879 break; | |
| 880 | |
| 881 case MEM: | |
| 882 if (mode == DImode || mode == DFmode) | |
| 883 *total = 5; /* 7 on VAX 2 */ | |
| 884 else | |
| 885 *total = 3; /* 4 on VAX 2 */ | |
| 886 x = XEXP (x, 0); | |
| 887 if (!REG_P (x) && GET_CODE (x) != POST_INC) | |
| 888 *total += vax_address_cost_1 (x); | |
| 889 return true; | |
| 890 | |
| 891 case FLOAT_EXTEND: | |
| 892 case FLOAT_TRUNCATE: | |
| 893 case TRUNCATE: | |
| 894 *total = 3; /* FIXME: Costs need to be checked */ | |
| 895 break; | |
| 896 | |
| 897 default: | |
| 898 return false; | |
| 899 } | |
| 900 | |
| 901 /* Now look inside the expression. Operands which are not registers or | |
| 902 short constants add to the cost. | |
| 903 | |
| 904 FMT and I may have been adjusted in the switch above for instructions | |
| 905 which require special handling. */ | |
| 906 | |
| 907 while (*fmt++ == 'e') | |
| 908 { | |
| 909 rtx op = XEXP (x, i); | |
| 910 | |
| 911 i += 1; | |
| 912 code = GET_CODE (op); | |
| 913 | |
| 914 /* A NOT is likely to be found as the first operand of an AND | |
| 915 (in which case the relevant cost is of the operand inside | |
| 916 the not) and not likely to be found anywhere else. */ | |
| 917 if (code == NOT) | |
| 918 op = XEXP (op, 0), code = GET_CODE (op); | |
| 919 | |
| 920 switch (code) | |
| 921 { | |
| 922 case CONST_INT: | |
| 923 if ((unsigned HOST_WIDE_INT)INTVAL (op) > 63 | |
| 924 && GET_MODE (x) != QImode) | |
| 925 *total += 1; /* 2 on VAX 2 */ | |
| 926 break; | |
| 927 case CONST: | |
| 928 case LABEL_REF: | |
| 929 case SYMBOL_REF: | |
| 930 *total += 1; /* 2 on VAX 2 */ | |
| 931 break; | |
| 932 case CONST_DOUBLE: | |
| 933 if (GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT) | |
| 934 { | |
| 935 /* Registers are faster than floating point constants -- even | |
| 936 those constants which can be encoded in a single byte. */ | |
| 937 if (vax_float_literal (op)) | |
| 938 *total += 1; | |
| 939 else | |
| 940 *total += (GET_MODE (x) == DFmode) ? 3 : 2; | |
| 941 } | |
| 942 else | |
| 943 { | |
| 944 if (CONST_DOUBLE_HIGH (op) != 0 | |
|
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945 || (unsigned HOST_WIDE_INT)CONST_DOUBLE_LOW (op) > 63) |
| 0 | 946 *total += 2; |
| 947 } | |
| 948 break; | |
| 949 case MEM: | |
| 950 *total += 1; /* 2 on VAX 2 */ | |
| 951 if (!REG_P (XEXP (op, 0))) | |
| 952 *total += vax_address_cost_1 (XEXP (op, 0)); | |
| 953 break; | |
| 954 case REG: | |
| 955 case SUBREG: | |
| 956 break; | |
| 957 default: | |
| 958 *total += 1; | |
| 959 break; | |
| 960 } | |
| 961 } | |
| 962 return true; | |
| 963 } | |
| 964 | |
| 965 /* Output code to add DELTA to the first argument, and then jump to FUNCTION. | |
| 966 Used for C++ multiple inheritance. | |
| 967 .mask ^m<r2,r3,r4,r5,r6,r7,r8,r9,r10,r11> #conservative entry mask | |
| 968 addl2 $DELTA, 4(ap) #adjust first argument | |
| 969 jmp FUNCTION+2 #jump beyond FUNCTION's entry mask | |
| 970 */ | |
| 971 | |
| 972 static void | |
| 973 vax_output_mi_thunk (FILE * file, | |
|
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974 tree thunk ATTRIBUTE_UNUSED, |
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975 HOST_WIDE_INT delta, |
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976 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, |
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977 tree function) |
| 0 | 978 { |
| 979 fprintf (file, "\t.word 0x0ffc\n\taddl2 $" HOST_WIDE_INT_PRINT_DEC, delta); | |
| 980 asm_fprintf (file, ",4(%Rap)\n"); | |
| 981 fprintf (file, "\tjmp "); | |
| 982 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); | |
| 983 fprintf (file, "+2\n"); | |
| 984 } | |
| 985 | |
| 986 static rtx | |
| 987 vax_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, | |
| 988 int incoming ATTRIBUTE_UNUSED) | |
| 989 { | |
| 990 return gen_rtx_REG (Pmode, VAX_STRUCT_VALUE_REGNUM); | |
| 991 } | |
| 992 | |
|
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993 static rtx |
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994 vax_builtin_setjmp_frame_value (void) |
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995 { |
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996 return hard_frame_pointer_rtx; |
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997 } |
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998 |
| 0 | 999 /* Worker function for NOTICE_UPDATE_CC. */ |
| 1000 | |
| 1001 void | |
| 1002 vax_notice_update_cc (rtx exp, rtx insn ATTRIBUTE_UNUSED) | |
| 1003 { | |
| 1004 if (GET_CODE (exp) == SET) | |
| 1005 { | |
| 1006 if (GET_CODE (SET_SRC (exp)) == CALL) | |
| 1007 CC_STATUS_INIT; | |
| 1008 else if (GET_CODE (SET_DEST (exp)) != ZERO_EXTRACT | |
| 1009 && GET_CODE (SET_DEST (exp)) != PC) | |
| 1010 { | |
| 1011 cc_status.flags = 0; | |
| 1012 /* The integer operations below don't set carry or | |
| 1013 set it in an incompatible way. That's ok though | |
| 1014 as the Z bit is all we need when doing unsigned | |
| 1015 comparisons on the result of these insns (since | |
| 1016 they're always with 0). Set CC_NO_OVERFLOW to | |
| 1017 generate the correct unsigned branches. */ | |
| 1018 switch (GET_CODE (SET_SRC (exp))) | |
| 1019 { | |
| 1020 case NEG: | |
| 1021 if (GET_MODE_CLASS (GET_MODE (exp)) == MODE_FLOAT) | |
| 1022 break; | |
| 1023 case AND: | |
| 1024 case IOR: | |
| 1025 case XOR: | |
| 1026 case NOT: | |
| 1027 case MEM: | |
| 1028 case REG: | |
| 1029 cc_status.flags = CC_NO_OVERFLOW; | |
| 1030 break; | |
| 1031 default: | |
| 1032 break; | |
| 1033 } | |
| 1034 cc_status.value1 = SET_DEST (exp); | |
| 1035 cc_status.value2 = SET_SRC (exp); | |
| 1036 } | |
| 1037 } | |
| 1038 else if (GET_CODE (exp) == PARALLEL | |
| 1039 && GET_CODE (XVECEXP (exp, 0, 0)) == SET) | |
| 1040 { | |
| 1041 if (GET_CODE (SET_SRC (XVECEXP (exp, 0, 0))) == CALL) | |
| 1042 CC_STATUS_INIT; | |
| 1043 else if (GET_CODE (SET_DEST (XVECEXP (exp, 0, 0))) != PC) | |
| 1044 { | |
| 1045 cc_status.flags = 0; | |
| 1046 cc_status.value1 = SET_DEST (XVECEXP (exp, 0, 0)); | |
| 1047 cc_status.value2 = SET_SRC (XVECEXP (exp, 0, 0)); | |
| 1048 } | |
| 1049 else | |
| 1050 /* PARALLELs whose first element sets the PC are aob, | |
| 1051 sob insns. They do change the cc's. */ | |
| 1052 CC_STATUS_INIT; | |
| 1053 } | |
| 1054 else | |
| 1055 CC_STATUS_INIT; | |
| 1056 if (cc_status.value1 && REG_P (cc_status.value1) | |
| 1057 && cc_status.value2 | |
| 1058 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) | |
| 1059 cc_status.value2 = 0; | |
| 1060 if (cc_status.value1 && MEM_P (cc_status.value1) | |
| 1061 && cc_status.value2 | |
| 1062 && MEM_P (cc_status.value2)) | |
| 1063 cc_status.value2 = 0; | |
| 1064 /* Actual condition, one line up, should be that value2's address | |
| 1065 depends on value1, but that is too much of a pain. */ | |
| 1066 } | |
| 1067 | |
| 1068 /* Output integer move instructions. */ | |
| 1069 | |
| 1070 const char * | |
| 1071 vax_output_int_move (rtx insn ATTRIBUTE_UNUSED, rtx *operands, | |
| 1072 enum machine_mode mode) | |
| 1073 { | |
|
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1074 rtx hi[3], lo[3]; |
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1075 const char *pattern_hi, *pattern_lo; |
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1076 |
| 0 | 1077 switch (mode) |
| 1078 { | |
|
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1079 case DImode: |
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1080 if (operands[1] == const0_rtx) |
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1081 return "clrq %0"; |
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1082 if (TARGET_QMATH && optimize_size |
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1083 && (CONST_INT_P (operands[1]) |
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1084 || GET_CODE (operands[1]) == CONST_DOUBLE)) |
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1085 { |
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1086 unsigned HOST_WIDE_INT hval, lval; |
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1087 int n; |
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1088 |
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1089 if (GET_CODE (operands[1]) == CONST_DOUBLE) |
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1090 { |
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1091 gcc_assert (HOST_BITS_PER_WIDE_INT != 64); |
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1092 |
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1093 /* Make sure only the low 32 bits are valid. */ |
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1094 lval = CONST_DOUBLE_LOW (operands[1]) & 0xffffffff; |
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1095 hval = CONST_DOUBLE_HIGH (operands[1]) & 0xffffffff; |
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1096 } |
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1097 else |
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1098 { |
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1099 lval = INTVAL (operands[1]); |
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1100 hval = 0; |
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1101 } |
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1102 |
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1103 /* Here we see if we are trying to see if the 64bit value is really |
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1104 a 6bit shifted some arbitrary amount. If so, we can use ashq to |
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1105 shift it to the correct value saving 7 bytes (1 addr-mode-byte + |
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1106 8 bytes - 1 shift byte - 1 short literal byte. */ |
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1107 if (lval != 0 |
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1108 && (n = exact_log2 (lval & (- lval))) != -1 |
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1109 && (lval >> n) < 64) |
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1110 { |
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1111 lval >>= n; |
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1112 |
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1113 #if HOST_BITS_PER_WIDE_INT == 32 |
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1114 /* On 32bit platforms, if the 6bits didn't overflow into the |
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1115 upper 32bit value that value better be 0. If we have |
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1116 overflowed, make sure it wasn't too much. */ |
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1117 if (hval != 0) |
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1118 { |
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1119 if (n <= 26 || hval >= ((unsigned)1 << (n - 26))) |
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1120 n = 0; /* failure */ |
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1121 else |
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1122 lval |= hval << (32 - n); |
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1123 } |
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1124 #endif |
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1125 /* If n is 0, then ashq is not the best way to emit this. */ |
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changeset
|
1126 if (n > 0) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1127 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1128 operands[1] = GEN_INT (lval); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1129 operands[2] = GEN_INT (n); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1130 return "ashq %2,%1,%0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1131 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1132 #if HOST_BITS_PER_WIDE_INT == 32 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1133 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1134 /* On 32bit platforms, if the low 32bit value is 0, checkout the |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1135 upper 32bit value. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1136 else if (hval != 0 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1137 && (n = exact_log2 (hval & (- hval)) - 1) != -1 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1138 && (hval >> n) < 64) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1139 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1140 operands[1] = GEN_INT (hval >> n); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1141 operands[2] = GEN_INT (n + 32); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1142 return "ashq %2,%1,%0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1143 #endif |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1144 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1145 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1146 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1147 if (TARGET_QMATH |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1148 && (!MEM_P (operands[0]) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1149 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1150 || GET_CODE (XEXP (operands[0], 0)) == POST_INC |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1151 || !illegal_addsub_di_memory_operand (operands[0], DImode)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1152 && ((CONST_INT_P (operands[1]) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1153 && (unsigned HOST_WIDE_INT) INTVAL (operands[1]) >= 64) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1154 || GET_CODE (operands[1]) == CONST_DOUBLE)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1155 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1156 hi[0] = operands[0]; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1157 hi[1] = operands[1]; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1158 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1159 split_quadword_operands (insn, SET, hi, lo, 2); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1160 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1161 pattern_lo = vax_output_int_move (NULL, lo, SImode); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1162 pattern_hi = vax_output_int_move (NULL, hi, SImode); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1163 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1164 /* The patterns are just movl/movl or pushl/pushl then a movq will |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1165 be shorter (1 opcode byte + 1 addrmode byte + 8 immediate value |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1166 bytes .vs. 2 opcode bytes + 2 addrmode bytes + 8 immediate value |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1167 value bytes. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1168 if ((!strncmp (pattern_lo, "movl", 4) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1169 && !strncmp (pattern_hi, "movl", 4)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1170 || (!strncmp (pattern_lo, "pushl", 5) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1171 && !strncmp (pattern_hi, "pushl", 5))) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1172 return "movq %1,%0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1173 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1174 if (MEM_P (operands[0]) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1175 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1176 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1177 output_asm_insn (pattern_hi, hi); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1178 operands[0] = lo[0]; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1179 operands[1] = lo[1]; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1180 operands[2] = lo[2]; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1181 return pattern_lo; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1182 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1183 else |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1184 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1185 output_asm_insn (pattern_lo, lo); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1186 operands[0] = hi[0]; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1187 operands[1] = hi[1]; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1188 operands[2] = hi[2]; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1189 return pattern_hi; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1190 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1191 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1192 return "movq %1,%0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1193 |
| 0 | 1194 case SImode: |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1195 if (symbolic_operand (operands[1], SImode)) |
| 0 | 1196 { |
| 1197 if (push_operand (operands[0], SImode)) | |
| 1198 return "pushab %a1"; | |
| 1199 return "movab %a1,%0"; | |
| 1200 } | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1201 |
| 0 | 1202 if (operands[1] == const0_rtx) |
| 1203 { | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1204 if (push_operand (operands[1], SImode)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1205 return "pushl %1"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1206 return "clrl %0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1207 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1208 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1209 if (CONST_INT_P (operands[1]) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1210 && (unsigned HOST_WIDE_INT) INTVAL (operands[1]) >= 64) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1211 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1212 HOST_WIDE_INT i = INTVAL (operands[1]); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1213 int n; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1214 if ((unsigned HOST_WIDE_INT)(~i) < 64) |
| 0 | 1215 return "mcoml %N1,%0"; |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1216 if ((unsigned HOST_WIDE_INT)i < 0x100) |
| 0 | 1217 return "movzbl %1,%0"; |
| 1218 if (i >= -0x80 && i < 0) | |
| 1219 return "cvtbl %1,%0"; | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1220 if (optimize_size |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1221 && (n = exact_log2 (i & (-i))) != -1 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1222 && ((unsigned HOST_WIDE_INT)i >> n) < 64) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1223 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1224 operands[1] = GEN_INT ((unsigned HOST_WIDE_INT)i >> n); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1225 operands[2] = GEN_INT (n); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1226 return "ashl %2,%1,%0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1227 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1228 if ((unsigned HOST_WIDE_INT)i < 0x10000) |
| 0 | 1229 return "movzwl %1,%0"; |
| 1230 if (i >= -0x8000 && i < 0) | |
| 1231 return "cvtwl %1,%0"; | |
| 1232 } | |
| 1233 if (push_operand (operands[0], SImode)) | |
| 1234 return "pushl %1"; | |
| 1235 return "movl %1,%0"; | |
| 1236 | |
| 1237 case HImode: | |
| 1238 if (CONST_INT_P (operands[1])) | |
| 1239 { | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1240 HOST_WIDE_INT i = INTVAL (operands[1]); |
| 0 | 1241 if (i == 0) |
| 1242 return "clrw %0"; | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1243 else if ((unsigned HOST_WIDE_INT)i < 64) |
| 0 | 1244 return "movw %1,%0"; |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1245 else if ((unsigned HOST_WIDE_INT)~i < 64) |
| 0 | 1246 return "mcomw %H1,%0"; |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1247 else if ((unsigned HOST_WIDE_INT)i < 256) |
| 0 | 1248 return "movzbw %1,%0"; |
|
55
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update it from 4.4.3 to 4.5.0
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19
diff
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|
1249 else if (i >= -0x80 && i < 0) |
|
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19
diff
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|
1250 return "cvtbw %1,%0"; |
| 0 | 1251 } |
| 1252 return "movw %1,%0"; | |
| 1253 | |
| 1254 case QImode: | |
| 1255 if (CONST_INT_P (operands[1])) | |
| 1256 { | |
|
55
77e2b8dfacca
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19
diff
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|
1257 HOST_WIDE_INT i = INTVAL (operands[1]); |
| 0 | 1258 if (i == 0) |
| 1259 return "clrb %0"; | |
|
55
77e2b8dfacca
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parents:
19
diff
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|
1260 else if ((unsigned HOST_WIDE_INT)~i < 64) |
| 0 | 1261 return "mcomb %B1,%0"; |
| 1262 } | |
| 1263 return "movb %1,%0"; | |
| 1264 | |
| 1265 default: | |
| 1266 gcc_unreachable (); | |
| 1267 } | |
| 1268 } | |
| 1269 | |
| 1270 /* Output integer add instructions. | |
| 1271 | |
| 1272 The space-time-opcode tradeoffs for addition vary by model of VAX. | |
| 1273 | |
| 1274 On a VAX 3 "movab (r1)[r2],r3" is faster than "addl3 r1,r2,r3", | |
| 1275 but it not faster on other models. | |
| 1276 | |
| 1277 "movab #(r1),r2" is usually shorter than "addl3 #,r1,r2", and is | |
| 1278 faster on a VAX 3, but some VAXen (e.g. VAX 9000) will stall if | |
| 1279 a register is used in an address too soon after it is set. | |
| 1280 Compromise by using movab only when it is shorter than the add | |
| 1281 or the base register in the address is one of sp, ap, and fp, | |
| 1282 which are not modified very often. */ | |
| 1283 | |
| 1284 const char * | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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19
diff
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|
1285 vax_output_int_add (rtx insn, rtx *operands, enum machine_mode mode) |
| 0 | 1286 { |
| 1287 switch (mode) | |
| 1288 { | |
|
55
77e2b8dfacca
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19
diff
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|
1289 case DImode: |
|
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19
diff
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|
1290 { |
|
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19
diff
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|
1291 rtx low[3]; |
|
77e2b8dfacca
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19
diff
changeset
|
1292 const char *pattern; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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19
diff
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|
1293 int carry = 1; |
|
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19
diff
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|
1294 bool sub; |
|
77e2b8dfacca
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19
diff
changeset
|
1295 |
|
77e2b8dfacca
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parents:
19
diff
changeset
|
1296 if (TARGET_QMATH && 0) |
|
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19
diff
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|
1297 debug_rtx (insn); |
|
77e2b8dfacca
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19
diff
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|
1298 |
|
77e2b8dfacca
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19
diff
changeset
|
1299 split_quadword_operands (insn, PLUS, operands, low, 3); |
|
77e2b8dfacca
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19
diff
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|
1300 |
|
77e2b8dfacca
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19
diff
changeset
|
1301 if (TARGET_QMATH) |
|
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19
diff
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|
1302 { |
|
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parents:
19
diff
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|
1303 gcc_assert (rtx_equal_p (operands[0], operands[1])); |
|
77e2b8dfacca
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19
diff
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|
1304 #ifdef NO_EXTERNAL_INDIRECT_ADDRESSS |
|
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19
diff
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|
1305 gcc_assert (!flag_pic || !external_memory_operand (low[2], SImode)); |
|
77e2b8dfacca
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19
diff
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|
1306 gcc_assert (!flag_pic || !external_memory_operand (low[0], SImode)); |
|
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19
diff
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|
1307 #endif |
|
77e2b8dfacca
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19
diff
changeset
|
1308 |
|
77e2b8dfacca
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19
diff
changeset
|
1309 /* No reason to add a 0 to the low part and thus no carry, so just |
|
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19
diff
changeset
|
1310 emit the appropriate add/sub instruction. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
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|
1311 if (low[2] == const0_rtx) |
|
77e2b8dfacca
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parents:
19
diff
changeset
|
1312 return vax_output_int_add (NULL, operands, SImode); |
|
77e2b8dfacca
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19
diff
changeset
|
1313 |
|
77e2b8dfacca
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parents:
19
diff
changeset
|
1314 /* Are we doing addition or subtraction? */ |
|
77e2b8dfacca
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19
diff
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|
1315 sub = CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0; |
|
77e2b8dfacca
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19
diff
changeset
|
1316 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
1317 /* We can't use vax_output_int_add since some the patterns don't |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
1318 modify the carry bit. */ |
|
77e2b8dfacca
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parents:
19
diff
changeset
|
1319 if (sub) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
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|
1320 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
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|
1321 if (low[2] == constm1_rtx) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
1322 pattern = "decl %0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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19
diff
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|
1323 else |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
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|
1324 pattern = "subl2 $%n2,%0"; |
|
77e2b8dfacca
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parents:
19
diff
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|
1325 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
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|
1326 else |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
1327 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
1328 if (low[2] == const1_rtx) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1329 pattern = "incl %0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
1330 else |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
1331 pattern = "addl2 %2,%0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1332 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1333 output_asm_insn (pattern, low); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1334 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1335 /* In 2's complement, -n = ~n + 1. Since we are dealing with |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1336 two 32bit parts, we complement each and then add one to |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1337 low part. We know that the low part can't overflow since |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1338 it's value can never be 0. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
1339 if (sub) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
1340 return "sbwc %N2,%0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
1341 return "adwc %2,%0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
1342 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
1343 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
1344 /* Add low parts. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1345 if (rtx_equal_p (operands[0], operands[1])) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1346 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1347 if (low[2] == const0_rtx) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1348 /* Should examine operand, punt if not POST_INC. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1349 pattern = "tstl %0", carry = 0; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
1350 else if (low[2] == const1_rtx) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
1351 pattern = "incl %0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1352 else |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1353 pattern = "addl2 %2,%0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
1354 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1355 else |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1356 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1357 if (low[2] == const0_rtx) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1358 pattern = "movl %1,%0", carry = 0; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1359 else |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1360 pattern = "addl3 %2,%1,%0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
1361 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1362 if (pattern) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1363 output_asm_insn (pattern, low); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1364 if (!carry) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1365 /* If CARRY is 0, we don't have any carry value to worry about. */ |
|
77e2b8dfacca
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1366 return get_insn_template (CODE_FOR_addsi3, insn); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1367 /* %0 = C + %1 + %2 */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1368 if (!rtx_equal_p (operands[0], operands[1])) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1369 output_asm_insn ((operands[1] == const0_rtx |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1370 ? "clrl %0" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1371 : "movl %1,%0"), operands); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
1372 return "adwc %2,%0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
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parents:
19
diff
changeset
|
1373 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1374 |
| 0 | 1375 case SImode: |
| 1376 if (rtx_equal_p (operands[0], operands[1])) | |
| 1377 { | |
| 1378 if (operands[2] == const1_rtx) | |
| 1379 return "incl %0"; | |
| 1380 if (operands[2] == constm1_rtx) | |
| 1381 return "decl %0"; | |
| 1382 if (CONST_INT_P (operands[2]) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1383 && (unsigned HOST_WIDE_INT) (- INTVAL (operands[2])) < 64) |
| 0 | 1384 return "subl2 $%n2,%0"; |
| 1385 if (CONST_INT_P (operands[2]) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1386 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 64 |
| 0 | 1387 && REG_P (operands[1]) |
| 1388 && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768) | |
| 1389 || REGNO (operands[1]) > 11)) | |
| 1390 return "movab %c2(%1),%0"; | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1391 if (REG_P (operands[0]) && symbolic_operand (operands[2], SImode)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1392 return "movab %a2[%0],%0"; |
| 0 | 1393 return "addl2 %2,%0"; |
| 1394 } | |
| 1395 | |
| 1396 if (rtx_equal_p (operands[0], operands[2])) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1397 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1398 if (REG_P (operands[0]) && symbolic_operand (operands[1], SImode)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1399 return "movab %a1[%0],%0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1400 return "addl2 %1,%0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1401 } |
| 0 | 1402 |
| 1403 if (CONST_INT_P (operands[2]) | |
| 1404 && INTVAL (operands[2]) < 32767 | |
| 1405 && INTVAL (operands[2]) > -32768 | |
| 1406 && REG_P (operands[1]) | |
| 1407 && push_operand (operands[0], SImode)) | |
| 1408 return "pushab %c2(%1)"; | |
| 1409 | |
| 1410 if (CONST_INT_P (operands[2]) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1411 && (unsigned HOST_WIDE_INT) (- INTVAL (operands[2])) < 64) |
| 0 | 1412 return "subl3 $%n2,%1,%0"; |
| 1413 | |
| 1414 if (CONST_INT_P (operands[2]) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1415 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 64 |
| 0 | 1416 && REG_P (operands[1]) |
| 1417 && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768) | |
| 1418 || REGNO (operands[1]) > 11)) | |
| 1419 return "movab %c2(%1),%0"; | |
| 1420 | |
| 1421 /* Add this if using gcc on a VAX 3xxx: | |
| 1422 if (REG_P (operands[1]) && REG_P (operands[2])) | |
| 1423 return "movab (%1)[%2],%0"; | |
| 1424 */ | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1425 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1426 if (REG_P (operands[1]) && symbolic_operand (operands[2], SImode)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1427 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1428 if (push_operand (operands[0], SImode)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1429 return "pushab %a2[%1]"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1430 return "movab %a2[%1],%0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1431 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1432 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1433 if (REG_P (operands[2]) && symbolic_operand (operands[1], SImode)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1434 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1435 if (push_operand (operands[0], SImode)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1436 return "pushab %a1[%2]"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1437 return "movab %a1[%2],%0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1438 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1439 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1440 if (flag_pic && REG_P (operands[0]) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1441 && symbolic_operand (operands[2], SImode)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1442 return "movab %a2,%0;addl2 %1,%0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1443 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1444 if (flag_pic |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1445 && (symbolic_operand (operands[1], SImode) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1446 || symbolic_operand (operands[1], SImode))) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1447 debug_rtx (insn); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1448 |
| 0 | 1449 return "addl3 %1,%2,%0"; |
| 1450 | |
| 1451 case HImode: | |
| 1452 if (rtx_equal_p (operands[0], operands[1])) | |
| 1453 { | |
| 1454 if (operands[2] == const1_rtx) | |
| 1455 return "incw %0"; | |
| 1456 if (operands[2] == constm1_rtx) | |
| 1457 return "decw %0"; | |
| 1458 if (CONST_INT_P (operands[2]) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1459 && (unsigned HOST_WIDE_INT) (- INTVAL (operands[2])) < 64) |
| 0 | 1460 return "subw2 $%n2,%0"; |
| 1461 return "addw2 %2,%0"; | |
| 1462 } | |
| 1463 if (rtx_equal_p (operands[0], operands[2])) | |
| 1464 return "addw2 %1,%0"; | |
| 1465 if (CONST_INT_P (operands[2]) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1466 && (unsigned HOST_WIDE_INT) (- INTVAL (operands[2])) < 64) |
| 0 | 1467 return "subw3 $%n2,%1,%0"; |
| 1468 return "addw3 %1,%2,%0"; | |
| 1469 | |
| 1470 case QImode: | |
| 1471 if (rtx_equal_p (operands[0], operands[1])) | |
| 1472 { | |
| 1473 if (operands[2] == const1_rtx) | |
| 1474 return "incb %0"; | |
| 1475 if (operands[2] == constm1_rtx) | |
| 1476 return "decb %0"; | |
| 1477 if (CONST_INT_P (operands[2]) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1478 && (unsigned HOST_WIDE_INT) (- INTVAL (operands[2])) < 64) |
| 0 | 1479 return "subb2 $%n2,%0"; |
| 1480 return "addb2 %2,%0"; | |
| 1481 } | |
| 1482 if (rtx_equal_p (operands[0], operands[2])) | |
| 1483 return "addb2 %1,%0"; | |
| 1484 if (CONST_INT_P (operands[2]) | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1485 && (unsigned HOST_WIDE_INT) (- INTVAL (operands[2])) < 64) |
| 0 | 1486 return "subb3 $%n2,%1,%0"; |
| 1487 return "addb3 %1,%2,%0"; | |
| 1488 | |
| 1489 default: | |
| 1490 gcc_unreachable (); | |
| 1491 } | |
| 1492 } | |
| 1493 | |
| 1494 const char * | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1495 vax_output_int_subtract (rtx insn, rtx *operands, enum machine_mode mode) |
| 0 | 1496 { |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1497 switch (mode) |
| 0 | 1498 { |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1499 case DImode: |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1500 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1501 rtx low[3]; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1502 const char *pattern; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1503 int carry = 1; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1504 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1505 if (TARGET_QMATH && 0) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1506 debug_rtx (insn); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1507 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1508 split_quadword_operands (insn, MINUS, operands, low, 3); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1509 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1510 if (TARGET_QMATH) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1511 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1512 if (operands[1] == const0_rtx && low[1] == const0_rtx) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1513 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1514 /* Negation is tricky. It's basically complement and increment. |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1515 Negate hi, then lo, and subtract the carry back. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1516 if ((MEM_P (low[0]) && GET_CODE (XEXP (low[0], 0)) == POST_INC) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1517 || (MEM_P (operands[0]) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1518 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1519 fatal_insn ("illegal operand detected", insn); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1520 output_asm_insn ("mnegl %2,%0", operands); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1521 output_asm_insn ("mnegl %2,%0", low); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1522 return "sbwc $0,%0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1523 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1524 gcc_assert (rtx_equal_p (operands[0], operands[1])); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1525 gcc_assert (rtx_equal_p (low[0], low[1])); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1526 if (low[2] == const1_rtx) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1527 output_asm_insn ("decl %0", low); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1528 else |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1529 output_asm_insn ("subl2 %2,%0", low); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1530 return "sbwc %2,%0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1531 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1532 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1533 /* Subtract low parts. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1534 if (rtx_equal_p (operands[0], operands[1])) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1535 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1536 if (low[2] == const0_rtx) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1537 pattern = 0, carry = 0; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1538 else if (low[2] == constm1_rtx) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1539 pattern = "decl %0"; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1540 else |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
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|
1541 pattern = "subl2 %2,%0"; |
|
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diff
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|
1542 } |
|
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diff
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|
1543 else |
|
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diff
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|
1544 { |
|
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|
1545 if (low[2] == constm1_rtx) |
|
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diff
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|
1546 pattern = "decl %0"; |
|
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diff
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|
1547 else if (low[2] == const0_rtx) |
|
77e2b8dfacca
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|
1548 pattern = get_insn_template (CODE_FOR_movsi, insn), carry = 0; |
|
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diff
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|
1549 else |
|
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|
1550 pattern = "subl3 %2,%1,%0"; |
|
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|
1551 } |
|
77e2b8dfacca
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|
1552 if (pattern) |
|
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diff
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|
1553 output_asm_insn (pattern, low); |
|
77e2b8dfacca
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diff
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|
1554 if (carry) |
|
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diff
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|
1555 { |
|
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|
1556 if (!rtx_equal_p (operands[0], operands[1])) |
|
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diff
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|
1557 return "movl %1,%0;sbwc %2,%0"; |
|
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|
1558 return "sbwc %2,%0"; |
|
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|
1559 /* %0 = %2 - %1 - C */ |
|
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|
1560 } |
|
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|
1561 return get_insn_template (CODE_FOR_subsi3, insn); |
|
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|
1562 } |
|
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|
1563 |
|
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|
1564 default: |
|
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|
1565 gcc_unreachable (); |
|
77e2b8dfacca
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|
1566 } |
| 0 | 1567 } |
| 1568 | |
|
55
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|
1569 /* True if X is an rtx for a constant that is a valid address. */ |
| 0 | 1570 |
|
55
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|
1571 bool |
| 0 | 1572 legitimate_constant_address_p (rtx x) |
| 1573 { | |
|
55
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|
1574 if (GET_CODE (x) == LABEL_REF || GET_CODE (x) == SYMBOL_REF |
|
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|
1575 || CONST_INT_P (x) || GET_CODE (x) == HIGH) |
|
77e2b8dfacca
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|
1576 return true; |
|
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diff
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|
1577 if (GET_CODE (x) != CONST) |
|
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|
1578 return false; |
|
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diff
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|
1579 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS |
|
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diff
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|
1580 if (flag_pic |
|
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|
1581 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF |
|
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|
1582 && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (x, 0), 0))) |
|
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|
1583 return false; |
|
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diff
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|
1584 #endif |
|
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|
1585 return true; |
| 0 | 1586 } |
| 1587 | |
|
55
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|
1588 /* True if the constant value X is a legitimate general operand. |
| 0 | 1589 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ |
| 1590 | |
|
55
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diff
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|
1591 bool |
| 0 | 1592 legitimate_constant_p (rtx x ATTRIBUTE_UNUSED) |
| 1593 { | |
|
55
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|
1594 return true; |
| 0 | 1595 } |
| 1596 | |
| 1597 /* The other macros defined here are used only in legitimate_address_p (). */ | |
| 1598 | |
| 1599 /* Nonzero if X is a hard reg that can be used as an index | |
| 1600 or, if not strict, if it is a pseudo reg. */ | |
| 1601 #define INDEX_REGISTER_P(X, STRICT) \ | |
| 1602 (REG_P (X) && (!(STRICT) || REGNO_OK_FOR_INDEX_P (REGNO (X)))) | |
| 1603 | |
| 1604 /* Nonzero if X is a hard reg that can be used as a base reg | |
| 1605 or, if not strict, if it is a pseudo reg. */ | |
| 1606 #define BASE_REGISTER_P(X, STRICT) \ | |
| 1607 (REG_P (X) && (!(STRICT) || REGNO_OK_FOR_BASE_P (REGNO (X)))) | |
| 1608 | |
| 1609 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS | |
| 1610 | |
| 1611 /* Re-definition of CONSTANT_ADDRESS_P, which is true only when there | |
| 1612 are no SYMBOL_REFs for external symbols present. */ | |
| 1613 | |
|
55
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diff
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|
1614 static bool |
|
77e2b8dfacca
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diff
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|
1615 indirectable_constant_address_p (rtx x, bool indirect) |
| 0 | 1616 { |
|
55
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diff
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|
1617 if (GET_CODE (x) == SYMBOL_REF) |
|
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diff
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|
1618 return !flag_pic || SYMBOL_REF_LOCAL_P (x) || !indirect; |
| 0 | 1619 |
|
55
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19
diff
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|
1620 if (GET_CODE (x) == CONST) |
|
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diff
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|
1621 return !flag_pic |
|
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|
1622 || GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF |
|
77e2b8dfacca
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19
diff
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|
1623 || SYMBOL_REF_LOCAL_P (XEXP (XEXP (x, 0), 0)); |
|
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diff
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|
1624 |
|
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diff
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|
1625 return CONSTANT_ADDRESS_P (x); |
| 0 | 1626 } |
| 1627 | |
| 1628 #else /* not NO_EXTERNAL_INDIRECT_ADDRESS */ | |
| 1629 | |
|
55
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19
diff
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|
1630 static bool |
|
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diff
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|
1631 indirectable_constant_address_p (rtx x, bool indirect ATTRIBUTE_UNUSED) |
| 0 | 1632 { |
| 1633 return CONSTANT_ADDRESS_P (x); | |
| 1634 } | |
| 1635 | |
| 1636 #endif /* not NO_EXTERNAL_INDIRECT_ADDRESS */ | |
| 1637 | |
|
55
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19
diff
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|
1638 /* True if X is an address which can be indirected. External symbols |
| 0 | 1639 could be in a sharable image library, so we disallow those. */ |
| 1640 | |
|
55
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19
diff
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|
1641 static bool |
|
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diff
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|
1642 indirectable_address_p (rtx x, bool strict, bool indirect) |
| 0 | 1643 { |
|
55
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diff
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|
1644 if (indirectable_constant_address_p (x, indirect) |
|
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19
diff
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|
1645 || BASE_REGISTER_P (x, strict)) |
|
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19
diff
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|
1646 return true; |
|
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19
diff
changeset
|
1647 if (GET_CODE (x) != PLUS |
|
77e2b8dfacca
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19
diff
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|
1648 || !BASE_REGISTER_P (XEXP (x, 0), strict) |
|
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diff
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|
1649 || (flag_pic && !CONST_INT_P (XEXP (x, 1)))) |
|
77e2b8dfacca
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diff
changeset
|
1650 return false; |
|
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|
1651 return indirectable_constant_address_p (XEXP (x, 1), indirect); |
| 0 | 1652 } |
| 1653 | |
|
55
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diff
changeset
|
1654 /* Return true if x is a valid address not using indexing. |
| 0 | 1655 (This much is the easy part.) */ |
|
55
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diff
changeset
|
1656 static bool |
|
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|
1657 nonindexed_address_p (rtx x, bool strict) |
| 0 | 1658 { |
| 1659 rtx xfoo0; | |
| 1660 if (REG_P (x)) | |
| 1661 { | |
| 1662 extern rtx *reg_equiv_mem; | |
|
55
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diff
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|
1663 if (! reload_in_progress |
| 0 | 1664 || reg_equiv_mem[REGNO (x)] == 0 |
|
55
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|
1665 || indirectable_address_p (reg_equiv_mem[REGNO (x)], strict, false)) |
|
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|
1666 return true; |
| 0 | 1667 } |
|
55
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diff
changeset
|
1668 if (indirectable_constant_address_p (x, false)) |
|
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changeset
|
1669 return true; |
|
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19
diff
changeset
|
1670 if (indirectable_address_p (x, strict, false)) |
|
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|
1671 return true; |
| 0 | 1672 xfoo0 = XEXP (x, 0); |
|
55
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diff
changeset
|
1673 if (MEM_P (x) && indirectable_address_p (xfoo0, strict, true)) |
|
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|
1674 return true; |
| 0 | 1675 if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC) |
| 1676 && BASE_REGISTER_P (xfoo0, strict)) | |
|
55
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|
1677 return true; |
|
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|
1678 return false; |
| 0 | 1679 } |
| 1680 | |
|
55
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|
1681 /* True if PROD is either a reg times size of mode MODE and MODE is less |
| 0 | 1682 than or equal 8 bytes, or just a reg if MODE is one byte. */ |
| 1683 | |
|
55
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diff
changeset
|
1684 static bool |
|
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diff
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|
1685 index_term_p (rtx prod, enum machine_mode mode, bool strict) |
| 0 | 1686 { |
| 1687 rtx xfoo0, xfoo1; | |
| 1688 | |
| 1689 if (GET_MODE_SIZE (mode) == 1) | |
| 1690 return BASE_REGISTER_P (prod, strict); | |
| 1691 | |
| 1692 if (GET_CODE (prod) != MULT || GET_MODE_SIZE (mode) > 8) | |
|
55
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diff
changeset
|
1693 return false; |
| 0 | 1694 |
| 1695 xfoo0 = XEXP (prod, 0); | |
| 1696 xfoo1 = XEXP (prod, 1); | |
| 1697 | |
| 1698 if (CONST_INT_P (xfoo0) | |
| 1699 && INTVAL (xfoo0) == (int)GET_MODE_SIZE (mode) | |
| 1700 && INDEX_REGISTER_P (xfoo1, strict)) | |
|
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|
1701 return true; |
| 0 | 1702 |
| 1703 if (CONST_INT_P (xfoo1) | |
| 1704 && INTVAL (xfoo1) == (int)GET_MODE_SIZE (mode) | |
| 1705 && INDEX_REGISTER_P (xfoo0, strict)) | |
|
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|
1706 return true; |
| 0 | 1707 |
|
55
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|
1708 return false; |
| 0 | 1709 } |
| 1710 | |
|
55
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diff
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|
1711 /* Return true if X is the sum of a register |
| 0 | 1712 and a valid index term for mode MODE. */ |
|
55
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diff
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|
1713 static bool |
|
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|
1714 reg_plus_index_p (rtx x, enum machine_mode mode, bool strict) |
| 0 | 1715 { |
| 1716 rtx xfoo0, xfoo1; | |
| 1717 | |
| 1718 if (GET_CODE (x) != PLUS) | |
|
55
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|
1719 return false; |
| 0 | 1720 |
| 1721 xfoo0 = XEXP (x, 0); | |
| 1722 xfoo1 = XEXP (x, 1); | |
| 1723 | |
| 1724 if (BASE_REGISTER_P (xfoo0, strict) && index_term_p (xfoo1, mode, strict)) | |
|
55
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|
1725 return true; |
| 0 | 1726 |
| 1727 if (BASE_REGISTER_P (xfoo1, strict) && index_term_p (xfoo0, mode, strict)) | |
|
55
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|
1728 return true; |
| 0 | 1729 |
|
55
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|
1730 return false; |
| 0 | 1731 } |
| 1732 | |
|
55
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|
1733 /* Return true if xfoo0 and xfoo1 constitute a valid indexed address. */ |
|
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|
1734 static bool |
|
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|
1735 indexable_address_p (rtx xfoo0, rtx xfoo1, enum machine_mode mode, bool strict) |
|
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|
1736 { |
|
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|
1737 if (!CONSTANT_ADDRESS_P (xfoo0)) |
|
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|
1738 return false; |
|
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|
1739 if (BASE_REGISTER_P (xfoo1, strict)) |
|
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|
1740 return !flag_pic || mode == QImode; |
|
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|
1741 if (flag_pic && symbolic_operand (xfoo0, SImode)) |
|
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|
1742 return false; |
|
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|
1743 return reg_plus_index_p (xfoo1, mode, strict); |
|
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|
1744 } |
|
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|
1745 |
|
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|
1746 /* legitimate_address_p returns true if it recognizes an RTL expression "x" |
| 0 | 1747 that is a valid memory address for an instruction. |
| 1748 The MODE argument is the machine mode for the MEM expression | |
| 1749 that wants to use this address. */ | |
|
55
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|
1750 bool |
|
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|
1751 vax_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) |
| 0 | 1752 { |
| 1753 rtx xfoo0, xfoo1; | |
| 1754 | |
| 1755 if (nonindexed_address_p (x, strict)) | |
|
55
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|
1756 return true; |
| 0 | 1757 |
| 1758 if (GET_CODE (x) != PLUS) | |
|
55
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|
1759 return false; |
| 0 | 1760 |
| 1761 /* Handle <address>[index] represented with index-sum outermost */ | |
| 1762 | |
| 1763 xfoo0 = XEXP (x, 0); | |
| 1764 xfoo1 = XEXP (x, 1); | |
| 1765 | |
| 1766 if (index_term_p (xfoo0, mode, strict) | |
| 1767 && nonindexed_address_p (xfoo1, strict)) | |
|
55
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|
1768 return true; |
| 0 | 1769 |
| 1770 if (index_term_p (xfoo1, mode, strict) | |
| 1771 && nonindexed_address_p (xfoo0, strict)) | |
|
55
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|
1772 return true; |
| 0 | 1773 |
| 1774 /* Handle offset(reg)[index] with offset added outermost */ | |
| 1775 | |
|
55
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|
1776 if (indexable_address_p (xfoo0, xfoo1, mode, strict) |
|
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|
1777 || indexable_address_p (xfoo1, xfoo0, mode, strict)) |
|
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|
1778 return true; |
| 0 | 1779 |
|
55
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|
1780 return false; |
| 0 | 1781 } |
| 1782 | |
|
55
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|
1783 /* Return true if x (a legitimate address expression) has an effect that |
| 0 | 1784 depends on the machine mode it is used for. On the VAX, the predecrement |
| 1785 and postincrement address depend thus (the amount of decrement or | |
| 1786 increment being the length of the operand) and all indexed address depend | |
| 1787 thus (because the index scale factor is the length of the operand). */ | |
| 1788 | |
|
55
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|
1789 bool |
| 0 | 1790 vax_mode_dependent_address_p (rtx x) |
| 1791 { | |
| 1792 rtx xfoo0, xfoo1; | |
| 1793 | |
| 1794 /* Auto-increment cases are now dealt with generically in recog.c. */ | |
| 1795 if (GET_CODE (x) != PLUS) | |
|
55
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|
1796 return false; |
| 0 | 1797 |
| 1798 xfoo0 = XEXP (x, 0); | |
| 1799 xfoo1 = XEXP (x, 1); | |
| 1800 | |
|
55
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|
1801 if (CONST_INT_P (xfoo0) && REG_P (xfoo1)) |
|
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|
1802 return false; |
|
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|
1803 if (CONST_INT_P (xfoo1) && REG_P (xfoo0)) |
|
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|
1804 return false; |
|
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|
1805 if (!flag_pic && CONSTANT_ADDRESS_P (xfoo0) && REG_P (xfoo1)) |
|
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|
1806 return false; |
|
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|
1807 if (!flag_pic && CONSTANT_ADDRESS_P (xfoo1) && REG_P (xfoo0)) |
|
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|
1808 return false; |
|
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|
1809 |
|
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|
1810 return true; |
|
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diff
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|
1811 } |
|
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|
1812 |
|
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diff
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|
1813 static rtx |
|
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|
1814 fixup_mathdi_operand (rtx x, enum machine_mode mode) |
|
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|
1815 { |
|
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|
1816 if (illegal_addsub_di_memory_operand (x, mode)) |
|
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|
1817 { |
|
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|
1818 rtx addr = XEXP (x, 0); |
|
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|
1819 rtx temp = gen_reg_rtx (Pmode); |
|
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|
1820 rtx offset = 0; |
|
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|
1821 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS |
|
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|
1822 if (GET_CODE (addr) == CONST && flag_pic) |
|
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|
1823 { |
|
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|
1824 offset = XEXP (XEXP (addr, 0), 1); |
|
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|
1825 addr = XEXP (XEXP (addr, 0), 0); |
|
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1826 } |
|
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|
1827 #endif |
|
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|
1828 emit_move_insn (temp, addr); |
|
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changeset
|
1829 if (offset) |
|
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|
1830 temp = gen_rtx_PLUS (Pmode, temp, offset); |
|
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|
1831 x = gen_rtx_MEM (DImode, temp); |
|
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1832 } |
|
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|
1833 return x; |
|
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1834 } |
|
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|
1835 |
|
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|
1836 void |
|
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|
1837 vax_expand_addsub_di_operands (rtx * operands, enum rtx_code code) |
|
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1838 { |
|
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|
1839 int hi_only = operand_subword (operands[2], 0, 0, DImode) == const0_rtx; |
|
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|
1840 rtx temp; |
|
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|
1841 |
|
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|
1842 rtx (*gen_old_insn)(rtx, rtx, rtx); |
|
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|
1843 rtx (*gen_si_insn)(rtx, rtx, rtx); |
|
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|
1844 rtx (*gen_insn)(rtx, rtx, rtx); |
|
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|
1845 |
|
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|
1846 if (code == PLUS) |
|
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|
1847 { |
|
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|
1848 gen_old_insn = gen_adddi3_old; |
|
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changeset
|
1849 gen_si_insn = gen_addsi3; |
|
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|
1850 gen_insn = gen_adcdi3; |
|
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changeset
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1851 } |
|
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|
1852 else if (code == MINUS) |
|
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changeset
|
1853 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1854 gen_old_insn = gen_subdi3_old; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1855 gen_si_insn = gen_subsi3; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1856 gen_insn = gen_sbcdi3; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1857 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1858 else |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1859 gcc_unreachable (); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1860 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1861 /* If this is addition (thus operands are commutative) and if there is one |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1862 addend that duplicates the desination, we want that addend to be the |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1863 first addend. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1864 if (code == PLUS |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1865 && rtx_equal_p (operands[0], operands[2]) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1866 && !rtx_equal_p (operands[1], operands[2])) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1867 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1868 temp = operands[2]; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1869 operands[2] = operands[1]; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1870 operands[1] = temp; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1871 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1872 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1873 if (!TARGET_QMATH) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1874 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1875 emit_insn ((*gen_old_insn) (operands[0], operands[1], operands[2])); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1876 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1877 else if (hi_only) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1878 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1879 if (!rtx_equal_p (operands[0], operands[1]) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1880 && (REG_P (operands[0]) && MEM_P (operands[1]))) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1881 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1882 emit_move_insn (operands[0], operands[1]); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1883 operands[1] = operands[0]; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1884 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1885 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1886 operands[0] = fixup_mathdi_operand (operands[0], DImode); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1887 operands[1] = fixup_mathdi_operand (operands[1], DImode); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1888 operands[2] = fixup_mathdi_operand (operands[2], DImode); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1889 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1890 if (!rtx_equal_p (operands[0], operands[1])) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1891 emit_move_insn (operand_subword (operands[0], 0, 0, DImode), |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1892 operand_subword (operands[1], 0, 0, DImode)); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1893 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1894 emit_insn ((*gen_si_insn) (operand_subword (operands[0], 1, 0, DImode), |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1895 operand_subword (operands[1], 1, 0, DImode), |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1896 operand_subword (operands[2], 1, 0, DImode))); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1897 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1898 else |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1899 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1900 /* If are adding the same value together, that's really a multiply by 2, |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1901 and that's just a left shift of 1. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1902 if (rtx_equal_p (operands[1], operands[2])) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1903 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1904 gcc_assert (code != MINUS); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1905 emit_insn (gen_ashldi3 (operands[0], operands[1], const1_rtx)); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1906 return; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1907 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1908 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1909 operands[0] = fixup_mathdi_operand (operands[0], DImode); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1910 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1911 /* If an operand is the same as operand[0], use the operand[0] rtx |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1912 because fixup will an equivalent rtx but not an equal one. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1913 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1914 if (rtx_equal_p (operands[0], operands[1])) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1915 operands[1] = operands[0]; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1916 else |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1917 operands[1] = fixup_mathdi_operand (operands[1], DImode); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1918 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1919 if (rtx_equal_p (operands[0], operands[2])) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1920 operands[2] = operands[0]; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1921 else |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1922 operands[2] = fixup_mathdi_operand (operands[2], DImode); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1923 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1924 /* If we are subtracting not from ourselves [d = a - b], and because the |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1925 carry ops are two operand only, we would need to do a move prior to |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1926 the subtract. And if d == b, we would need a temp otherwise |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1927 [d = a, d -= d] and we end up with 0. Instead we rewrite d = a - b |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1928 into d = -b, d += a. Since -b can never overflow, even if b == d, |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1929 no temp is needed. |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1930 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1931 If we are doing addition, since the carry ops are two operand, if |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1932 we aren't adding to ourselves, move the first addend to the |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1933 destination first. */ |
| 0 | 1934 |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1935 gcc_assert (operands[1] != const0_rtx || code == MINUS); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1936 if (!rtx_equal_p (operands[0], operands[1]) && operands[1] != const0_rtx) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1937 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1938 if (code == MINUS && CONSTANT_P (operands[1])) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1939 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1940 temp = gen_reg_rtx (DImode); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1941 emit_insn (gen_sbcdi3 (operands[0], const0_rtx, operands[2])); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1942 code = PLUS; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1943 gen_insn = gen_adcdi3; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1944 operands[2] = operands[1]; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1945 operands[1] = operands[0]; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1946 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1947 else |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1948 emit_move_insn (operands[0], operands[1]); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1949 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1950 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1951 /* Subtracting a constant will have been rewritten to an addition of the |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1952 negative of that constant before we get here. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1953 gcc_assert (!CONSTANT_P (operands[2]) || code == PLUS); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1954 emit_insn ((*gen_insn) (operands[0], operands[1], operands[2])); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1955 } |
| 0 | 1956 } |
|
55
77e2b8dfacca
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1957 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1958 bool |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1959 adjacent_operands_p (rtx lo, rtx hi, enum machine_mode mode) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1960 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1961 HOST_WIDE_INT lo_offset; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1962 HOST_WIDE_INT hi_offset; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1963 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1964 if (GET_CODE (lo) != GET_CODE (hi)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1965 return false; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1966 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1967 if (REG_P (lo)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1968 return mode == SImode && REGNO (lo) + 1 == REGNO (hi); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1969 if (CONST_INT_P (lo)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1970 return INTVAL (hi) == 0 && 0 <= INTVAL (lo) && INTVAL (lo) < 64; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1971 if (CONST_INT_P (lo)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1972 return mode != SImode; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1973 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1974 if (!MEM_P (lo)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1975 return false; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1976 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1977 if (MEM_VOLATILE_P (lo) || MEM_VOLATILE_P (hi)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1978 return false; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1979 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1980 lo = XEXP (lo, 0); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1981 hi = XEXP (hi, 0); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1982 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1983 if (GET_CODE (lo) == POST_INC /* || GET_CODE (lo) == PRE_DEC */) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1984 return rtx_equal_p (lo, hi); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1985 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1986 switch (GET_CODE (lo)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1987 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1988 case REG: |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1989 case SYMBOL_REF: |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1990 lo_offset = 0; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1991 break; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1992 case CONST: |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1993 lo = XEXP (lo, 0); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1994 /* FALLTHROUGH */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1995 case PLUS: |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1996 if (!CONST_INT_P (XEXP (lo, 1))) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1997 return false; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1998 lo_offset = INTVAL (XEXP (lo, 1)); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
1999 lo = XEXP (lo, 0); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2000 break; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2001 default: |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2002 return false; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2003 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2004 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2005 switch (GET_CODE (hi)) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2006 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2007 case REG: |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2008 case SYMBOL_REF: |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2009 hi_offset = 0; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2010 break; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2011 case CONST: |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2012 hi = XEXP (hi, 0); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2013 /* FALLTHROUGH */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2014 case PLUS: |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2015 if (!CONST_INT_P (XEXP (hi, 1))) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2016 return false; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2017 hi_offset = INTVAL (XEXP (hi, 1)); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2018 hi = XEXP (hi, 0); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2019 break; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2020 default: |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2021 return false; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2022 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2023 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2024 if (GET_CODE (lo) == MULT || GET_CODE (lo) == PLUS) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2025 return false; |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2026 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2027 return rtx_equal_p (lo, hi) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2028 && hi_offset - lo_offset == GET_MODE_SIZE (mode); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2029 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2030 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2031 /* Output assembler code for a block containing the constant parts |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2032 of a trampoline, leaving space for the variable parts. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2033 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2034 /* On the VAX, the trampoline contains an entry mask and two instructions: |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2035 .word NN |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2036 movl $STATIC,r0 (store the functions static chain) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2037 jmp *$FUNCTION (jump to function code at address FUNCTION) */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2038 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2039 static void |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2040 vax_asm_trampoline_template (FILE *f ATTRIBUTE_UNUSED) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2041 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2042 assemble_aligned_integer (2, const0_rtx); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2043 assemble_aligned_integer (2, GEN_INT (0x8fd0)); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2044 assemble_aligned_integer (4, const0_rtx); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2045 assemble_aligned_integer (1, GEN_INT (0x50 + STATIC_CHAIN_REGNUM)); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2046 assemble_aligned_integer (2, GEN_INT (0x9f17)); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2047 assemble_aligned_integer (4, const0_rtx); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2048 } |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2049 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2050 /* We copy the register-mask from the function's pure code |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2051 to the start of the trampoline. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2052 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2053 static void |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2054 vax_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2055 { |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2056 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
19
diff
changeset
|
2057 rtx mem; |
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2058 |
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2059 emit_block_move (m_tramp, assemble_trampoline_template (), |
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2060 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); |
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2061 |
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2062 mem = adjust_address (m_tramp, HImode, 0); |
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2063 emit_move_insn (mem, gen_const_mem (HImode, fnaddr)); |
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2064 |
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2065 mem = adjust_address (m_tramp, SImode, 4); |
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2066 emit_move_insn (mem, cxt); |
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2067 mem = adjust_address (m_tramp, SImode, 11); |
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2068 emit_move_insn (mem, plus_constant (fnaddr, 2)); |
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2069 emit_insn (gen_sync_istream ()); |
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2070 } |
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2071 |