Mercurial > hg > CbC > CbC_gcc
annotate gcc/ira-costs.c @ 55:77e2b8dfacca gcc-4.4.5
update it from 4.4.3 to 4.5.0
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Fri, 12 Feb 2010 23:39:51 +0900 |
| parents | 58ad6c70ea60 |
| children | b7f97abdc517 |
| rev | line source |
|---|---|
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1 /* IRA hard register and memory cost calculation for allocnos or pseudos. |
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2 Copyright (C) 2006, 2007, 2008, 2009 |
| 0 | 3 Free Software Foundation, Inc. |
| 4 Contributed by Vladimir Makarov <vmakarov@redhat.com>. | |
| 5 | |
| 6 This file is part of GCC. | |
| 7 | |
| 8 GCC is free software; you can redistribute it and/or modify it under | |
| 9 the terms of the GNU General Public License as published by the Free | |
| 10 Software Foundation; either version 3, or (at your option) any later | |
| 11 version. | |
| 12 | |
| 13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
| 14 WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 16 for more details. | |
| 17 | |
| 18 You should have received a copy of the GNU General Public License | |
| 19 along with GCC; see the file COPYING3. If not see | |
| 20 <http://www.gnu.org/licenses/>. */ | |
| 21 | |
| 22 #include "config.h" | |
| 23 #include "system.h" | |
| 24 #include "coretypes.h" | |
| 25 #include "tm.h" | |
| 26 #include "hard-reg-set.h" | |
| 27 #include "rtl.h" | |
| 28 #include "expr.h" | |
| 29 #include "tm_p.h" | |
| 30 #include "flags.h" | |
| 31 #include "basic-block.h" | |
| 32 #include "regs.h" | |
| 33 #include "addresses.h" | |
| 34 #include "insn-config.h" | |
| 35 #include "recog.h" | |
| 36 #include "toplev.h" | |
| 37 #include "target.h" | |
| 38 #include "params.h" | |
| 39 #include "ira-int.h" | |
| 40 | |
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41 /* The flags is set up every time when we calculate pseudo register |
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42 classes through function ira_set_pseudo_classes. */ |
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43 static bool pseudo_classes_defined_p = false; |
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44 |
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45 /* TRUE if we work with allocnos. Otherwise we work with pseudos. */ |
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46 static bool allocno_p; |
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47 |
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48 /* Number of elements in arrays `in_inc_dec' and `costs'. */ |
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49 static int cost_elements_num; |
| 0 | 50 |
| 51 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
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52 /* Indexed by n, is TRUE if allocno or pseudo with number N is used in |
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53 an auto-inc or auto-dec context. */ |
| 0 | 54 static bool *in_inc_dec; |
| 55 #endif | |
| 56 | |
| 57 /* The `costs' struct records the cost of using hard registers of each | |
| 58 class considered for the calculation and of using memory for each | |
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59 allocno or pseudo. */ |
| 0 | 60 struct costs |
| 61 { | |
| 62 int mem_cost; | |
| 63 /* Costs for register classes start here. We process only some | |
| 64 register classes (cover classes on the 1st cost calculation | |
| 65 iteration and important classes on the 2nd iteration). */ | |
| 66 int cost[1]; | |
| 67 }; | |
| 68 | |
| 69 /* Initialized once. It is a maximal possible size of the allocated | |
| 70 struct costs. */ | |
| 71 static int max_struct_costs_size; | |
| 72 | |
| 73 /* Allocated and initialized once, and used to initialize cost values | |
| 74 for each insn. */ | |
| 75 static struct costs *init_cost; | |
| 76 | |
| 77 /* Allocated once, and used for temporary purposes. */ | |
| 78 static struct costs *temp_costs; | |
| 79 | |
| 80 /* Allocated once, and used for the cost calculation. */ | |
| 81 static struct costs *op_costs[MAX_RECOG_OPERANDS]; | |
| 82 static struct costs *this_op_costs[MAX_RECOG_OPERANDS]; | |
| 83 | |
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84 /* Costs of each class for each allocno or pseudo. */ |
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85 static struct costs *costs; |
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86 |
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87 /* Accumulated costs of each class for each allocno. */ |
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88 static struct costs *total_allocno_costs; |
| 0 | 89 |
| 90 /* Classes used for cost calculation. They may be different on | |
| 91 different iterations of the cost calculations or in different | |
| 92 optimization modes. */ | |
| 93 static enum reg_class *cost_classes; | |
| 94 | |
| 95 /* The size of the previous array. */ | |
| 96 static int cost_classes_num; | |
| 97 | |
| 98 /* Map: cost class -> order number (they start with 0) of the cost | |
| 99 class. The order number is negative for non-cost classes. */ | |
| 100 static int cost_class_nums[N_REG_CLASSES]; | |
| 101 | |
| 102 /* It is the current size of struct costs. */ | |
| 103 static int struct_costs_size; | |
| 104 | |
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105 /* Return pointer to structure containing costs of allocno or pseudo |
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106 with given NUM in array ARR. */ |
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107 #define COSTS(arr, num) \ |
| 0 | 108 ((struct costs *) ((char *) (arr) + (num) * struct_costs_size)) |
| 109 | |
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110 /* Return index in COSTS when processing reg with REGNO. */ |
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111 #define COST_INDEX(regno) (allocno_p \ |
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112 ? ALLOCNO_NUM (ira_curr_regno_allocno_map[regno]) \ |
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113 : (int) regno) |
| 0 | 114 |
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115 /* Record register class preferences of each allocno or pseudo. Null |
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116 value means no preferences. It happens on the 1st iteration of the |
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117 cost calculation. */ |
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118 static enum reg_class *pref; |
| 0 | 119 |
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120 /* Allocated buffers for pref. */ |
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121 static enum reg_class *pref_buffer; |
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122 |
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123 /* Record cover register class of each allocno with the same regno. */ |
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124 static enum reg_class *regno_cover_class; |
| 0 | 125 |
| 126 /* Execution frequency of the current insn. */ | |
| 127 static int frequency; | |
| 128 | |
| 129 | |
| 130 | |
| 131 /* Compute the cost of loading X into (if TO_P is TRUE) or from (if | |
| 132 TO_P is FALSE) a register of class RCLASS in mode MODE. X must not | |
| 133 be a pseudo register. */ | |
| 134 static int | |
| 135 copy_cost (rtx x, enum machine_mode mode, enum reg_class rclass, bool to_p, | |
| 136 secondary_reload_info *prev_sri) | |
| 137 { | |
| 138 secondary_reload_info sri; | |
| 139 enum reg_class secondary_class = NO_REGS; | |
| 140 | |
| 141 /* If X is a SCRATCH, there is actually nothing to move since we are | |
| 142 assuming optimal allocation. */ | |
| 143 if (GET_CODE (x) == SCRATCH) | |
| 144 return 0; | |
| 145 | |
| 146 /* Get the class we will actually use for a reload. */ | |
| 147 rclass = PREFERRED_RELOAD_CLASS (x, rclass); | |
| 148 | |
| 149 /* If we need a secondary reload for an intermediate, the cost is | |
| 150 that to load the input into the intermediate register, then to | |
| 151 copy it. */ | |
| 152 sri.prev_sri = prev_sri; | |
| 153 sri.extra_cost = 0; | |
| 154 secondary_class = targetm.secondary_reload (to_p, x, rclass, mode, &sri); | |
| 155 | |
| 156 if (secondary_class != NO_REGS) | |
| 157 { | |
| 158 if (!move_cost[mode]) | |
| 159 init_move_cost (mode); | |
| 160 return (move_cost[mode][secondary_class][rclass] + sri.extra_cost | |
| 161 + copy_cost (x, mode, secondary_class, to_p, &sri)); | |
| 162 } | |
| 163 | |
| 164 /* For memory, use the memory move cost, for (hard) registers, use | |
| 165 the cost to move between the register classes, and use 2 for | |
| 166 everything else (constants). */ | |
| 167 if (MEM_P (x) || rclass == NO_REGS) | |
| 168 return sri.extra_cost + ira_memory_move_cost[mode][rclass][to_p != 0]; | |
| 169 else if (REG_P (x)) | |
| 170 { | |
| 171 if (!move_cost[mode]) | |
| 172 init_move_cost (mode); | |
| 173 return (sri.extra_cost + move_cost[mode][REGNO_REG_CLASS (REGNO (x))][rclass]); | |
| 174 } | |
| 175 else | |
| 176 /* If this is a constant, we may eventually want to call rtx_cost | |
| 177 here. */ | |
| 178 return sri.extra_cost + COSTS_N_INSNS (1); | |
| 179 } | |
| 180 | |
| 181 | |
| 182 | |
| 183 /* Record the cost of using memory or hard registers of various | |
| 184 classes for the operands in INSN. | |
| 185 | |
| 186 N_ALTS is the number of alternatives. | |
| 187 N_OPS is the number of operands. | |
| 188 OPS is an array of the operands. | |
| 189 MODES are the modes of the operands, in case any are VOIDmode. | |
| 190 CONSTRAINTS are the constraints to use for the operands. This array | |
| 191 is modified by this procedure. | |
| 192 | |
| 193 This procedure works alternative by alternative. For each | |
| 194 alternative we assume that we will be able to allocate all allocnos | |
| 195 to their ideal register class and calculate the cost of using that | |
| 196 alternative. Then we compute, for each operand that is a | |
| 197 pseudo-register, the cost of having the allocno allocated to each | |
| 198 register class and using it in that alternative. To this cost is | |
| 199 added the cost of the alternative. | |
| 200 | |
| 201 The cost of each class for this insn is its lowest cost among all | |
| 202 the alternatives. */ | |
| 203 static void | |
| 204 record_reg_classes (int n_alts, int n_ops, rtx *ops, | |
| 205 enum machine_mode *modes, const char **constraints, | |
| 206 rtx insn, struct costs **op_costs, | |
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207 enum reg_class *pref) |
| 0 | 208 { |
| 209 int alt; | |
| 210 int i, j, k; | |
| 211 rtx set; | |
| 212 int insn_allows_mem[MAX_RECOG_OPERANDS]; | |
| 213 | |
| 214 for (i = 0; i < n_ops; i++) | |
| 215 insn_allows_mem[i] = 0; | |
| 216 | |
| 217 /* Process each alternative, each time minimizing an operand's cost | |
| 218 with the cost for each operand in that alternative. */ | |
| 219 for (alt = 0; alt < n_alts; alt++) | |
| 220 { | |
| 221 enum reg_class classes[MAX_RECOG_OPERANDS]; | |
| 222 int allows_mem[MAX_RECOG_OPERANDS]; | |
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223 enum reg_class rclass; |
| 0 | 224 int alt_fail = 0; |
| 225 int alt_cost = 0, op_cost_add; | |
| 226 | |
| 227 for (i = 0; i < n_ops; i++) | |
| 228 { | |
| 229 unsigned char c; | |
| 230 const char *p = constraints[i]; | |
| 231 rtx op = ops[i]; | |
| 232 enum machine_mode mode = modes[i]; | |
| 233 int allows_addr = 0; | |
| 234 int win = 0; | |
| 235 | |
| 236 /* Initially show we know nothing about the register class. */ | |
| 237 classes[i] = NO_REGS; | |
| 238 allows_mem[i] = 0; | |
| 239 | |
| 240 /* If this operand has no constraints at all, we can | |
| 241 conclude nothing about it since anything is valid. */ | |
| 242 if (*p == 0) | |
| 243 { | |
| 244 if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
| 245 memset (this_op_costs[i], 0, struct_costs_size); | |
| 246 continue; | |
| 247 } | |
| 248 | |
| 249 /* If this alternative is only relevant when this operand | |
| 250 matches a previous operand, we do different things | |
| 251 depending on whether this operand is a allocno-reg or not. | |
| 252 We must process any modifiers for the operand before we | |
| 253 can make this test. */ | |
| 254 while (*p == '%' || *p == '=' || *p == '+' || *p == '&') | |
| 255 p++; | |
| 256 | |
| 257 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) | |
| 258 { | |
| 259 /* Copy class and whether memory is allowed from the | |
| 260 matching alternative. Then perform any needed cost | |
| 261 computations and/or adjustments. */ | |
| 262 j = p[0] - '0'; | |
| 263 classes[i] = classes[j]; | |
| 264 allows_mem[i] = allows_mem[j]; | |
| 265 if (allows_mem[i]) | |
| 266 insn_allows_mem[i] = 1; | |
| 267 | |
| 268 if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER) | |
| 269 { | |
| 270 /* If this matches the other operand, we have no | |
| 271 added cost and we win. */ | |
| 272 if (rtx_equal_p (ops[j], op)) | |
| 273 win = 1; | |
| 274 /* If we can put the other operand into a register, | |
| 275 add to the cost of this alternative the cost to | |
| 276 copy this operand to the register used for the | |
| 277 other operand. */ | |
| 278 else if (classes[j] != NO_REGS) | |
| 279 { | |
| 280 alt_cost += copy_cost (op, mode, classes[j], 1, NULL); | |
| 281 win = 1; | |
| 282 } | |
| 283 } | |
| 284 else if (! REG_P (ops[j]) | |
| 285 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) | |
| 286 { | |
| 287 /* This op is an allocno but the one it matches is | |
| 288 not. */ | |
| 289 | |
| 290 /* If we can't put the other operand into a | |
| 291 register, this alternative can't be used. */ | |
| 292 | |
| 293 if (classes[j] == NO_REGS) | |
| 294 alt_fail = 1; | |
| 295 /* Otherwise, add to the cost of this alternative | |
| 296 the cost to copy the other operand to the hard | |
| 297 register used for this operand. */ | |
| 298 else | |
| 299 alt_cost += copy_cost (ops[j], mode, classes[j], 1, NULL); | |
| 300 } | |
| 301 else | |
| 302 { | |
| 303 /* The costs of this operand are not the same as the | |
| 304 other operand since move costs are not symmetric. | |
| 305 Moreover, if we cannot tie them, this alternative | |
| 306 needs to do a copy, which is one insn. */ | |
| 307 struct costs *pp = this_op_costs[i]; | |
| 308 | |
| 309 for (k = 0; k < cost_classes_num; k++) | |
| 310 { | |
| 311 rclass = cost_classes[k]; | |
| 312 pp->cost[k] | |
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313 = (((recog_data.operand_type[i] != OP_OUT |
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314 ? ira_get_may_move_cost (mode, rclass, |
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315 classes[i], true) : 0) |
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316 + (recog_data.operand_type[i] != OP_IN |
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317 ? ira_get_may_move_cost (mode, classes[i], |
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318 rclass, false) : 0)) |
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319 * frequency); |
| 0 | 320 } |
| 321 | |
| 322 /* If the alternative actually allows memory, make | |
| 323 things a bit cheaper since we won't need an extra | |
| 324 insn to load it. */ | |
| 325 pp->mem_cost | |
| 326 = ((recog_data.operand_type[i] != OP_IN | |
| 327 ? ira_memory_move_cost[mode][classes[i]][0] : 0) | |
| 328 + (recog_data.operand_type[i] != OP_OUT | |
| 329 ? ira_memory_move_cost[mode][classes[i]][1] : 0) | |
| 330 - allows_mem[i]) * frequency; | |
| 331 | |
| 332 /* If we have assigned a class to this allocno in our | |
| 333 first pass, add a cost to this alternative | |
| 334 corresponding to what we would add if this allocno | |
| 335 were not in the appropriate class. We could use | |
| 336 cover class here but it is less accurate | |
| 337 approximation. */ | |
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338 if (pref) |
| 0 | 339 { |
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340 enum reg_class pref_class = pref[COST_INDEX (REGNO (op))]; |
| 0 | 341 |
| 342 if (pref_class == NO_REGS) | |
| 343 alt_cost | |
| 344 += ((recog_data.operand_type[i] != OP_IN | |
| 345 ? ira_memory_move_cost[mode][classes[i]][0] | |
| 346 : 0) | |
| 347 + (recog_data.operand_type[i] != OP_OUT | |
| 348 ? ira_memory_move_cost[mode][classes[i]][1] | |
| 349 : 0)); | |
| 350 else if (ira_reg_class_intersect | |
| 351 [pref_class][classes[i]] == NO_REGS) | |
|
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352 alt_cost += ira_get_register_move_cost (mode, |
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353 pref_class, |
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354 classes[i]); |
| 0 | 355 } |
| 356 if (REGNO (ops[i]) != REGNO (ops[j]) | |
| 357 && ! find_reg_note (insn, REG_DEAD, op)) | |
| 358 alt_cost += 2; | |
| 359 | |
| 360 /* This is in place of ordinary cost computation for | |
| 361 this operand, so skip to the end of the | |
| 362 alternative (should be just one character). */ | |
| 363 while (*p && *p++ != ',') | |
| 364 ; | |
| 365 | |
| 366 constraints[i] = p; | |
| 367 continue; | |
| 368 } | |
| 369 } | |
|
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370 |
| 0 | 371 /* Scan all the constraint letters. See if the operand |
| 372 matches any of the constraints. Collect the valid | |
| 373 register classes and see if this operand accepts | |
| 374 memory. */ | |
| 375 while ((c = *p)) | |
| 376 { | |
| 377 switch (c) | |
| 378 { | |
| 379 case ',': | |
| 380 break; | |
| 381 case '*': | |
| 382 /* Ignore the next letter for this pass. */ | |
| 383 c = *++p; | |
| 384 break; | |
| 385 | |
| 386 case '?': | |
| 387 alt_cost += 2; | |
| 388 case '!': case '#': case '&': | |
| 389 case '0': case '1': case '2': case '3': case '4': | |
| 390 case '5': case '6': case '7': case '8': case '9': | |
| 391 break; | |
| 392 | |
| 393 case 'p': | |
| 394 allows_addr = 1; | |
| 395 win = address_operand (op, GET_MODE (op)); | |
| 396 /* We know this operand is an address, so we want it | |
| 397 to be allocated to a register that can be the | |
| 398 base of an address, i.e. BASE_REG_CLASS. */ | |
| 399 classes[i] | |
| 400 = ira_reg_class_union[classes[i]] | |
| 401 [base_reg_class (VOIDmode, ADDRESS, SCRATCH)]; | |
| 402 break; | |
| 403 | |
| 404 case 'm': case 'o': case 'V': | |
| 405 /* It doesn't seem worth distinguishing between | |
| 406 offsettable and non-offsettable addresses | |
| 407 here. */ | |
| 408 insn_allows_mem[i] = allows_mem[i] = 1; | |
| 409 if (MEM_P (op)) | |
| 410 win = 1; | |
| 411 break; | |
| 412 | |
| 413 case '<': | |
| 414 if (MEM_P (op) | |
| 415 && (GET_CODE (XEXP (op, 0)) == PRE_DEC | |
| 416 || GET_CODE (XEXP (op, 0)) == POST_DEC)) | |
| 417 win = 1; | |
| 418 break; | |
| 419 | |
| 420 case '>': | |
| 421 if (MEM_P (op) | |
| 422 && (GET_CODE (XEXP (op, 0)) == PRE_INC | |
| 423 || GET_CODE (XEXP (op, 0)) == POST_INC)) | |
| 424 win = 1; | |
| 425 break; | |
| 426 | |
| 427 case 'E': | |
| 428 case 'F': | |
| 429 if (GET_CODE (op) == CONST_DOUBLE | |
| 430 || (GET_CODE (op) == CONST_VECTOR | |
| 431 && (GET_MODE_CLASS (GET_MODE (op)) | |
| 432 == MODE_VECTOR_FLOAT))) | |
| 433 win = 1; | |
| 434 break; | |
| 435 | |
| 436 case 'G': | |
| 437 case 'H': | |
| 438 if (GET_CODE (op) == CONST_DOUBLE | |
| 439 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p)) | |
| 440 win = 1; | |
| 441 break; | |
| 442 | |
| 443 case 's': | |
|
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444 if (CONST_INT_P (op) |
| 0 | 445 || (GET_CODE (op) == CONST_DOUBLE |
| 446 && GET_MODE (op) == VOIDmode)) | |
| 447 break; | |
| 448 | |
| 449 case 'i': | |
| 450 if (CONSTANT_P (op) | |
| 451 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))) | |
| 452 win = 1; | |
| 453 break; | |
| 454 | |
| 455 case 'n': | |
|
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456 if (CONST_INT_P (op) |
| 0 | 457 || (GET_CODE (op) == CONST_DOUBLE |
| 458 && GET_MODE (op) == VOIDmode)) | |
| 459 win = 1; | |
| 460 break; | |
| 461 | |
| 462 case 'I': | |
| 463 case 'J': | |
| 464 case 'K': | |
| 465 case 'L': | |
| 466 case 'M': | |
| 467 case 'N': | |
| 468 case 'O': | |
| 469 case 'P': | |
|
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470 if (CONST_INT_P (op) |
| 0 | 471 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p)) |
| 472 win = 1; | |
| 473 break; | |
| 474 | |
| 475 case 'X': | |
| 476 win = 1; | |
| 477 break; | |
| 478 | |
| 479 case 'g': | |
| 480 if (MEM_P (op) | |
| 481 || (CONSTANT_P (op) | |
| 482 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)))) | |
| 483 win = 1; | |
| 484 insn_allows_mem[i] = allows_mem[i] = 1; | |
| 485 case 'r': | |
| 486 classes[i] = ira_reg_class_union[classes[i]][GENERAL_REGS]; | |
| 487 break; | |
| 488 | |
| 489 default: | |
| 490 if (REG_CLASS_FROM_CONSTRAINT (c, p) != NO_REGS) | |
| 491 classes[i] = ira_reg_class_union[classes[i]] | |
| 492 [REG_CLASS_FROM_CONSTRAINT (c, p)]; | |
| 493 #ifdef EXTRA_CONSTRAINT_STR | |
| 494 else if (EXTRA_CONSTRAINT_STR (op, c, p)) | |
| 495 win = 1; | |
| 496 | |
| 497 if (EXTRA_MEMORY_CONSTRAINT (c, p)) | |
| 498 { | |
| 499 /* Every MEM can be reloaded to fit. */ | |
| 500 insn_allows_mem[i] = allows_mem[i] = 1; | |
| 501 if (MEM_P (op)) | |
| 502 win = 1; | |
| 503 } | |
| 504 if (EXTRA_ADDRESS_CONSTRAINT (c, p)) | |
| 505 { | |
| 506 /* Every address can be reloaded to fit. */ | |
| 507 allows_addr = 1; | |
| 508 if (address_operand (op, GET_MODE (op))) | |
| 509 win = 1; | |
| 510 /* We know this operand is an address, so we | |
| 511 want it to be allocated to a hard register | |
| 512 that can be the base of an address, | |
| 513 i.e. BASE_REG_CLASS. */ | |
| 514 classes[i] | |
| 515 = ira_reg_class_union[classes[i]] | |
| 516 [base_reg_class (VOIDmode, ADDRESS, SCRATCH)]; | |
| 517 } | |
| 518 #endif | |
| 519 break; | |
| 520 } | |
| 521 p += CONSTRAINT_LEN (c, p); | |
| 522 if (c == ',') | |
| 523 break; | |
| 524 } | |
| 525 | |
| 526 constraints[i] = p; | |
| 527 | |
| 528 /* How we account for this operand now depends on whether it | |
| 529 is a pseudo register or not. If it is, we first check if | |
| 530 any register classes are valid. If not, we ignore this | |
| 531 alternative, since we want to assume that all allocnos get | |
| 532 allocated for register preferencing. If some register | |
| 533 class is valid, compute the costs of moving the allocno | |
| 534 into that class. */ | |
| 535 if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) | |
| 536 { | |
| 537 if (classes[i] == NO_REGS) | |
| 538 { | |
| 539 /* We must always fail if the operand is a REG, but | |
| 540 we did not find a suitable class. | |
| 541 | |
| 542 Otherwise we may perform an uninitialized read | |
| 543 from this_op_costs after the `continue' statement | |
| 544 below. */ | |
| 545 alt_fail = 1; | |
| 546 } | |
| 547 else | |
| 548 { | |
| 549 struct costs *pp = this_op_costs[i]; | |
| 550 | |
| 551 for (k = 0; k < cost_classes_num; k++) | |
| 552 { | |
| 553 rclass = cost_classes[k]; | |
| 554 pp->cost[k] | |
|
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555 = (((recog_data.operand_type[i] != OP_OUT |
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556 ? ira_get_may_move_cost (mode, rclass, |
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557 classes[i], true) : 0) |
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558 + (recog_data.operand_type[i] != OP_IN |
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559 ? ira_get_may_move_cost (mode, classes[i], |
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560 rclass, false) : 0)) |
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561 * frequency); |
| 0 | 562 } |
| 563 | |
| 564 /* If the alternative actually allows memory, make | |
| 565 things a bit cheaper since we won't need an extra | |
| 566 insn to load it. */ | |
| 567 pp->mem_cost | |
| 568 = ((recog_data.operand_type[i] != OP_IN | |
| 569 ? ira_memory_move_cost[mode][classes[i]][0] : 0) | |
| 570 + (recog_data.operand_type[i] != OP_OUT | |
| 571 ? ira_memory_move_cost[mode][classes[i]][1] : 0) | |
| 572 - allows_mem[i]) * frequency; | |
| 573 /* If we have assigned a class to this allocno in our | |
| 574 first pass, add a cost to this alternative | |
| 575 corresponding to what we would add if this allocno | |
| 576 were not in the appropriate class. We could use | |
| 577 cover class here but it is less accurate | |
| 578 approximation. */ | |
|
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579 if (pref) |
| 0 | 580 { |
|
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581 enum reg_class pref_class = pref[COST_INDEX (REGNO (op))]; |
| 0 | 582 |
| 583 if (pref_class == NO_REGS) | |
| 584 alt_cost | |
| 585 += ((recog_data.operand_type[i] != OP_IN | |
| 586 ? ira_memory_move_cost[mode][classes[i]][0] | |
| 587 : 0) | |
| 588 + (recog_data.operand_type[i] != OP_OUT | |
| 589 ? ira_memory_move_cost[mode][classes[i]][1] | |
| 590 : 0)); | |
| 591 else if (ira_reg_class_intersect[pref_class][classes[i]] | |
| 592 == NO_REGS) | |
|
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593 alt_cost += ira_get_register_move_cost (mode, |
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594 pref_class, |
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595 classes[i]); |
| 0 | 596 } |
| 597 } | |
| 598 } | |
| 599 | |
| 600 /* Otherwise, if this alternative wins, either because we | |
| 601 have already determined that or if we have a hard | |
| 602 register of the proper class, there is no cost for this | |
| 603 alternative. */ | |
| 604 else if (win || (REG_P (op) | |
| 605 && reg_fits_class_p (op, classes[i], | |
| 606 0, GET_MODE (op)))) | |
| 607 ; | |
| 608 | |
| 609 /* If registers are valid, the cost of this alternative | |
| 610 includes copying the object to and/or from a | |
| 611 register. */ | |
| 612 else if (classes[i] != NO_REGS) | |
| 613 { | |
| 614 if (recog_data.operand_type[i] != OP_OUT) | |
| 615 alt_cost += copy_cost (op, mode, classes[i], 1, NULL); | |
| 616 | |
| 617 if (recog_data.operand_type[i] != OP_IN) | |
| 618 alt_cost += copy_cost (op, mode, classes[i], 0, NULL); | |
| 619 } | |
| 620 /* The only other way this alternative can be used is if | |
| 621 this is a constant that could be placed into memory. */ | |
| 622 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) | |
| 623 alt_cost += ira_memory_move_cost[mode][classes[i]][1]; | |
| 624 else | |
| 625 alt_fail = 1; | |
| 626 } | |
| 627 | |
| 628 if (alt_fail) | |
| 629 continue; | |
| 630 | |
| 631 op_cost_add = alt_cost * frequency; | |
| 632 /* Finally, update the costs with the information we've | |
| 633 calculated about this alternative. */ | |
| 634 for (i = 0; i < n_ops; i++) | |
| 635 if (REG_P (ops[i]) && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
| 636 { | |
| 637 struct costs *pp = op_costs[i], *qq = this_op_costs[i]; | |
| 638 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); | |
| 639 | |
| 640 pp->mem_cost = MIN (pp->mem_cost, | |
| 641 (qq->mem_cost + op_cost_add) * scale); | |
| 642 | |
| 643 for (k = 0; k < cost_classes_num; k++) | |
| 644 pp->cost[k] | |
| 645 = MIN (pp->cost[k], (qq->cost[k] + op_cost_add) * scale); | |
| 646 } | |
| 647 } | |
| 648 | |
|
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649 if (allocno_p) |
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650 for (i = 0; i < n_ops; i++) |
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651 { |
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652 ira_allocno_t a; |
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653 rtx op = ops[i]; |
| 0 | 654 |
|
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655 if (! REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER) |
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656 continue; |
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657 a = ira_curr_regno_allocno_map [REGNO (op)]; |
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658 if (! ALLOCNO_BAD_SPILL_P (a) && insn_allows_mem[i] == 0) |
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659 ALLOCNO_BAD_SPILL_P (a) = true; |
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660 } |
| 0 | 661 |
| 662 /* If this insn is a single set copying operand 1 to operand 0 and | |
| 663 one operand is an allocno with the other a hard reg or an allocno | |
| 664 that prefers a hard register that is in its own register class | |
| 665 then we may want to adjust the cost of that register class to -1. | |
| 666 | |
| 667 Avoid the adjustment if the source does not die to avoid | |
| 668 stressing of register allocator by preferrencing two colliding | |
| 669 registers into single class. | |
| 670 | |
| 671 Also avoid the adjustment if a copy between hard registers of the | |
| 672 class is expensive (ten times the cost of a default copy is | |
| 673 considered arbitrarily expensive). This avoids losing when the | |
| 674 preferred class is very expensive as the source of a copy | |
| 675 instruction. */ | |
| 676 if ((set = single_set (insn)) != 0 | |
| 677 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) | |
| 678 && REG_P (ops[0]) && REG_P (ops[1]) | |
| 679 && find_regno_note (insn, REG_DEAD, REGNO (ops[1]))) | |
| 680 for (i = 0; i <= 1; i++) | |
| 681 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) | |
| 682 { | |
| 683 unsigned int regno = REGNO (ops[!i]); | |
| 684 enum machine_mode mode = GET_MODE (ops[!i]); | |
|
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685 enum reg_class rclass; |
| 0 | 686 unsigned int nr; |
| 687 | |
| 688 if (regno < FIRST_PSEUDO_REGISTER) | |
| 689 for (k = 0; k < cost_classes_num; k++) | |
| 690 { | |
| 691 rclass = cost_classes[k]; | |
| 692 if (TEST_HARD_REG_BIT (reg_class_contents[rclass], regno) | |
| 693 && (reg_class_size[rclass] | |
| 694 == (unsigned) CLASS_MAX_NREGS (rclass, mode))) | |
| 695 { | |
| 696 if (reg_class_size[rclass] == 1) | |
| 697 op_costs[i]->cost[k] = -frequency; | |
| 698 else | |
| 699 { | |
| 700 for (nr = 0; | |
| 701 nr < (unsigned) hard_regno_nregs[regno][mode]; | |
| 702 nr++) | |
| 703 if (! TEST_HARD_REG_BIT (reg_class_contents[rclass], | |
| 704 regno + nr)) | |
| 705 break; | |
|
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706 |
| 0 | 707 if (nr == (unsigned) hard_regno_nregs[regno][mode]) |
| 708 op_costs[i]->cost[k] = -frequency; | |
| 709 } | |
| 710 } | |
| 711 } | |
| 712 } | |
| 713 } | |
| 714 | |
| 715 | |
| 716 | |
| 717 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */ | |
| 718 static inline bool | |
| 719 ok_for_index_p_nonstrict (rtx reg) | |
| 720 { | |
| 721 unsigned regno = REGNO (reg); | |
| 722 | |
| 723 return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno); | |
| 724 } | |
| 725 | |
| 726 /* A version of regno_ok_for_base_p for use here, when all | |
| 727 pseudo-registers should count as OK. Arguments as for | |
| 728 regno_ok_for_base_p. */ | |
| 729 static inline bool | |
| 730 ok_for_base_p_nonstrict (rtx reg, enum machine_mode mode, | |
| 731 enum rtx_code outer_code, enum rtx_code index_code) | |
| 732 { | |
| 733 unsigned regno = REGNO (reg); | |
| 734 | |
| 735 if (regno >= FIRST_PSEUDO_REGISTER) | |
| 736 return true; | |
| 737 return ok_for_base_p_1 (regno, mode, outer_code, index_code); | |
| 738 } | |
| 739 | |
| 740 /* Record the pseudo registers we must reload into hard registers in a | |
| 741 subexpression of a memory address, X. | |
| 742 | |
| 743 If CONTEXT is 0, we are looking at the base part of an address, | |
| 744 otherwise we are looking at the index part. | |
| 745 | |
| 746 MODE is the mode of the memory reference; OUTER_CODE and INDEX_CODE | |
| 747 give the context that the rtx appears in. These three arguments | |
| 748 are passed down to base_reg_class. | |
| 749 | |
| 750 SCALE is twice the amount to multiply the cost by (it is twice so | |
| 751 we can represent half-cost adjustments). */ | |
| 752 static void | |
| 753 record_address_regs (enum machine_mode mode, rtx x, int context, | |
| 754 enum rtx_code outer_code, enum rtx_code index_code, | |
| 755 int scale) | |
| 756 { | |
| 757 enum rtx_code code = GET_CODE (x); | |
| 758 enum reg_class rclass; | |
| 759 | |
| 760 if (context == 1) | |
| 761 rclass = INDEX_REG_CLASS; | |
| 762 else | |
| 763 rclass = base_reg_class (mode, outer_code, index_code); | |
| 764 | |
| 765 switch (code) | |
| 766 { | |
| 767 case CONST_INT: | |
| 768 case CONST: | |
| 769 case CC0: | |
| 770 case PC: | |
| 771 case SYMBOL_REF: | |
| 772 case LABEL_REF: | |
| 773 return; | |
| 774 | |
| 775 case PLUS: | |
| 776 /* When we have an address that is a sum, we must determine | |
| 777 whether registers are "base" or "index" regs. If there is a | |
| 778 sum of two registers, we must choose one to be the "base". | |
| 779 Luckily, we can use the REG_POINTER to make a good choice | |
| 780 most of the time. We only need to do this on machines that | |
| 781 can have two registers in an address and where the base and | |
| 782 index register classes are different. | |
| 783 | |
| 784 ??? This code used to set REGNO_POINTER_FLAG in some cases, | |
| 785 but that seems bogus since it should only be set when we are | |
| 786 sure the register is being used as a pointer. */ | |
| 787 { | |
| 788 rtx arg0 = XEXP (x, 0); | |
| 789 rtx arg1 = XEXP (x, 1); | |
| 790 enum rtx_code code0 = GET_CODE (arg0); | |
| 791 enum rtx_code code1 = GET_CODE (arg1); | |
| 792 | |
| 793 /* Look inside subregs. */ | |
| 794 if (code0 == SUBREG) | |
| 795 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); | |
| 796 if (code1 == SUBREG) | |
| 797 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); | |
| 798 | |
| 799 /* If this machine only allows one register per address, it | |
| 800 must be in the first operand. */ | |
| 801 if (MAX_REGS_PER_ADDRESS == 1) | |
| 802 record_address_regs (mode, arg0, 0, PLUS, code1, scale); | |
| 803 | |
| 804 /* If index and base registers are the same on this machine, | |
| 805 just record registers in any non-constant operands. We | |
| 806 assume here, as well as in the tests below, that all | |
| 807 addresses are in canonical form. */ | |
| 808 else if (INDEX_REG_CLASS == base_reg_class (VOIDmode, PLUS, SCRATCH)) | |
| 809 { | |
| 810 record_address_regs (mode, arg0, context, PLUS, code1, scale); | |
| 811 if (! CONSTANT_P (arg1)) | |
| 812 record_address_regs (mode, arg1, context, PLUS, code0, scale); | |
| 813 } | |
| 814 | |
| 815 /* If the second operand is a constant integer, it doesn't | |
| 816 change what class the first operand must be. */ | |
| 817 else if (code1 == CONST_INT || code1 == CONST_DOUBLE) | |
| 818 record_address_regs (mode, arg0, context, PLUS, code1, scale); | |
| 819 /* If the second operand is a symbolic constant, the first | |
| 820 operand must be an index register. */ | |
| 821 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) | |
| 822 record_address_regs (mode, arg0, 1, PLUS, code1, scale); | |
| 823 /* If both operands are registers but one is already a hard | |
| 824 register of index or reg-base class, give the other the | |
| 825 class that the hard register is not. */ | |
| 826 else if (code0 == REG && code1 == REG | |
| 827 && REGNO (arg0) < FIRST_PSEUDO_REGISTER | |
| 828 && (ok_for_base_p_nonstrict (arg0, mode, PLUS, REG) | |
| 829 || ok_for_index_p_nonstrict (arg0))) | |
| 830 record_address_regs (mode, arg1, | |
| 831 ok_for_base_p_nonstrict (arg0, mode, PLUS, REG) | |
| 832 ? 1 : 0, | |
| 833 PLUS, REG, scale); | |
| 834 else if (code0 == REG && code1 == REG | |
| 835 && REGNO (arg1) < FIRST_PSEUDO_REGISTER | |
| 836 && (ok_for_base_p_nonstrict (arg1, mode, PLUS, REG) | |
| 837 || ok_for_index_p_nonstrict (arg1))) | |
| 838 record_address_regs (mode, arg0, | |
| 839 ok_for_base_p_nonstrict (arg1, mode, PLUS, REG) | |
| 840 ? 1 : 0, | |
| 841 PLUS, REG, scale); | |
| 842 /* If one operand is known to be a pointer, it must be the | |
| 843 base with the other operand the index. Likewise if the | |
| 844 other operand is a MULT. */ | |
| 845 else if ((code0 == REG && REG_POINTER (arg0)) || code1 == MULT) | |
| 846 { | |
| 847 record_address_regs (mode, arg0, 0, PLUS, code1, scale); | |
| 848 record_address_regs (mode, arg1, 1, PLUS, code0, scale); | |
| 849 } | |
| 850 else if ((code1 == REG && REG_POINTER (arg1)) || code0 == MULT) | |
| 851 { | |
| 852 record_address_regs (mode, arg0, 1, PLUS, code1, scale); | |
| 853 record_address_regs (mode, arg1, 0, PLUS, code0, scale); | |
| 854 } | |
| 855 /* Otherwise, count equal chances that each might be a base or | |
| 856 index register. This case should be rare. */ | |
| 857 else | |
| 858 { | |
| 859 record_address_regs (mode, arg0, 0, PLUS, code1, scale / 2); | |
| 860 record_address_regs (mode, arg0, 1, PLUS, code1, scale / 2); | |
| 861 record_address_regs (mode, arg1, 0, PLUS, code0, scale / 2); | |
| 862 record_address_regs (mode, arg1, 1, PLUS, code0, scale / 2); | |
| 863 } | |
| 864 } | |
| 865 break; | |
| 866 | |
| 867 /* Double the importance of an allocno that is incremented or | |
| 868 decremented, since it would take two extra insns if it ends | |
| 869 up in the wrong place. */ | |
| 870 case POST_MODIFY: | |
| 871 case PRE_MODIFY: | |
| 872 record_address_regs (mode, XEXP (x, 0), 0, code, | |
| 873 GET_CODE (XEXP (XEXP (x, 1), 1)), 2 * scale); | |
| 874 if (REG_P (XEXP (XEXP (x, 1), 1))) | |
| 875 record_address_regs (mode, XEXP (XEXP (x, 1), 1), 1, code, REG, | |
| 876 2 * scale); | |
| 877 break; | |
| 878 | |
| 879 case POST_INC: | |
| 880 case PRE_INC: | |
| 881 case POST_DEC: | |
| 882 case PRE_DEC: | |
| 883 /* Double the importance of an allocno that is incremented or | |
| 884 decremented, since it would take two extra insns if it ends | |
| 885 up in the wrong place. If the operand is a pseudo-register, | |
| 886 show it is being used in an INC_DEC context. */ | |
| 887 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 888 if (REG_P (XEXP (x, 0)) | |
| 889 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) | |
|
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890 in_inc_dec[COST_INDEX (REGNO (XEXP (x, 0)))] = true; |
| 0 | 891 #endif |
| 892 record_address_regs (mode, XEXP (x, 0), 0, code, SCRATCH, 2 * scale); | |
| 893 break; | |
| 894 | |
| 895 case REG: | |
| 896 { | |
| 897 struct costs *pp; | |
|
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898 enum reg_class i; |
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899 int k; |
| 0 | 900 |
| 901 if (REGNO (x) < FIRST_PSEUDO_REGISTER) | |
| 902 break; | |
| 903 | |
|
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904 if (allocno_p) |
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905 ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map[REGNO (x)]) = true; |
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906 pp = COSTS (costs, COST_INDEX (REGNO (x))); |
| 0 | 907 pp->mem_cost += (ira_memory_move_cost[Pmode][rclass][1] * scale) / 2; |
| 908 for (k = 0; k < cost_classes_num; k++) | |
| 909 { | |
| 910 i = cost_classes[k]; | |
| 911 pp->cost[k] | |
|
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912 += (ira_get_may_move_cost (Pmode, i, rclass, true) * scale) / 2; |
| 0 | 913 } |
| 914 } | |
| 915 break; | |
| 916 | |
| 917 default: | |
| 918 { | |
| 919 const char *fmt = GET_RTX_FORMAT (code); | |
| 920 int i; | |
| 921 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
| 922 if (fmt[i] == 'e') | |
| 923 record_address_regs (mode, XEXP (x, i), context, code, SCRATCH, | |
| 924 scale); | |
| 925 } | |
| 926 } | |
| 927 } | |
| 928 | |
| 929 | |
| 930 | |
| 931 /* Calculate the costs of insn operands. */ | |
| 932 static void | |
|
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933 record_operand_costs (rtx insn, struct costs **op_costs, enum reg_class *pref) |
| 0 | 934 { |
| 935 const char *constraints[MAX_RECOG_OPERANDS]; | |
| 936 enum machine_mode modes[MAX_RECOG_OPERANDS]; | |
| 937 int i; | |
| 938 | |
| 939 for (i = 0; i < recog_data.n_operands; i++) | |
| 940 { | |
| 941 constraints[i] = recog_data.constraints[i]; | |
| 942 modes[i] = recog_data.operand_mode[i]; | |
| 943 } | |
| 944 | |
| 945 /* If we get here, we are set up to record the costs of all the | |
| 946 operands for this insn. Start by initializing the costs. Then | |
| 947 handle any address registers. Finally record the desired classes | |
| 948 for any allocnos, doing it twice if some pair of operands are | |
| 949 commutative. */ | |
| 950 for (i = 0; i < recog_data.n_operands; i++) | |
| 951 { | |
| 952 memcpy (op_costs[i], init_cost, struct_costs_size); | |
| 953 | |
| 954 if (GET_CODE (recog_data.operand[i]) == SUBREG) | |
| 955 recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]); | |
| 956 | |
| 957 if (MEM_P (recog_data.operand[i])) | |
| 958 record_address_regs (GET_MODE (recog_data.operand[i]), | |
| 959 XEXP (recog_data.operand[i], 0), | |
| 960 0, MEM, SCRATCH, frequency * 2); | |
| 961 else if (constraints[i][0] == 'p' | |
| 962 || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], | |
| 963 constraints[i])) | |
| 964 record_address_regs (VOIDmode, recog_data.operand[i], 0, ADDRESS, | |
| 965 SCRATCH, frequency * 2); | |
| 966 } | |
| 967 | |
| 968 /* Check for commutative in a separate loop so everything will have | |
| 969 been initialized. We must do this even if one operand is a | |
| 970 constant--see addsi3 in m68k.md. */ | |
| 971 for (i = 0; i < (int) recog_data.n_operands - 1; i++) | |
| 972 if (constraints[i][0] == '%') | |
| 973 { | |
| 974 const char *xconstraints[MAX_RECOG_OPERANDS]; | |
| 975 int j; | |
| 976 | |
| 977 /* Handle commutative operands by swapping the constraints. | |
| 978 We assume the modes are the same. */ | |
| 979 for (j = 0; j < recog_data.n_operands; j++) | |
| 980 xconstraints[j] = constraints[j]; | |
| 981 | |
| 982 xconstraints[i] = constraints[i+1]; | |
| 983 xconstraints[i+1] = constraints[i]; | |
| 984 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
| 985 recog_data.operand, modes, | |
|
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986 xconstraints, insn, op_costs, pref); |
| 0 | 987 } |
| 988 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, | |
| 989 recog_data.operand, modes, | |
|
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990 constraints, insn, op_costs, pref); |
| 0 | 991 } |
| 992 | |
| 993 | |
| 994 | |
| 995 /* Process one insn INSN. Scan it and record each time it would save | |
| 996 code to put a certain allocnos in a certain class. Return the last | |
| 997 insn processed, so that the scan can be continued from there. */ | |
| 998 static rtx | |
| 999 scan_one_insn (rtx insn) | |
| 1000 { | |
| 1001 enum rtx_code pat_code; | |
| 1002 rtx set, note; | |
| 1003 int i, k; | |
| 1004 | |
|
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1005 if (!NONDEBUG_INSN_P (insn)) |
| 0 | 1006 return insn; |
| 1007 | |
| 1008 pat_code = GET_CODE (PATTERN (insn)); | |
| 1009 if (pat_code == USE || pat_code == CLOBBER || pat_code == ASM_INPUT | |
| 1010 || pat_code == ADDR_VEC || pat_code == ADDR_DIFF_VEC) | |
| 1011 return insn; | |
| 1012 | |
| 1013 set = single_set (insn); | |
| 1014 extract_insn (insn); | |
| 1015 | |
| 1016 /* If this insn loads a parameter from its stack slot, then it | |
| 1017 represents a savings, rather than a cost, if the parameter is | |
| 1018 stored in memory. Record this fact. */ | |
| 1019 if (set != 0 && REG_P (SET_DEST (set)) && MEM_P (SET_SRC (set)) | |
| 1020 && (note = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != NULL_RTX | |
| 1021 && MEM_P (XEXP (note, 0))) | |
| 1022 { | |
| 1023 enum reg_class cl = GENERAL_REGS; | |
| 1024 rtx reg = SET_DEST (set); | |
|
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1025 int num = COST_INDEX (REGNO (reg)); |
| 0 | 1026 |
|
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1027 if (pref) |
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1028 cl = pref[num]; |
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1029 COSTS (costs, num)->mem_cost |
| 0 | 1030 -= ira_memory_move_cost[GET_MODE (reg)][cl][1] * frequency; |
| 1031 record_address_regs (GET_MODE (SET_SRC (set)), XEXP (SET_SRC (set), 0), | |
| 1032 0, MEM, SCRATCH, frequency * 2); | |
| 1033 } | |
| 1034 | |
|
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1035 record_operand_costs (insn, op_costs, pref); |
| 0 | 1036 |
| 1037 /* Now add the cost for each operand to the total costs for its | |
| 1038 allocno. */ | |
| 1039 for (i = 0; i < recog_data.n_operands; i++) | |
| 1040 if (REG_P (recog_data.operand[i]) | |
| 1041 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER) | |
| 1042 { | |
| 1043 int regno = REGNO (recog_data.operand[i]); | |
|
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1044 struct costs *p = COSTS (costs, COST_INDEX (regno)); |
| 0 | 1045 struct costs *q = op_costs[i]; |
| 1046 | |
| 1047 p->mem_cost += q->mem_cost; | |
| 1048 for (k = 0; k < cost_classes_num; k++) | |
| 1049 p->cost[k] += q->cost[k]; | |
| 1050 } | |
| 1051 | |
| 1052 return insn; | |
| 1053 } | |
| 1054 | |
| 1055 | |
| 1056 | |
| 1057 /* Print allocnos costs to file F. */ | |
| 1058 static void | |
|
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1059 print_allocno_costs (FILE *f) |
| 0 | 1060 { |
| 1061 int k; | |
| 1062 ira_allocno_t a; | |
| 1063 ira_allocno_iterator ai; | |
| 1064 | |
|
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1065 ira_assert (allocno_p); |
| 0 | 1066 fprintf (f, "\n"); |
| 1067 FOR_EACH_ALLOCNO (a, ai) | |
| 1068 { | |
| 1069 int i, rclass; | |
| 1070 basic_block bb; | |
| 1071 int regno = ALLOCNO_REGNO (a); | |
| 1072 | |
| 1073 i = ALLOCNO_NUM (a); | |
| 1074 fprintf (f, " a%d(r%d,", i, regno); | |
| 1075 if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) | |
| 1076 fprintf (f, "b%d", bb->index); | |
| 1077 else | |
| 1078 fprintf (f, "l%d", ALLOCNO_LOOP_TREE_NODE (a)->loop->num); | |
| 1079 fprintf (f, ") costs:"); | |
| 1080 for (k = 0; k < cost_classes_num; k++) | |
| 1081 { | |
| 1082 rclass = cost_classes[k]; | |
| 1083 if (contains_reg_of_mode[rclass][PSEUDO_REGNO_MODE (regno)] | |
| 1084 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 1085 && (! in_inc_dec[i] || ! forbidden_inc_dec_class[rclass]) | |
| 1086 #endif | |
| 1087 #ifdef CANNOT_CHANGE_MODE_CLASS | |
| 1088 && ! invalid_mode_change_p (regno, (enum reg_class) rclass, | |
| 1089 PSEUDO_REGNO_MODE (regno)) | |
| 1090 #endif | |
| 1091 ) | |
| 1092 { | |
| 1093 fprintf (f, " %s:%d", reg_class_names[rclass], | |
|
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1094 COSTS (costs, i)->cost[k]); |
| 0 | 1095 if (flag_ira_region == IRA_REGION_ALL |
| 1096 || flag_ira_region == IRA_REGION_MIXED) | |
|
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1097 fprintf (f, ",%d", COSTS (total_allocno_costs, i)->cost[k]); |
| 0 | 1098 } |
| 1099 } | |
|
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1100 fprintf (f, " MEM:%i\n", COSTS (costs, i)->mem_cost); |
| 0 | 1101 } |
| 1102 } | |
| 1103 | |
|
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1104 /* Print pseudo costs to file F. */ |
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1105 static void |
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1106 print_pseudo_costs (FILE *f) |
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1107 { |
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1108 int regno, k; |
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1109 int rclass; |
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1110 |
|
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|
1111 ira_assert (! allocno_p); |
|
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|
1112 fprintf (f, "\n"); |
|
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|
1113 for (regno = max_reg_num () - 1; regno >= FIRST_PSEUDO_REGISTER; regno--) |
|
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|
1114 { |
|
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|
1115 if (regno_reg_rtx[regno] == NULL_RTX) |
|
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|
1116 continue; |
|
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|
1117 fprintf (f, " r%d costs:", regno); |
|
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|
1118 for (k = 0; k < cost_classes_num; k++) |
|
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|
1119 { |
|
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|
1120 rclass = cost_classes[k]; |
|
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|
1121 if (contains_reg_of_mode[rclass][PSEUDO_REGNO_MODE (regno)] |
|
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diff
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|
1122 #ifdef FORBIDDEN_INC_DEC_CLASSES |
|
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|
1123 && (! in_inc_dec[regno] || ! forbidden_inc_dec_class[rclass]) |
|
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|
1124 #endif |
|
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|
1125 #ifdef CANNOT_CHANGE_MODE_CLASS |
|
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|
1126 && ! invalid_mode_change_p (regno, (enum reg_class) rclass, |
|
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|
1127 PSEUDO_REGNO_MODE (regno)) |
|
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1128 #endif |
|
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1129 ) |
|
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|
1130 fprintf (f, " %s:%d", reg_class_names[rclass], |
|
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|
1131 COSTS (costs, regno)->cost[k]); |
|
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|
1132 } |
|
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1133 fprintf (f, " MEM:%i\n", COSTS (costs, regno)->mem_cost); |
|
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|
1134 } |
|
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|
1135 } |
|
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|
1136 |
|
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|
1137 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno |
|
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|
1138 costs. */ |
|
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|
1139 static void |
|
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|
1140 process_bb_for_costs (basic_block bb) |
|
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|
1141 { |
|
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|
1142 rtx insn; |
|
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|
1143 |
|
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|
1144 frequency = REG_FREQ_FROM_BB (bb); |
|
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|
1145 if (frequency == 0) |
|
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|
1146 frequency = 1; |
|
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|
1147 FOR_BB_INSNS (bb, insn) |
|
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|
1148 insn = scan_one_insn (insn); |
|
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|
1149 } |
|
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1150 |
| 0 | 1151 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno |
| 1152 costs. */ | |
| 1153 static void | |
| 1154 process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node) | |
| 1155 { | |
| 1156 basic_block bb; | |
| 1157 | |
| 1158 bb = loop_tree_node->bb; | |
|
55
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diff
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|
1159 if (bb != NULL) |
|
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|
1160 process_bb_for_costs (bb); |
| 0 | 1161 } |
| 1162 | |
|
55
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diff
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|
1163 /* Find costs of register classes and memory for allocnos or pseudos |
|
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|
1164 and their best costs. Set up preferred, alternative and cover |
|
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diff
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|
1165 classes for pseudos. */ |
| 0 | 1166 static void |
|
55
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|
1167 find_costs_and_classes (FILE *dump_file) |
| 0 | 1168 { |
|
55
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parents:
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diff
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|
1169 int i, k, start; |
| 0 | 1170 int pass; |
| 1171 basic_block bb; | |
| 1172 | |
| 1173 init_recog (); | |
| 1174 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
|
55
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|
1175 in_inc_dec = ira_allocate (sizeof (bool) * cost_elements_num); |
| 0 | 1176 #endif /* FORBIDDEN_INC_DEC_CLASSES */ |
|
55
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diff
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|
1177 pref = NULL; |
|
77e2b8dfacca
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|
1178 start = 0; |
|
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|
1179 if (!resize_reg_info () && allocno_p && pseudo_classes_defined_p) |
|
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|
1180 { |
|
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|
1181 ira_allocno_t a; |
|
77e2b8dfacca
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diff
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|
1182 ira_allocno_iterator ai; |
|
77e2b8dfacca
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diff
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|
1183 |
|
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diff
changeset
|
1184 pref = pref_buffer; |
|
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19
diff
changeset
|
1185 FOR_EACH_ALLOCNO (a, ai) |
|
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parents:
19
diff
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|
1186 pref[ALLOCNO_NUM (a)] = reg_preferred_class (ALLOCNO_REGNO (a)); |
|
77e2b8dfacca
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parents:
19
diff
changeset
|
1187 if (flag_expensive_optimizations) |
|
77e2b8dfacca
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19
diff
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|
1188 start = 1; |
|
77e2b8dfacca
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19
diff
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|
1189 } |
|
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parents:
19
diff
changeset
|
1190 if (allocno_p) |
|
77e2b8dfacca
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19
diff
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|
1191 /* Clear the flag for the next compiled function. */ |
|
77e2b8dfacca
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19
diff
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|
1192 pseudo_classes_defined_p = false; |
| 0 | 1193 /* Normally we scan the insns once and determine the best class to |
| 1194 use for each allocno. However, if -fexpensive-optimizations are | |
| 1195 on, we do so twice, the second time using the tentative best | |
| 1196 classes to guide the selection. */ | |
|
55
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19
diff
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|
1197 for (pass = start; pass <= flag_expensive_optimizations; pass++) |
| 0 | 1198 { |
|
55
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diff
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|
1199 if ((!allocno_p || internal_flag_ira_verbose > 0) && dump_file) |
|
77e2b8dfacca
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19
diff
changeset
|
1200 fprintf (dump_file, |
|
77e2b8dfacca
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diff
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|
1201 "\nPass %i for finding pseudo/allocno costs\n\n", pass); |
| 0 | 1202 /* We could use only cover classes. Unfortunately it does not |
| 1203 work well for some targets where some subclass of cover class | |
| 1204 is costly and wrong cover class is chosen. */ | |
| 1205 for (i = 0; i < N_REG_CLASSES; i++) | |
| 1206 cost_class_nums[i] = -1; | |
| 1207 for (cost_classes_num = 0; | |
| 1208 cost_classes_num < ira_important_classes_num; | |
| 1209 cost_classes_num++) | |
| 1210 { | |
| 1211 cost_classes[cost_classes_num] | |
| 1212 = ira_important_classes[cost_classes_num]; | |
| 1213 cost_class_nums[cost_classes[cost_classes_num]] | |
| 1214 = cost_classes_num; | |
| 1215 } | |
| 1216 struct_costs_size | |
| 1217 = sizeof (struct costs) + sizeof (int) * (cost_classes_num - 1); | |
| 1218 /* Zero out our accumulation of the cost of each class for each | |
| 1219 allocno. */ | |
|
55
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diff
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|
1220 memset (costs, 0, cost_elements_num * struct_costs_size); |
| 0 | 1221 #ifdef FORBIDDEN_INC_DEC_CLASSES |
|
55
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19
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|
1222 memset (in_inc_dec, 0, cost_elements_num * sizeof (bool)); |
| 0 | 1223 #endif |
| 1224 | |
|
55
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19
diff
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|
1225 if (allocno_p) |
|
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19
diff
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|
1226 { |
|
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19
diff
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|
1227 /* Scan the instructions and record each time it would save code |
|
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diff
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|
1228 to put a certain allocno in a certain class. */ |
|
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diff
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|
1229 ira_traverse_loop_tree (true, ira_loop_tree_root, |
|
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diff
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|
1230 process_bb_node_for_costs, NULL); |
| 0 | 1231 |
|
55
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diff
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|
1232 memcpy (total_allocno_costs, costs, |
|
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|
1233 max_struct_costs_size * ira_allocnos_num); |
|
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|
1234 } |
|
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|
1235 else |
|
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|
1236 { |
|
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|
1237 basic_block bb; |
|
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|
1238 |
|
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|
1239 FOR_EACH_BB (bb) |
|
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|
1240 process_bb_for_costs (bb); |
|
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|
1241 } |
|
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|
1242 |
| 0 | 1243 if (pass == 0) |
|
55
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|
1244 pref = pref_buffer; |
| 0 | 1245 |
| 1246 /* Now for each allocno look at how desirable each class is and | |
| 1247 find which class is preferred. */ | |
| 1248 for (i = max_reg_num () - 1; i >= FIRST_PSEUDO_REGISTER; i--) | |
| 1249 { | |
| 1250 ira_allocno_t a, parent_a; | |
| 1251 int rclass, a_num, parent_a_num; | |
| 1252 ira_loop_tree_node_t parent; | |
| 1253 int best_cost, allocno_cost; | |
| 1254 enum reg_class best, alt_class; | |
| 1255 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 1256 int inc_dec_p = false; | |
| 1257 #endif | |
| 1258 | |
|
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1259 if (! allocno_p) |
| 0 | 1260 { |
|
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1261 if (regno_reg_rtx[i] == NULL_RTX) |
|
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|
1262 continue; |
|
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|
1263 #ifdef FORBIDDEN_INC_DEC_CLASSES |
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1264 inc_dec_p = in_inc_dec[i]; |
|
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1265 #endif |
|
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1266 memcpy (temp_costs, COSTS (costs, i), struct_costs_size); |
|
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1267 } |
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1268 else |
|
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1269 { |
|
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1270 if (ira_regno_allocno_map[i] == NULL) |
|
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1271 continue; |
|
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1272 memset (temp_costs, 0, struct_costs_size); |
|
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1273 /* Find cost of all allocnos with the same regno. */ |
|
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1274 for (a = ira_regno_allocno_map[i]; |
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1275 a != NULL; |
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1276 a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) |
| 0 | 1277 { |
|
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1278 a_num = ALLOCNO_NUM (a); |
|
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1279 if ((flag_ira_region == IRA_REGION_ALL |
|
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1280 || flag_ira_region == IRA_REGION_MIXED) |
|
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1281 && (parent = ALLOCNO_LOOP_TREE_NODE (a)->parent) != NULL |
|
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1282 && (parent_a = parent->regno_allocno_map[i]) != NULL |
|
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1283 /* There are no caps yet. */ |
|
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1284 && bitmap_bit_p (ALLOCNO_LOOP_TREE_NODE |
|
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1285 (a)->border_allocnos, |
|
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1286 ALLOCNO_NUM (a))) |
|
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1287 { |
|
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1288 /* Propagate costs to upper levels in the region |
|
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1289 tree. */ |
|
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1290 parent_a_num = ALLOCNO_NUM (parent_a); |
|
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1291 for (k = 0; k < cost_classes_num; k++) |
|
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1292 COSTS (total_allocno_costs, parent_a_num)->cost[k] |
|
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1293 += COSTS (total_allocno_costs, a_num)->cost[k]; |
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1294 COSTS (total_allocno_costs, parent_a_num)->mem_cost |
|
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1295 += COSTS (total_allocno_costs, a_num)->mem_cost; |
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1296 } |
| 0 | 1297 for (k = 0; k < cost_classes_num; k++) |
|
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1298 temp_costs->cost[k] += COSTS (costs, a_num)->cost[k]; |
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1299 temp_costs->mem_cost += COSTS (costs, a_num)->mem_cost; |
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1300 #ifdef FORBIDDEN_INC_DEC_CLASSES |
|
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1301 if (in_inc_dec[a_num]) |
|
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1302 inc_dec_p = true; |
|
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1303 #endif |
| 0 | 1304 } |
| 1305 } | |
| 1306 best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; | |
| 1307 best = ALL_REGS; | |
| 1308 alt_class = NO_REGS; | |
| 1309 /* Find best common class for all allocnos with the same | |
| 1310 regno. */ | |
| 1311 for (k = 0; k < cost_classes_num; k++) | |
| 1312 { | |
| 1313 rclass = cost_classes[k]; | |
| 1314 /* Ignore classes that are too small for this operand or | |
| 1315 invalid for an operand that was auto-incremented. */ | |
| 1316 if (! contains_reg_of_mode[rclass][PSEUDO_REGNO_MODE (i)] | |
| 1317 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 1318 || (inc_dec_p && forbidden_inc_dec_class[rclass]) | |
| 1319 #endif | |
| 1320 #ifdef CANNOT_CHANGE_MODE_CLASS | |
| 1321 || invalid_mode_change_p (i, (enum reg_class) rclass, | |
| 1322 PSEUDO_REGNO_MODE (i)) | |
| 1323 #endif | |
| 1324 ) | |
| 1325 continue; | |
| 1326 if (temp_costs->cost[k] < best_cost) | |
| 1327 { | |
| 1328 best_cost = temp_costs->cost[k]; | |
| 1329 best = (enum reg_class) rclass; | |
| 1330 } | |
| 1331 else if (temp_costs->cost[k] == best_cost) | |
| 1332 best = ira_reg_class_union[best][rclass]; | |
| 1333 if (pass == flag_expensive_optimizations | |
| 1334 && temp_costs->cost[k] < temp_costs->mem_cost | |
| 1335 && (reg_class_size[reg_class_subunion[alt_class][rclass]] | |
| 1336 > reg_class_size[alt_class])) | |
| 1337 alt_class = reg_class_subunion[alt_class][rclass]; | |
| 1338 } | |
| 1339 alt_class = ira_class_translate[alt_class]; | |
|
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1340 if (best_cost > temp_costs->mem_cost) |
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1341 regno_cover_class[i] = NO_REGS; |
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1342 else if (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY) |
|
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1343 /* Make the common class the biggest class of best and |
|
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1344 alt_class. */ |
|
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1345 regno_cover_class[i] = alt_class == NO_REGS ? best : alt_class; |
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1346 else |
|
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1347 /* Make the common class a cover class. Remember all |
|
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1348 allocnos with the same regno should have the same cover |
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1349 class. */ |
|
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1350 regno_cover_class[i] = ira_class_translate[best]; |
| 0 | 1351 if (pass == flag_expensive_optimizations) |
| 1352 { | |
| 1353 if (best_cost > temp_costs->mem_cost) | |
| 1354 best = alt_class = NO_REGS; | |
| 1355 else if (best == alt_class) | |
| 1356 alt_class = NO_REGS; | |
|
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1357 setup_reg_classes (i, best, alt_class, regno_cover_class[i]); |
|
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1358 if ((!allocno_p || internal_flag_ira_verbose > 2) |
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1359 && dump_file != NULL) |
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1360 fprintf (dump_file, |
|
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1361 " r%d: preferred %s, alternative %s, cover %s\n", |
|
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1362 i, reg_class_names[best], reg_class_names[alt_class], |
|
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1363 reg_class_names[regno_cover_class[i]]); |
| 0 | 1364 } |
|
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1365 if (! allocno_p) |
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1366 { |
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1367 pref[i] = best_cost > temp_costs->mem_cost ? NO_REGS : best; |
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1368 continue; |
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1369 } |
| 0 | 1370 for (a = ira_regno_allocno_map[i]; |
| 1371 a != NULL; | |
| 1372 a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) | |
| 1373 { | |
| 1374 a_num = ALLOCNO_NUM (a); | |
|
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1375 if (regno_cover_class[i] == NO_REGS) |
| 0 | 1376 best = NO_REGS; |
| 1377 else | |
|
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1378 { |
| 0 | 1379 /* Finding best class which is subset of the common |
| 1380 class. */ | |
| 1381 best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; | |
| 1382 allocno_cost = best_cost; | |
| 1383 best = ALL_REGS; | |
| 1384 for (k = 0; k < cost_classes_num; k++) | |
| 1385 { | |
| 1386 rclass = cost_classes[k]; | |
|
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1387 if (! ira_class_subset_p[rclass][regno_cover_class[i]]) |
| 0 | 1388 continue; |
| 1389 /* Ignore classes that are too small for this | |
| 1390 operand or invalid for an operand that was | |
| 1391 auto-incremented. */ | |
| 1392 if (! contains_reg_of_mode[rclass][PSEUDO_REGNO_MODE (i)] | |
| 1393 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 1394 || (inc_dec_p && forbidden_inc_dec_class[rclass]) | |
| 1395 #endif | |
| 1396 #ifdef CANNOT_CHANGE_MODE_CLASS | |
| 1397 || invalid_mode_change_p (i, (enum reg_class) rclass, | |
| 1398 PSEUDO_REGNO_MODE (i)) | |
| 1399 #endif | |
| 1400 ) | |
| 1401 ; | |
|
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1402 else if (COSTS (total_allocno_costs, a_num)->cost[k] |
| 0 | 1403 < best_cost) |
| 1404 { | |
| 1405 best_cost | |
|
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1406 = COSTS (total_allocno_costs, a_num)->cost[k]; |
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1407 allocno_cost = COSTS (costs, a_num)->cost[k]; |
| 0 | 1408 best = (enum reg_class) rclass; |
| 1409 } | |
|
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1410 else if (COSTS (total_allocno_costs, a_num)->cost[k] |
| 0 | 1411 == best_cost) |
| 1412 { | |
| 1413 best = ira_reg_class_union[best][rclass]; | |
| 1414 allocno_cost | |
|
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1415 = MAX (allocno_cost, COSTS (costs, a_num)->cost[k]); |
| 0 | 1416 } |
| 1417 } | |
| 1418 ALLOCNO_COVER_CLASS_COST (a) = allocno_cost; | |
| 1419 } | |
| 1420 ira_assert (flag_ira_algorithm == IRA_ALGORITHM_PRIORITY | |
|
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1421 || ira_class_translate[best] == regno_cover_class[i]); |
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1422 if (internal_flag_ira_verbose > 2 && dump_file != NULL |
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1423 && (pass == 0 || pref[a_num] != best)) |
| 0 | 1424 { |
|
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1425 fprintf (dump_file, " a%d (r%d,", a_num, i); |
| 0 | 1426 if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) |
|
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1427 fprintf (dump_file, "b%d", bb->index); |
| 0 | 1428 else |
|
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1429 fprintf (dump_file, "l%d", |
| 0 | 1430 ALLOCNO_LOOP_TREE_NODE (a)->loop->num); |
|
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1431 fprintf (dump_file, ") best %s, cover %s\n", |
| 0 | 1432 reg_class_names[best], |
|
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1433 reg_class_names[regno_cover_class[i]]); |
| 0 | 1434 } |
|
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1435 pref[a_num] = best; |
| 0 | 1436 } |
| 1437 } | |
|
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1438 |
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1439 if (internal_flag_ira_verbose > 4 && dump_file) |
| 0 | 1440 { |
|
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1441 if (allocno_p) |
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1442 print_allocno_costs (dump_file); |
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1443 else |
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1444 print_pseudo_costs (dump_file); |
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1445 fprintf (dump_file,"\n"); |
| 0 | 1446 } |
| 1447 } | |
| 1448 #ifdef FORBIDDEN_INC_DEC_CLASSES | |
| 1449 ira_free (in_inc_dec); | |
| 1450 #endif | |
| 1451 } | |
| 1452 | |
| 1453 | |
| 1454 | |
| 1455 /* Process moves involving hard regs to modify allocno hard register | |
| 1456 costs. We can do this only after determining allocno cover class. | |
| 1457 If a hard register forms a register class, than moves with the hard | |
| 1458 register are already taken into account in class costs for the | |
| 1459 allocno. */ | |
| 1460 static void | |
| 1461 process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node) | |
| 1462 { | |
| 1463 int i, freq, cost, src_regno, dst_regno, hard_regno; | |
| 1464 bool to_p; | |
| 1465 ira_allocno_t a; | |
| 1466 enum reg_class rclass, hard_reg_class; | |
| 1467 enum machine_mode mode; | |
| 1468 basic_block bb; | |
| 1469 rtx insn, set, src, dst; | |
| 1470 | |
| 1471 bb = loop_tree_node->bb; | |
| 1472 if (bb == NULL) | |
| 1473 return; | |
| 1474 freq = REG_FREQ_FROM_BB (bb); | |
| 1475 if (freq == 0) | |
| 1476 freq = 1; | |
| 1477 FOR_BB_INSNS (bb, insn) | |
| 1478 { | |
|
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1479 if (!NONDEBUG_INSN_P (insn)) |
| 0 | 1480 continue; |
| 1481 set = single_set (insn); | |
| 1482 if (set == NULL_RTX) | |
| 1483 continue; | |
| 1484 dst = SET_DEST (set); | |
| 1485 src = SET_SRC (set); | |
| 1486 if (! REG_P (dst) || ! REG_P (src)) | |
| 1487 continue; | |
| 1488 dst_regno = REGNO (dst); | |
| 1489 src_regno = REGNO (src); | |
| 1490 if (dst_regno >= FIRST_PSEUDO_REGISTER | |
| 1491 && src_regno < FIRST_PSEUDO_REGISTER) | |
| 1492 { | |
| 1493 hard_regno = src_regno; | |
| 1494 to_p = true; | |
| 1495 a = ira_curr_regno_allocno_map[dst_regno]; | |
| 1496 } | |
| 1497 else if (src_regno >= FIRST_PSEUDO_REGISTER | |
| 1498 && dst_regno < FIRST_PSEUDO_REGISTER) | |
| 1499 { | |
| 1500 hard_regno = dst_regno; | |
| 1501 to_p = false; | |
| 1502 a = ira_curr_regno_allocno_map[src_regno]; | |
| 1503 } | |
| 1504 else | |
| 1505 continue; | |
| 1506 rclass = ALLOCNO_COVER_CLASS (a); | |
| 1507 if (! TEST_HARD_REG_BIT (reg_class_contents[rclass], hard_regno)) | |
| 1508 continue; | |
| 1509 i = ira_class_hard_reg_index[rclass][hard_regno]; | |
| 1510 if (i < 0) | |
| 1511 continue; | |
| 1512 mode = ALLOCNO_MODE (a); | |
| 1513 hard_reg_class = REGNO_REG_CLASS (hard_regno); | |
|
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1514 cost |
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1515 = (to_p ? ira_get_register_move_cost (mode, hard_reg_class, rclass) |
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1516 : ira_get_register_move_cost (mode, rclass, hard_reg_class)) * freq; |
| 0 | 1517 ira_allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a), rclass, |
| 1518 ALLOCNO_COVER_CLASS_COST (a)); | |
| 1519 ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a), | |
| 1520 rclass, 0); | |
| 1521 ALLOCNO_HARD_REG_COSTS (a)[i] -= cost; | |
| 1522 ALLOCNO_CONFLICT_HARD_REG_COSTS (a)[i] -= cost; | |
| 1523 ALLOCNO_COVER_CLASS_COST (a) = MIN (ALLOCNO_COVER_CLASS_COST (a), | |
| 1524 ALLOCNO_HARD_REG_COSTS (a)[i]); | |
| 1525 } | |
| 1526 } | |
| 1527 | |
| 1528 /* After we find hard register and memory costs for allocnos, define | |
| 1529 its cover class and modify hard register cost because insns moving | |
| 1530 allocno to/from hard registers. */ | |
| 1531 static void | |
| 1532 setup_allocno_cover_class_and_costs (void) | |
| 1533 { | |
| 1534 int i, j, n, regno, num; | |
| 1535 int *reg_costs; | |
| 1536 enum reg_class cover_class, rclass; | |
| 1537 ira_allocno_t a; | |
| 1538 ira_allocno_iterator ai; | |
| 1539 | |
|
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1540 ira_assert (allocno_p); |
| 0 | 1541 FOR_EACH_ALLOCNO (a, ai) |
| 1542 { | |
| 1543 i = ALLOCNO_NUM (a); | |
|
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1544 cover_class = regno_cover_class[ALLOCNO_REGNO (a)]; |
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1545 ira_assert (pref[i] == NO_REGS || cover_class != NO_REGS); |
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1546 ALLOCNO_MEMORY_COST (a) = COSTS (costs, i)->mem_cost; |
| 0 | 1547 ira_set_allocno_cover_class (a, cover_class); |
| 1548 if (cover_class == NO_REGS) | |
| 1549 continue; | |
| 1550 ALLOCNO_AVAILABLE_REGS_NUM (a) = ira_available_class_regs[cover_class]; | |
|
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1551 if (optimize && ALLOCNO_COVER_CLASS (a) != pref[i]) |
| 0 | 1552 { |
| 1553 n = ira_class_hard_regs_num[cover_class]; | |
| 1554 ALLOCNO_HARD_REG_COSTS (a) | |
| 1555 = reg_costs = ira_allocate_cost_vector (cover_class); | |
| 1556 for (j = n - 1; j >= 0; j--) | |
| 1557 { | |
| 1558 regno = ira_class_hard_regs[cover_class][j]; | |
|
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1559 if (TEST_HARD_REG_BIT (reg_class_contents[pref[i]], regno)) |
| 0 | 1560 reg_costs[j] = ALLOCNO_COVER_CLASS_COST (a); |
| 1561 else | |
| 1562 { | |
| 1563 rclass = REGNO_REG_CLASS (regno); | |
| 1564 num = cost_class_nums[rclass]; | |
| 1565 if (num < 0) | |
| 1566 { | |
| 1567 /* The hard register class is not a cover class or a | |
| 1568 class not fully inside in a cover class -- use | |
| 1569 the allocno cover class. */ | |
| 1570 ira_assert (ira_hard_regno_cover_class[regno] | |
| 1571 == cover_class); | |
| 1572 num = cost_class_nums[cover_class]; | |
| 1573 } | |
|
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1574 reg_costs[j] = COSTS (costs, i)->cost[num]; |
| 0 | 1575 } |
| 1576 } | |
| 1577 } | |
| 1578 } | |
| 1579 if (optimize) | |
| 1580 ira_traverse_loop_tree (true, ira_loop_tree_root, | |
| 1581 process_bb_node_for_hard_reg_moves, NULL); | |
| 1582 } | |
| 1583 | |
| 1584 | |
| 1585 | |
| 1586 /* Function called once during compiler work. */ | |
| 1587 void | |
| 1588 ira_init_costs_once (void) | |
| 1589 { | |
| 1590 int i; | |
| 1591 | |
| 1592 init_cost = NULL; | |
| 1593 for (i = 0; i < MAX_RECOG_OPERANDS; i++) | |
| 1594 { | |
| 1595 op_costs[i] = NULL; | |
| 1596 this_op_costs[i] = NULL; | |
| 1597 } | |
| 1598 temp_costs = NULL; | |
| 1599 cost_classes = NULL; | |
| 1600 } | |
| 1601 | |
| 1602 /* Free allocated temporary cost vectors. */ | |
| 1603 static void | |
| 1604 free_ira_costs (void) | |
| 1605 { | |
| 1606 int i; | |
| 1607 | |
| 1608 if (init_cost != NULL) | |
| 1609 free (init_cost); | |
| 1610 init_cost = NULL; | |
| 1611 for (i = 0; i < MAX_RECOG_OPERANDS; i++) | |
| 1612 { | |
| 1613 if (op_costs[i] != NULL) | |
| 1614 free (op_costs[i]); | |
| 1615 if (this_op_costs[i] != NULL) | |
| 1616 free (this_op_costs[i]); | |
| 1617 op_costs[i] = this_op_costs[i] = NULL; | |
| 1618 } | |
| 1619 if (temp_costs != NULL) | |
| 1620 free (temp_costs); | |
| 1621 temp_costs = NULL; | |
| 1622 if (cost_classes != NULL) | |
| 1623 free (cost_classes); | |
| 1624 cost_classes = NULL; | |
| 1625 } | |
| 1626 | |
| 1627 /* This is called each time register related information is | |
| 1628 changed. */ | |
| 1629 void | |
| 1630 ira_init_costs (void) | |
| 1631 { | |
| 1632 int i; | |
| 1633 | |
| 1634 free_ira_costs (); | |
| 1635 max_struct_costs_size | |
| 1636 = sizeof (struct costs) + sizeof (int) * (ira_important_classes_num - 1); | |
| 1637 /* Don't use ira_allocate because vectors live through several IRA calls. */ | |
| 1638 init_cost = (struct costs *) xmalloc (max_struct_costs_size); | |
| 1639 init_cost->mem_cost = 1000000; | |
| 1640 for (i = 0; i < ira_important_classes_num; i++) | |
| 1641 init_cost->cost[i] = 1000000; | |
| 1642 for (i = 0; i < MAX_RECOG_OPERANDS; i++) | |
| 1643 { | |
| 1644 op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size); | |
| 1645 this_op_costs[i] = (struct costs *) xmalloc (max_struct_costs_size); | |
| 1646 } | |
| 1647 temp_costs = (struct costs *) xmalloc (max_struct_costs_size); | |
| 1648 cost_classes = (enum reg_class *) xmalloc (sizeof (enum reg_class) | |
| 1649 * ira_important_classes_num); | |
| 1650 } | |
| 1651 | |
| 1652 /* Function called once at the end of compiler work. */ | |
| 1653 void | |
| 1654 ira_finish_costs_once (void) | |
| 1655 { | |
| 1656 free_ira_costs (); | |
| 1657 } | |
| 1658 | |
| 1659 | |
| 1660 | |
|
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1661 /* Common initialization function for ira_costs and |
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1662 ira_set_pseudo_classes. */ |
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1663 static void |
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1664 init_costs (void) |
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1665 { |
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1666 init_subregs_of_mode (); |
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1667 costs = (struct costs *) ira_allocate (max_struct_costs_size |
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1668 * cost_elements_num); |
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1669 pref_buffer |
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1670 = (enum reg_class *) ira_allocate (sizeof (enum reg_class) |
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1671 * cost_elements_num); |
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1672 regno_cover_class |
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1673 = (enum reg_class *) ira_allocate (sizeof (enum reg_class) |
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1674 * max_reg_num ()); |
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1675 } |
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1676 |
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1677 /* Common finalization function for ira_costs and |
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1678 ira_set_pseudo_classes. */ |
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1679 static void |
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1680 finish_costs (void) |
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1681 { |
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1682 ira_free (regno_cover_class); |
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1683 ira_free (pref_buffer); |
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1684 ira_free (costs); |
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1685 } |
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1686 |
| 0 | 1687 /* Entry function which defines cover class, memory and hard register |
| 1688 costs for each allocno. */ | |
| 1689 void | |
| 1690 ira_costs (void) | |
| 1691 { | |
|
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1692 allocno_p = true; |
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1693 cost_elements_num = ira_allocnos_num; |
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1694 init_costs (); |
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1695 total_allocno_costs = (struct costs *) ira_allocate (max_struct_costs_size |
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1696 * ira_allocnos_num); |
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1697 find_costs_and_classes (ira_dump_file); |
| 0 | 1698 setup_allocno_cover_class_and_costs (); |
|
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1699 finish_costs (); |
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1700 ira_free (total_allocno_costs); |
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1701 } |
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1702 |
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1703 /* Entry function which defines classes for pseudos. */ |
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1704 void |
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1705 ira_set_pseudo_classes (FILE *dump_file) |
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1706 { |
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1707 allocno_p = false; |
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1708 internal_flag_ira_verbose = flag_ira_verbose; |
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1709 cost_elements_num = max_reg_num (); |
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1710 init_costs (); |
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1711 find_costs_and_classes (dump_file); |
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1712 pseudo_classes_defined_p = true; |
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1713 finish_costs (); |
| 0 | 1714 } |
| 1715 | |
| 1716 | |
| 1717 | |
| 1718 /* Change hard register costs for allocnos which lives through | |
| 1719 function calls. This is called only when we found all intersected | |
| 1720 calls during building allocno live ranges. */ | |
| 1721 void | |
| 1722 ira_tune_allocno_costs_and_cover_classes (void) | |
| 1723 { | |
| 1724 int j, n, regno; | |
| 1725 int cost, min_cost, *reg_costs; | |
| 1726 enum reg_class cover_class, rclass; | |
| 1727 enum machine_mode mode; | |
| 1728 ira_allocno_t a; | |
| 1729 ira_allocno_iterator ai; | |
| 1730 | |
| 1731 FOR_EACH_ALLOCNO (a, ai) | |
| 1732 { | |
| 1733 cover_class = ALLOCNO_COVER_CLASS (a); | |
| 1734 if (cover_class == NO_REGS) | |
| 1735 continue; | |
| 1736 mode = ALLOCNO_MODE (a); | |
| 1737 n = ira_class_hard_regs_num[cover_class]; | |
| 1738 min_cost = INT_MAX; | |
| 1739 if (ALLOCNO_CALLS_CROSSED_NUM (a) != 0) | |
| 1740 { | |
| 1741 ira_allocate_and_set_costs | |
| 1742 (&ALLOCNO_HARD_REG_COSTS (a), cover_class, | |
| 1743 ALLOCNO_COVER_CLASS_COST (a)); | |
| 1744 reg_costs = ALLOCNO_HARD_REG_COSTS (a); | |
| 1745 for (j = n - 1; j >= 0; j--) | |
| 1746 { | |
| 1747 regno = ira_class_hard_regs[cover_class][j]; | |
| 1748 rclass = REGNO_REG_CLASS (regno); | |
| 1749 cost = 0; | |
| 1750 if (! ira_hard_reg_not_in_set_p (regno, mode, call_used_reg_set) | |
| 1751 || HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)) | |
| 1752 cost += (ALLOCNO_CALL_FREQ (a) | |
| 1753 * (ira_memory_move_cost[mode][rclass][0] | |
| 1754 + ira_memory_move_cost[mode][rclass][1])); | |
| 1755 #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER | |
| 1756 cost += ((ira_memory_move_cost[mode][rclass][0] | |
| 1757 + ira_memory_move_cost[mode][rclass][1]) | |
| 1758 * ALLOCNO_FREQ (a) | |
| 1759 * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno) / 2); | |
| 1760 #endif | |
| 1761 reg_costs[j] += cost; | |
| 1762 if (min_cost > reg_costs[j]) | |
| 1763 min_cost = reg_costs[j]; | |
| 1764 } | |
| 1765 } | |
| 1766 if (min_cost != INT_MAX) | |
| 1767 ALLOCNO_COVER_CLASS_COST (a) = min_cost; | |
| 1768 } | |
| 1769 } |