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1 ;; Machine description for AArch64 architecture.
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131
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2 ;; Copyright (C) 2009-2018 Free Software Foundation, Inc.
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111
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3 ;; Contributed by ARM Ltd.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but
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13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 ;; General Public License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_special_predicate "cc_register"
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22 (and (match_code "reg")
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23 (and (match_test "REGNO (op) == CC_REGNUM")
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24 (ior (match_test "mode == GET_MODE (op)")
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25 (match_test "mode == VOIDmode
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26 && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))
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27 )
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28
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29 (define_predicate "aarch64_call_insn_operand"
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30 (ior (match_code "symbol_ref")
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31 (match_operand 0 "register_operand")))
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32
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33 ;; Return true if OP a (const_int 0) operand.
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34 (define_predicate "const0_operand"
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35 (and (match_code "const_int")
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36 (match_test "op == CONST0_RTX (mode)")))
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37
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38 (define_special_predicate "subreg_lowpart_operator"
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39 (and (match_code "subreg")
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40 (match_test "subreg_lowpart_p (op)")))
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41
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42 (define_predicate "aarch64_ccmp_immediate"
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43 (and (match_code "const_int")
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44 (match_test "IN_RANGE (INTVAL (op), -31, 31)")))
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45
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46 (define_predicate "aarch64_ccmp_operand"
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47 (ior (match_operand 0 "register_operand")
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48 (match_operand 0 "aarch64_ccmp_immediate")))
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49
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50 (define_predicate "aarch64_simd_register"
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51 (and (match_code "reg")
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52 (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS")
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53 (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS"))))
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54
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55 (define_predicate "aarch64_reg_or_zero"
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56 (and (match_code "reg,subreg,const_int")
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57 (ior (match_operand 0 "register_operand")
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58 (match_test "op == const0_rtx"))))
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59
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60 (define_predicate "aarch64_reg_or_fp_zero"
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61 (ior (match_operand 0 "register_operand")
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62 (and (match_code "const_double")
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63 (match_test "aarch64_float_const_zero_rtx_p (op)"))))
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64
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131
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65 (define_predicate "aarch64_reg_zero_or_fp_zero"
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66 (ior (match_operand 0 "aarch64_reg_or_fp_zero")
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67 (match_operand 0 "aarch64_reg_or_zero")))
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68
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111
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69 (define_predicate "aarch64_reg_zero_or_m1_or_1"
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70 (and (match_code "reg,subreg,const_int")
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71 (ior (match_operand 0 "register_operand")
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72 (ior (match_test "op == const0_rtx")
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73 (ior (match_test "op == constm1_rtx")
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74 (match_test "op == const1_rtx"))))))
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75
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76 (define_predicate "aarch64_reg_or_orr_imm"
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77 (ior (match_operand 0 "register_operand")
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78 (and (match_code "const_vector")
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131
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79 (match_test "aarch64_simd_valid_immediate (op, NULL,
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80 AARCH64_CHECK_ORR)"))))
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111
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81
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82 (define_predicate "aarch64_reg_or_bic_imm"
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83 (ior (match_operand 0 "register_operand")
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84 (and (match_code "const_vector")
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131
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85 (match_test "aarch64_simd_valid_immediate (op, NULL,
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86 AARCH64_CHECK_BIC)"))))
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111
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87
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88 (define_predicate "aarch64_fp_compare_operand"
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89 (ior (match_operand 0 "register_operand")
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90 (and (match_code "const_double")
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91 (match_test "aarch64_float_const_zero_rtx_p (op)"))))
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92
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93 (define_predicate "aarch64_fp_pow2"
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94 (and (match_code "const_double")
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95 (match_test "aarch64_fpconst_pow_of_2 (op) > 0")))
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96
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97 (define_predicate "aarch64_fp_vec_pow2"
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98 (match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0"))
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99
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131
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100 (define_predicate "aarch64_sve_cnt_immediate"
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101 (and (match_code "const_poly_int")
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102 (match_test "aarch64_sve_cnt_immediate_p (op)")))
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103
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111
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104 (define_predicate "aarch64_sub_immediate"
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105 (and (match_code "const_int")
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106 (match_test "aarch64_uimm12_shift (-INTVAL (op))")))
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107
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108 (define_predicate "aarch64_plus_immediate"
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109 (and (match_code "const_int")
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110 (ior (match_test "aarch64_uimm12_shift (INTVAL (op))")
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111 (match_test "aarch64_uimm12_shift (-INTVAL (op))"))))
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112
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113 (define_predicate "aarch64_plus_operand"
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114 (ior (match_operand 0 "register_operand")
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115 (match_operand 0 "aarch64_plus_immediate")))
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116
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117 (define_predicate "aarch64_pluslong_immediate"
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118 (and (match_code "const_int")
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119 (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)")))
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120
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121 (define_predicate "aarch64_pluslong_strict_immedate"
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122 (and (match_operand 0 "aarch64_pluslong_immediate")
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123 (not (match_operand 0 "aarch64_plus_immediate"))))
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124
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131
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125 (define_predicate "aarch64_sve_addvl_addpl_immediate"
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126 (and (match_code "const_poly_int")
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127 (match_test "aarch64_sve_addvl_addpl_immediate_p (op)")))
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128
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129 (define_predicate "aarch64_split_add_offset_immediate"
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130 (and (match_code "const_poly_int")
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131 (match_test "aarch64_add_offset_temporaries (op) == 1")))
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132
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111
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133 (define_predicate "aarch64_pluslong_operand"
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134 (ior (match_operand 0 "register_operand")
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131
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135 (match_operand 0 "aarch64_pluslong_immediate")
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136 (match_operand 0 "aarch64_sve_addvl_addpl_immediate")))
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137
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138 (define_predicate "aarch64_pluslong_or_poly_operand"
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139 (ior (match_operand 0 "aarch64_pluslong_operand")
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140 (match_operand 0 "aarch64_split_add_offset_immediate")))
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111
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141
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142 (define_predicate "aarch64_logical_immediate"
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143 (and (match_code "const_int")
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144 (match_test "aarch64_bitmask_imm (INTVAL (op), mode)")))
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145
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146 (define_predicate "aarch64_logical_operand"
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147 (ior (match_operand 0 "register_operand")
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148 (match_operand 0 "aarch64_logical_immediate")))
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149
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150 (define_predicate "aarch64_mov_imm_operand"
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151 (and (match_code "const_int")
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152 (match_test "aarch64_move_imm (INTVAL (op), mode)")))
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153
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154 (define_predicate "aarch64_logical_and_immediate"
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155 (and (match_code "const_int")
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156 (match_test "aarch64_and_bitmask_imm (INTVAL (op), mode)")))
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157
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158 (define_predicate "aarch64_shift_imm_si"
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159 (and (match_code "const_int")
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160 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 32")))
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161
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162 (define_predicate "aarch64_shift_imm_di"
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163 (and (match_code "const_int")
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164 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 64")))
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165
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166 (define_predicate "aarch64_shift_imm64_di"
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167 (and (match_code "const_int")
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168 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 64")))
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169
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170 (define_predicate "aarch64_reg_or_shift_imm_si"
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171 (ior (match_operand 0 "register_operand")
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172 (match_operand 0 "aarch64_shift_imm_si")))
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173
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174 (define_predicate "aarch64_reg_or_shift_imm_di"
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175 (ior (match_operand 0 "register_operand")
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176 (match_operand 0 "aarch64_shift_imm_di")))
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177
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178 ;; The imm3 field is a 3-bit field that only accepts immediates in the
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179 ;; range 0..4.
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180 (define_predicate "aarch64_imm3"
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181 (and (match_code "const_int")
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182 (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4")))
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183
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131
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184 ;; The imm2 field is a 2-bit field that only accepts immediates in the
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185 ;; range 0..3.
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186 (define_predicate "aarch64_imm2"
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187 (and (match_code "const_int")
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188 (match_test "UINTVAL (op) <= 3")))
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189
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190 ;; The imm3 field is a 3-bit field that only accepts immediates in the
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191 ;; range 0..7.
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192 (define_predicate "aarch64_lane_imm3"
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193 (and (match_code "const_int")
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194 (match_test "UINTVAL (op) <= 7")))
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195
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111
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196 ;; An immediate that fits into 24 bits.
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197 (define_predicate "aarch64_imm24"
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198 (and (match_code "const_int")
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199 (match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)")))
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200
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201 (define_predicate "aarch64_pwr_imm3"
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202 (and (match_code "const_int")
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203 (match_test "INTVAL (op) != 0
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204 && (unsigned) exact_log2 (INTVAL (op)) <= 4")))
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205
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206 (define_predicate "aarch64_pwr_2_si"
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207 (and (match_code "const_int")
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208 (match_test "INTVAL (op) != 0
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209 && (unsigned) exact_log2 (INTVAL (op)) < 32")))
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210
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211 (define_predicate "aarch64_pwr_2_di"
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212 (and (match_code "const_int")
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213 (match_test "INTVAL (op) != 0
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214 && (unsigned) exact_log2 (INTVAL (op)) < 64")))
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215
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216 (define_predicate "aarch64_mem_pair_offset"
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217 (and (match_code "const_int")
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218 (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))
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219
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220 (define_predicate "aarch64_mem_pair_operand"
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221 (and (match_code "mem")
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131
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222 (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), false,
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223 ADDR_QUERY_LDP_STP)")))
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224
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225 ;; Used for storing two 64-bit values in an AdvSIMD register using an STP
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226 ;; as a 128-bit vec_concat.
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227 (define_predicate "aarch64_mem_pair_lanes_operand"
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228 (and (match_code "mem")
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229 (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
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230 false,
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231 ADDR_QUERY_LDP_STP_N)")))
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111
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232
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233 (define_predicate "aarch64_prefetch_operand"
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234 (match_test "aarch64_address_valid_for_prefetch_p (op, false)"))
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235
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236 (define_predicate "aarch64_valid_symref"
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237 (match_code "const, symbol_ref, label_ref")
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238 {
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239 return (aarch64_classify_symbolic_expression (op)
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240 != SYMBOL_FORCE_TO_MEM);
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241 })
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242
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243 (define_predicate "aarch64_tls_ie_symref"
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244 (match_code "const, symbol_ref, label_ref")
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245 {
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246 switch (GET_CODE (op))
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247 {
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248 case CONST:
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249 op = XEXP (op, 0);
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250 if (GET_CODE (op) != PLUS
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251 || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
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252 || GET_CODE (XEXP (op, 1)) != CONST_INT)
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253 return false;
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254 op = XEXP (op, 0);
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255 /* FALLTHRU */
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256
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257 case SYMBOL_REF:
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258 return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC;
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259
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260 default:
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261 gcc_unreachable ();
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262 }
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263 })
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264
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265 (define_predicate "aarch64_tls_le_symref"
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266 (match_code "const, symbol_ref, label_ref")
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267 {
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268 switch (GET_CODE (op))
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269 {
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270 case CONST:
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271 op = XEXP (op, 0);
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272 if (GET_CODE (op) != PLUS
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273 || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
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274 || GET_CODE (XEXP (op, 1)) != CONST_INT)
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275 return false;
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276 op = XEXP (op, 0);
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277 /* FALLTHRU */
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278
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279 case SYMBOL_REF:
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280 return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC;
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281
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282 default:
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283 gcc_unreachable ();
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284 }
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285 })
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286
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287 (define_predicate "aarch64_mov_operand"
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131
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288 (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high,
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289 const_poly_int,const_vector")
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111
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290 (ior (match_operand 0 "register_operand")
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291 (ior (match_operand 0 "memory_operand")
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292 (match_test "aarch64_mov_operand_p (op, mode)")))))
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293
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131
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294 (define_predicate "aarch64_nonmemory_operand"
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295 (and (match_code "reg,subreg,const,const_int,symbol_ref,label_ref,high,
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296 const_poly_int,const_vector")
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111
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297 (ior (match_operand 0 "register_operand")
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131
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298 (match_test "aarch64_mov_operand_p (op, mode)"))))
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299
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300 (define_predicate "aarch64_movti_operand"
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301 (ior (match_operand 0 "register_operand")
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302 (match_operand 0 "memory_operand")
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303 (and (match_operand 0 "const_scalar_int_operand")
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304 (match_test "aarch64_mov128_immediate (op)"))))
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111
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305
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306 (define_predicate "aarch64_reg_or_imm"
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131
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307 (ior (match_operand 0 "register_operand")
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308 (match_operand 0 "const_scalar_int_operand")))
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111
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309
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310 ;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ.
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311 (define_special_predicate "aarch64_comparison_operator"
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312 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
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313 ordered,unlt,unle,unge,ungt"))
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314
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315 ;; Same as aarch64_comparison_operator but don't ignore the mode.
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316 ;; RTL SET operations require their operands source and destination have
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317 ;; the same modes, so we can't ignore the modes there. See PR target/69161.
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318 (define_predicate "aarch64_comparison_operator_mode"
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319 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
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320 ordered,unlt,unle,unge,ungt"))
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321
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322 (define_special_predicate "aarch64_comparison_operation"
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323 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
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324 ordered,unlt,unle,unge,ungt")
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325 {
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326 if (XEXP (op, 1) != const0_rtx)
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327 return false;
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328 rtx op0 = XEXP (op, 0);
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329 if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
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330 return false;
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331 return aarch64_get_condition_code (op) >= 0;
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332 })
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333
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131
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334 (define_special_predicate "aarch64_equality_operator"
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335 (match_code "eq,ne"))
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336
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111
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337 (define_special_predicate "aarch64_carry_operation"
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338 (match_code "ne,geu")
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339 {
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340 if (XEXP (op, 1) != const0_rtx)
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341 return false;
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342 machine_mode ccmode = (GET_CODE (op) == NE ? CC_Cmode : CCmode);
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343 rtx op0 = XEXP (op, 0);
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344 return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
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345 })
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346
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347 (define_special_predicate "aarch64_borrow_operation"
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348 (match_code "eq,ltu")
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349 {
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350 if (XEXP (op, 1) != const0_rtx)
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351 return false;
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352 machine_mode ccmode = (GET_CODE (op) == EQ ? CC_Cmode : CCmode);
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353 rtx op0 = XEXP (op, 0);
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354 return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
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355 })
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356
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357 ;; True if the operand is memory reference suitable for a load/store exclusive.
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358 (define_predicate "aarch64_sync_memory_operand"
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359 (and (match_operand 0 "memory_operand")
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360 (match_code "reg" "0")))
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361
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131
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362 (define_predicate "aarch64_9bit_offset_memory_operand"
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363 (and (match_operand 0 "memory_operand")
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364 (ior (match_code "reg" "0")
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365 (and (match_code "plus" "0")
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366 (match_code "reg" "00")
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367 (match_code "const_int" "01"))))
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368 {
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369 rtx mem_op = XEXP (op, 0);
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370
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371 if (REG_P (mem_op))
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372 return GET_MODE (mem_op) == DImode;
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373
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374 rtx plus_op0 = XEXP (mem_op, 0);
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375 rtx plus_op1 = XEXP (mem_op, 1);
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376
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377 if (GET_MODE (plus_op0) != DImode)
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378 return false;
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379
|
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380 poly_int64 offset;
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381 if (!poly_int_rtx_p (plus_op1, &offset))
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382 gcc_unreachable ();
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383
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384 return aarch64_offset_9bit_signed_unscaled_p (mode, offset);
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|
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385 })
|
|
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386
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|
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387 (define_predicate "aarch64_rcpc_memory_operand"
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|
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388 (if_then_else (match_test "AARCH64_ISA_RCPC8_4")
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389 (match_operand 0 "aarch64_9bit_offset_memory_operand")
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390 (match_operand 0 "aarch64_sync_memory_operand")))
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|
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391
|
|
111
|
392 ;; Predicates for parallel expanders based on mode.
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|
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393 (define_special_predicate "vect_par_cnst_hi_half"
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|
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394 (match_code "parallel")
|
|
|
395 {
|
|
|
396 return aarch64_simd_check_vect_par_cnst_half (op, mode, true);
|
|
|
397 })
|
|
|
398
|
|
|
399 (define_special_predicate "vect_par_cnst_lo_half"
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|
|
400 (match_code "parallel")
|
|
|
401 {
|
|
|
402 return aarch64_simd_check_vect_par_cnst_half (op, mode, false);
|
|
|
403 })
|
|
|
404
|
|
|
405 (define_special_predicate "aarch64_simd_lshift_imm"
|
|
131
|
406 (match_code "const,const_vector")
|
|
111
|
407 {
|
|
|
408 return aarch64_simd_shift_imm_p (op, mode, true);
|
|
|
409 })
|
|
|
410
|
|
|
411 (define_special_predicate "aarch64_simd_rshift_imm"
|
|
131
|
412 (match_code "const,const_vector")
|
|
111
|
413 {
|
|
|
414 return aarch64_simd_shift_imm_p (op, mode, false);
|
|
|
415 })
|
|
|
416
|
|
131
|
417 (define_predicate "aarch64_simd_imm_zero"
|
|
|
418 (and (match_code "const,const_vector")
|
|
|
419 (match_test "op == CONST0_RTX (GET_MODE (op))")))
|
|
|
420
|
|
|
421 (define_predicate "aarch64_simd_or_scalar_imm_zero"
|
|
|
422 (and (match_code "const_int,const_double,const,const_vector")
|
|
|
423 (match_test "op == CONST0_RTX (GET_MODE (op))")))
|
|
|
424
|
|
|
425 (define_predicate "aarch64_simd_imm_minus_one"
|
|
|
426 (and (match_code "const,const_vector")
|
|
|
427 (match_test "op == CONSTM1_RTX (GET_MODE (op))")))
|
|
|
428
|
|
111
|
429 (define_predicate "aarch64_simd_reg_or_zero"
|
|
131
|
430 (and (match_code "reg,subreg,const_int,const_double,const,const_vector")
|
|
111
|
431 (ior (match_operand 0 "register_operand")
|
|
131
|
432 (match_test "op == const0_rtx")
|
|
|
433 (match_operand 0 "aarch64_simd_or_scalar_imm_zero"))))
|
|
111
|
434
|
|
|
435 (define_predicate "aarch64_simd_struct_operand"
|
|
|
436 (and (match_code "mem")
|
|
|
437 (match_test "TARGET_SIMD && aarch64_simd_mem_operand_p (op)")))
|
|
|
438
|
|
|
439 ;; Like general_operand but allow only valid SIMD addressing modes.
|
|
|
440 (define_predicate "aarch64_simd_general_operand"
|
|
|
441 (and (match_operand 0 "general_operand")
|
|
|
442 (match_test "!MEM_P (op)
|
|
|
443 || GET_CODE (XEXP (op, 0)) == POST_INC
|
|
|
444 || GET_CODE (XEXP (op, 0)) == REG")))
|
|
|
445
|
|
|
446 ;; Like nonimmediate_operand but allow only valid SIMD addressing modes.
|
|
|
447 (define_predicate "aarch64_simd_nonimmediate_operand"
|
|
|
448 (and (match_operand 0 "nonimmediate_operand")
|
|
|
449 (match_test "!MEM_P (op)
|
|
|
450 || GET_CODE (XEXP (op, 0)) == POST_INC
|
|
|
451 || GET_CODE (XEXP (op, 0)) == REG")))
|
|
|
452
|
|
|
453 ;; Predicates used by the various SIMD shift operations. These
|
|
|
454 ;; fall in to 3 categories.
|
|
|
455 ;; Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm)
|
|
|
456 ;; Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset)
|
|
|
457 ;; Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize)
|
|
|
458 (define_predicate "aarch64_simd_shift_imm_qi"
|
|
|
459 (and (match_code "const_int")
|
|
|
460 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
|
|
|
461
|
|
|
462 (define_predicate "aarch64_simd_shift_imm_hi"
|
|
|
463 (and (match_code "const_int")
|
|
|
464 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
|
|
|
465
|
|
|
466 (define_predicate "aarch64_simd_shift_imm_si"
|
|
|
467 (and (match_code "const_int")
|
|
|
468 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
|
|
|
469
|
|
|
470 (define_predicate "aarch64_simd_shift_imm_di"
|
|
|
471 (and (match_code "const_int")
|
|
|
472 (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
|
|
|
473
|
|
|
474 (define_predicate "aarch64_simd_shift_imm_offset_qi"
|
|
|
475 (and (match_code "const_int")
|
|
|
476 (match_test "IN_RANGE (INTVAL (op), 1, 8)")))
|
|
|
477
|
|
|
478 (define_predicate "aarch64_simd_shift_imm_offset_hi"
|
|
|
479 (and (match_code "const_int")
|
|
|
480 (match_test "IN_RANGE (INTVAL (op), 1, 16)")))
|
|
|
481
|
|
|
482 (define_predicate "aarch64_simd_shift_imm_offset_si"
|
|
|
483 (and (match_code "const_int")
|
|
|
484 (match_test "IN_RANGE (INTVAL (op), 1, 32)")))
|
|
|
485
|
|
|
486 (define_predicate "aarch64_simd_shift_imm_offset_di"
|
|
|
487 (and (match_code "const_int")
|
|
|
488 (match_test "IN_RANGE (INTVAL (op), 1, 64)")))
|
|
|
489
|
|
|
490 (define_predicate "aarch64_simd_shift_imm_bitsize_qi"
|
|
|
491 (and (match_code "const_int")
|
|
|
492 (match_test "IN_RANGE (INTVAL (op), 0, 8)")))
|
|
|
493
|
|
|
494 (define_predicate "aarch64_simd_shift_imm_bitsize_hi"
|
|
|
495 (and (match_code "const_int")
|
|
|
496 (match_test "IN_RANGE (INTVAL (op), 0, 16)")))
|
|
|
497
|
|
|
498 (define_predicate "aarch64_simd_shift_imm_bitsize_si"
|
|
|
499 (and (match_code "const_int")
|
|
|
500 (match_test "IN_RANGE (INTVAL (op), 0, 32)")))
|
|
|
501
|
|
|
502 (define_predicate "aarch64_simd_shift_imm_bitsize_di"
|
|
|
503 (and (match_code "const_int")
|
|
|
504 (match_test "IN_RANGE (INTVAL (op), 0, 64)")))
|
|
|
505
|
|
|
506 (define_predicate "aarch64_constant_pool_symref"
|
|
|
507 (and (match_code "symbol_ref")
|
|
|
508 (match_test "CONSTANT_POOL_ADDRESS_P (op)")))
|
|
131
|
509
|
|
|
510 (define_predicate "aarch64_constant_vector_operand"
|
|
|
511 (match_code "const,const_vector"))
|
|
|
512
|
|
|
513 (define_predicate "aarch64_sve_ld1r_operand"
|
|
|
514 (and (match_operand 0 "memory_operand")
|
|
|
515 (match_test "aarch64_sve_ld1r_operand_p (op)")))
|
|
|
516
|
|
|
517 ;; Like memory_operand, but restricted to addresses that are valid for
|
|
|
518 ;; SVE LDR and STR instructions.
|
|
|
519 (define_predicate "aarch64_sve_ldr_operand"
|
|
|
520 (and (match_code "mem")
|
|
|
521 (match_test "aarch64_sve_ldr_operand_p (op)")))
|
|
|
522
|
|
|
523 (define_predicate "aarch64_sve_nonimmediate_operand"
|
|
|
524 (ior (match_operand 0 "register_operand")
|
|
|
525 (match_operand 0 "aarch64_sve_ldr_operand")))
|
|
|
526
|
|
|
527 (define_predicate "aarch64_sve_general_operand"
|
|
|
528 (and (match_code "reg,subreg,mem,const,const_vector")
|
|
|
529 (ior (match_operand 0 "register_operand")
|
|
|
530 (match_operand 0 "aarch64_sve_ldr_operand")
|
|
|
531 (match_test "aarch64_mov_operand_p (op, mode)"))))
|
|
|
532
|
|
|
533 (define_predicate "aarch64_sve_struct_memory_operand"
|
|
|
534 (and (match_code "mem")
|
|
|
535 (match_test "aarch64_sve_struct_memory_operand_p (op)")))
|
|
|
536
|
|
|
537 (define_predicate "aarch64_sve_struct_nonimmediate_operand"
|
|
|
538 (ior (match_operand 0 "register_operand")
|
|
|
539 (match_operand 0 "aarch64_sve_struct_memory_operand")))
|
|
|
540
|
|
|
541 ;; Doesn't include immediates, since those are handled by the move
|
|
|
542 ;; patterns instead.
|
|
|
543 (define_predicate "aarch64_sve_dup_operand"
|
|
|
544 (ior (match_operand 0 "register_operand")
|
|
|
545 (match_operand 0 "aarch64_sve_ld1r_operand")))
|
|
|
546
|
|
|
547 (define_predicate "aarch64_sve_arith_immediate"
|
|
|
548 (and (match_code "const,const_vector")
|
|
|
549 (match_test "aarch64_sve_arith_immediate_p (op, false)")))
|
|
|
550
|
|
|
551 (define_predicate "aarch64_sve_sub_arith_immediate"
|
|
|
552 (and (match_code "const,const_vector")
|
|
|
553 (match_test "aarch64_sve_arith_immediate_p (op, true)")))
|
|
|
554
|
|
|
555 (define_predicate "aarch64_sve_inc_dec_immediate"
|
|
|
556 (and (match_code "const,const_vector")
|
|
|
557 (match_test "aarch64_sve_inc_dec_immediate_p (op)")))
|
|
|
558
|
|
|
559 (define_predicate "aarch64_sve_logical_immediate"
|
|
|
560 (and (match_code "const,const_vector")
|
|
|
561 (match_test "aarch64_sve_bitmask_immediate_p (op)")))
|
|
|
562
|
|
|
563 (define_predicate "aarch64_sve_mul_immediate"
|
|
|
564 (and (match_code "const,const_vector")
|
|
|
565 (match_test "aarch64_const_vec_all_same_in_range_p (op, -128, 127)")))
|
|
|
566
|
|
|
567 (define_predicate "aarch64_sve_dup_immediate"
|
|
|
568 (and (match_code "const,const_vector")
|
|
|
569 (match_test "aarch64_sve_dup_immediate_p (op)")))
|
|
|
570
|
|
|
571 (define_predicate "aarch64_sve_cmp_vsc_immediate"
|
|
|
572 (and (match_code "const,const_vector")
|
|
|
573 (match_test "aarch64_sve_cmp_immediate_p (op, true)")))
|
|
|
574
|
|
|
575 (define_predicate "aarch64_sve_cmp_vsd_immediate"
|
|
|
576 (and (match_code "const,const_vector")
|
|
|
577 (match_test "aarch64_sve_cmp_immediate_p (op, false)")))
|
|
|
578
|
|
|
579 (define_predicate "aarch64_sve_index_immediate"
|
|
|
580 (and (match_code "const_int")
|
|
|
581 (match_test "aarch64_sve_index_immediate_p (op)")))
|
|
|
582
|
|
|
583 (define_predicate "aarch64_sve_float_arith_immediate"
|
|
|
584 (and (match_code "const,const_vector")
|
|
|
585 (match_test "aarch64_sve_float_arith_immediate_p (op, false)")))
|
|
|
586
|
|
|
587 (define_predicate "aarch64_sve_float_arith_with_sub_immediate"
|
|
|
588 (and (match_code "const,const_vector")
|
|
|
589 (match_test "aarch64_sve_float_arith_immediate_p (op, true)")))
|
|
|
590
|
|
|
591 (define_predicate "aarch64_sve_float_mul_immediate"
|
|
|
592 (and (match_code "const,const_vector")
|
|
|
593 (match_test "aarch64_sve_float_mul_immediate_p (op)")))
|
|
|
594
|
|
|
595 (define_predicate "aarch64_sve_arith_operand"
|
|
|
596 (ior (match_operand 0 "register_operand")
|
|
|
597 (match_operand 0 "aarch64_sve_arith_immediate")))
|
|
|
598
|
|
|
599 (define_predicate "aarch64_sve_add_operand"
|
|
|
600 (ior (match_operand 0 "aarch64_sve_arith_operand")
|
|
|
601 (match_operand 0 "aarch64_sve_sub_arith_immediate")
|
|
|
602 (match_operand 0 "aarch64_sve_inc_dec_immediate")))
|
|
|
603
|
|
|
604 (define_predicate "aarch64_sve_logical_operand"
|
|
|
605 (ior (match_operand 0 "register_operand")
|
|
|
606 (match_operand 0 "aarch64_sve_logical_immediate")))
|
|
|
607
|
|
|
608 (define_predicate "aarch64_sve_lshift_operand"
|
|
|
609 (ior (match_operand 0 "register_operand")
|
|
|
610 (match_operand 0 "aarch64_simd_lshift_imm")))
|
|
|
611
|
|
|
612 (define_predicate "aarch64_sve_rshift_operand"
|
|
|
613 (ior (match_operand 0 "register_operand")
|
|
|
614 (match_operand 0 "aarch64_simd_rshift_imm")))
|
|
|
615
|
|
|
616 (define_predicate "aarch64_sve_mul_operand"
|
|
|
617 (ior (match_operand 0 "register_operand")
|
|
|
618 (match_operand 0 "aarch64_sve_mul_immediate")))
|
|
|
619
|
|
|
620 (define_predicate "aarch64_sve_cmp_vsc_operand"
|
|
|
621 (ior (match_operand 0 "register_operand")
|
|
|
622 (match_operand 0 "aarch64_sve_cmp_vsc_immediate")))
|
|
|
623
|
|
|
624 (define_predicate "aarch64_sve_cmp_vsd_operand"
|
|
|
625 (ior (match_operand 0 "register_operand")
|
|
|
626 (match_operand 0 "aarch64_sve_cmp_vsd_immediate")))
|
|
|
627
|
|
|
628 (define_predicate "aarch64_sve_index_operand"
|
|
|
629 (ior (match_operand 0 "register_operand")
|
|
|
630 (match_operand 0 "aarch64_sve_index_immediate")))
|
|
|
631
|
|
|
632 (define_predicate "aarch64_sve_float_arith_operand"
|
|
|
633 (ior (match_operand 0 "register_operand")
|
|
|
634 (match_operand 0 "aarch64_sve_float_arith_immediate")))
|
|
|
635
|
|
|
636 (define_predicate "aarch64_sve_float_arith_with_sub_operand"
|
|
|
637 (ior (match_operand 0 "aarch64_sve_float_arith_operand")
|
|
|
638 (match_operand 0 "aarch64_sve_float_arith_with_sub_immediate")))
|
|
|
639
|
|
|
640 (define_predicate "aarch64_sve_float_mul_operand"
|
|
|
641 (ior (match_operand 0 "register_operand")
|
|
|
642 (match_operand 0 "aarch64_sve_float_mul_immediate")))
|
|
|
643
|
|
|
644 (define_predicate "aarch64_sve_vec_perm_operand"
|
|
|
645 (ior (match_operand 0 "register_operand")
|
|
|
646 (match_operand 0 "aarch64_constant_vector_operand")))
|
|
|
647
|
|
|
648 (define_predicate "aarch64_gather_scale_operand_w"
|
|
|
649 (and (match_code "const_int")
|
|
|
650 (match_test "INTVAL (op) == 1 || INTVAL (op) == 4")))
|
|
|
651
|
|
|
652 (define_predicate "aarch64_gather_scale_operand_d"
|
|
|
653 (and (match_code "const_int")
|
|
|
654 (match_test "INTVAL (op) == 1 || INTVAL (op) == 8")))
|
|
|
655
|
|
|
656 ;; A special predicate that doesn't match a particular mode.
|
|
|
657 (define_special_predicate "aarch64_any_register_operand"
|
|
|
658 (match_code "reg"))
|
|
|
659
|
|
|
660 (define_predicate "aarch64_sve_any_binary_operator"
|
|
|
661 (match_code "plus,minus,mult,div,udiv,smax,umax,smin,umin,and,ior,xor"))
|
