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1 ;; DFA scheduling description of the Synopsys DesignWare ARC HS cpu
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2 ;; for GNU C compiler
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3 ;; Copyright (C) 2007-2018 Free Software Foundation, Inc.
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4 ;; Contributor: Claudiu Zissulescu <claudiu.zissulescu@synopsys.com>
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5
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6 ;; This file is part of GCC.
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7
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8 ;; GCC is free software; you can redistribute it and/or modify
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9 ;; it under the terms of the GNU General Public License as published by
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10 ;; the Free Software Foundation; either version 3, or (at your option)
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11 ;; any later version.
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12
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13 ;; GCC is distributed in the hope that it will be useful,
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14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 ;; GNU General Public License for more details.
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17
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 (define_automaton "ARCHS")
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23
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24 (define_cpu_unit "hs_issue, hs_ld_st, divrem_hs, mul_hs, x1, x2" "ARCHS")
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25
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26 (define_insn_reservation "hs_data_load" 4
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27 (and (match_test "TARGET_HS")
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28 (eq_attr "tune" "none")
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29 (eq_attr "type" "load"))
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30 "hs_issue+hs_ld_st,hs_ld_st,nothing*2")
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31
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32 (define_insn_reservation "hs_data_store" 1
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33 (and (match_test "TARGET_HS")
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34 (eq_attr "tune" "none")
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35 (eq_attr "type" "store"))
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36 "hs_issue+hs_ld_st")
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37
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38 ;; Advanced ALU
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39 (define_insn_reservation "hs_alu0" 4
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40 (and (match_test "TARGET_HS")
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41 (eq_attr "tune" "none")
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42 (eq_attr "type" "cc_arith, two_cycle_core, shift, lr, sr"))
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43 "hs_issue+x1,x2, nothing*2")
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44
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45 ;; Basic ALU
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46 (define_insn_reservation "hs_alu1" 4
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47 (and (match_test "TARGET_HS")
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48 (eq_attr "tune" "none")
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49 (eq_attr "type" "move, cmove, unary, binary, compare, misc"))
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50 "hs_issue+x1, nothing*3")
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51
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52 (define_insn_reservation "hs_divrem" 13
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53 (and (match_test "TARGET_HS")
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54 (match_test "TARGET_DIVREM")
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55 (eq_attr "tune" "none")
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56 (eq_attr "type" "div_rem"))
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57 "hs_issue+divrem_hs, (divrem_hs)*12")
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58
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59 (define_insn_reservation "hs_mul" 4
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60 (and (match_test "TARGET_HS")
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61 (eq_attr "tune" "none")
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62 (eq_attr "type" "mul16_em, multi, umulti"))
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63 "hs_issue+mul_hs, nothing*3")
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64
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65 ;; BYPASS Advanced ALU ->
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66 (define_bypass 1 "hs_alu0" "hs_divrem")
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67 (define_bypass 1 "hs_alu0" "hs_mul")
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68 (define_bypass 2 "hs_alu0" "hs_alu0")
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69 (define_bypass 1 "hs_alu0" "hs_alu1")
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70 (define_bypass 1 "hs_alu0" "hs_data_load")
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71 (define_bypass 1 "hs_alu0" "hs_data_store" "store_data_bypass_p")
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72 (define_bypass 2 "hs_alu0" "hs_data_store")
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73
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74 ;; BYPASS Basic ALU ->
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75 (define_bypass 1 "hs_alu1" "hs_alu1")
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76 (define_bypass 1 "hs_alu1" "hs_data_store" "store_data_bypass_p")
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77 (define_bypass 3 "hs_alu1" "hs_mul")
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78 (define_bypass 3 "hs_alu1" "hs_divrem")
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79
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80 ;; BYPASS LD ->
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81 (define_bypass 1 "hs_data_load" "hs_alu1")
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82 (define_bypass 3 "hs_data_load" "hs_divrem")
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83 (define_bypass 3 "hs_data_load" "hs_data_load")
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84 (define_bypass 3 "hs_data_load" "hs_mul")
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85 (define_bypass 1 "hs_data_load" "hs_data_store" "store_data_bypass_p")
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86
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87 ;; BYPASS MPY ->
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88 (define_bypass 3 "hs_mul" "hs_mul")
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89 (define_bypass 1 "hs_mul" "hs_alu1")
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90 (define_bypass 3 "hs_mul" "hs_divrem")
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91 (define_bypass 1 "hs_mul" "hs_data_store" "store_data_bypass_p")
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