Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/arm/arm.opt @ 131:84e7813d76e9
gcc-8.2
| author | mir3636 |
|---|---|
| date | Thu, 25 Oct 2018 07:37:49 +0900 |
| parents | 04ced10e8804 |
| children | 1830386684a0 |
| rev | line source |
|---|---|
| 0 | 1 ; Options for the ARM port of the compiler. |
| 2 | |
| 131 | 3 ; Copyright (C) 2005-2018 Free Software Foundation, Inc. |
| 0 | 4 ; |
| 5 ; This file is part of GCC. | |
| 6 ; | |
| 7 ; GCC is free software; you can redistribute it and/or modify it under | |
| 8 ; the terms of the GNU General Public License as published by the Free | |
| 9 ; Software Foundation; either version 3, or (at your option) any later | |
| 10 ; version. | |
| 11 ; | |
| 12 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
| 13 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 14 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 15 ; for more details. | |
| 16 ; | |
| 17 ; You should have received a copy of the GNU General Public License | |
| 18 ; along with GCC; see the file COPYING3. If not see | |
| 19 ; <http://www.gnu.org/licenses/>. | |
| 20 | |
| 111 | 21 HeaderInclude |
| 22 config/arm/arm-opts.h | |
| 23 | |
| 24 TargetSave | |
| 25 const char *x_arm_arch_string | |
| 26 | |
| 27 TargetSave | |
| 28 const char *x_arm_cpu_string | |
| 29 | |
| 30 TargetSave | |
| 31 const char *x_arm_tune_string | |
| 32 | |
| 33 Enum | |
| 34 Name(tls_type) Type(enum arm_tls_type) | |
| 35 TLS dialect to use: | |
| 36 | |
| 37 EnumValue | |
| 38 Enum(tls_type) String(gnu) Value(TLS_GNU) | |
| 39 | |
| 40 EnumValue | |
| 41 Enum(tls_type) String(gnu2) Value(TLS_GNU2) | |
| 42 | |
| 0 | 43 mabi= |
| 111 | 44 Target RejectNegative Joined Enum(arm_abi_type) Var(arm_abi) Init(ARM_DEFAULT_ABI) |
| 45 Specify an ABI. | |
| 46 | |
| 47 Enum | |
| 48 Name(arm_abi_type) Type(enum arm_abi_type) | |
| 49 Known ARM ABIs (for use with the -mabi= option): | |
| 50 | |
| 51 EnumValue | |
| 52 Enum(arm_abi_type) String(apcs-gnu) Value(ARM_ABI_APCS) | |
| 53 | |
| 54 EnumValue | |
| 55 Enum(arm_abi_type) String(atpcs) Value(ARM_ABI_ATPCS) | |
| 56 | |
| 57 EnumValue | |
| 58 Enum(arm_abi_type) String(aapcs) Value(ARM_ABI_AAPCS) | |
| 59 | |
| 60 EnumValue | |
| 61 Enum(arm_abi_type) String(iwmmxt) Value(ARM_ABI_IWMMXT) | |
| 62 | |
| 63 EnumValue | |
| 64 Enum(arm_abi_type) String(aapcs-linux) Value(ARM_ABI_AAPCS_LINUX) | |
| 0 | 65 |
| 66 mabort-on-noreturn | |
| 67 Target Report Mask(ABORT_NORETURN) | |
| 111 | 68 Generate a call to abort if a noreturn function returns. |
| 0 | 69 |
| 70 mapcs | |
| 111 | 71 Target RejectNegative Mask(APCS_FRAME) Undocumented |
| 0 | 72 |
| 73 mapcs-frame | |
| 74 Target Report Mask(APCS_FRAME) | |
| 111 | 75 Generate APCS conformant stack frames. |
| 0 | 76 |
| 77 mapcs-reentrant | |
| 78 Target Report Mask(APCS_REENT) | |
| 111 | 79 Generate re-entrant, PIC code. |
| 0 | 80 |
| 81 mapcs-stack-check | |
| 82 Target Report Mask(APCS_STACK) Undocumented | |
| 83 | |
| 84 march= | |
| 111 | 85 Target RejectNegative ToLower Joined Var(arm_arch_string) |
| 86 Specify the name of the target architecture. | |
| 87 | |
| 88 ; Other arm_arch values are loaded from arm-tables.opt | |
| 89 ; but that is a generated file and this is an odd-one-out. | |
| 90 EnumValue | |
| 91 Enum(arm_arch) String(native) Value(-1) DriverOnly | |
| 0 | 92 |
| 93 marm | |
| 111 | 94 Target Report RejectNegative Negative(mthumb) InverseMask(THUMB) |
| 95 Generate code in 32 bit ARM state. | |
| 0 | 96 |
| 97 mbig-endian | |
| 111 | 98 Target Report RejectNegative Negative(mlittle-endian) Mask(BIG_END) |
| 99 Assume target CPU is configured as big endian. | |
| 0 | 100 |
| 101 mcallee-super-interworking | |
| 102 Target Report Mask(CALLEE_INTERWORKING) | |
| 111 | 103 Thumb: Assume non-static functions may be called from ARM code. |
| 0 | 104 |
| 105 mcaller-super-interworking | |
| 106 Target Report Mask(CALLER_INTERWORKING) | |
| 111 | 107 Thumb: Assume function pointers may go to non-Thumb aware code. |
| 0 | 108 |
| 109 mcpu= | |
| 111 | 110 Target RejectNegative ToLower Joined Var(arm_cpu_string) |
| 111 Specify the name of the target CPU. | |
| 0 | 112 |
| 113 mfloat-abi= | |
| 111 | 114 Target RejectNegative Joined Enum(float_abi_type) Var(arm_float_abi) Init(TARGET_DEFAULT_FLOAT_ABI) |
| 115 Specify if floating point hardware should be used. | |
| 116 | |
| 117 mcmse | |
| 118 Target RejectNegative Var(use_cmse) | |
| 119 Specify that the compiler should target secure code as per ARMv8-M Security Extensions. | |
| 120 | |
| 121 Enum | |
| 122 Name(float_abi_type) Type(enum float_abi_type) | |
| 123 Known floating-point ABIs (for use with the -mfloat-abi= option): | |
| 0 | 124 |
| 111 | 125 EnumValue |
| 126 Enum(float_abi_type) String(soft) Value(ARM_FLOAT_ABI_SOFT) | |
| 127 | |
| 128 EnumValue | |
| 129 Enum(float_abi_type) String(softfp) Value(ARM_FLOAT_ABI_SOFTFP) | |
| 130 | |
| 131 EnumValue | |
| 132 Enum(float_abi_type) String(hard) Value(ARM_FLOAT_ABI_HARD) | |
| 133 | |
| 134 mflip-thumb | |
| 135 Target Report Var(TARGET_FLIP_THUMB) Undocumented | |
| 136 Switch ARM/Thumb modes on alternating functions for compiler testing. | |
| 0 | 137 |
|
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77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
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138 mfp16-format= |
| 111 | 139 Target RejectNegative Joined Enum(arm_fp16_format_type) Var(arm_fp16_format) Init(ARM_FP16_FORMAT_NONE) |
| 140 Specify the __fp16 floating-point format. | |
| 141 | |
| 142 Enum | |
| 143 Name(arm_fp16_format_type) Type(enum arm_fp16_format_type) | |
| 144 Known __fp16 formats (for use with the -mfp16-format= option): | |
|
55
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
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145 |
| 111 | 146 EnumValue |
| 147 Enum(arm_fp16_format_type) String(none) Value(ARM_FP16_FORMAT_NONE) | |
| 0 | 148 |
| 111 | 149 EnumValue |
| 150 Enum(arm_fp16_format_type) String(ieee) Value(ARM_FP16_FORMAT_IEEE) | |
| 151 | |
| 152 EnumValue | |
| 153 Enum(arm_fp16_format_type) String(alternative) Value(ARM_FP16_FORMAT_ALTERNATIVE) | |
| 0 | 154 |
| 155 mfpu= | |
| 111 | 156 Target RejectNegative Joined Enum(arm_fpu) Var(arm_fpu_index) Init(TARGET_FPU_auto) Save |
| 157 Specify the name of the target floating point hardware/format. | |
| 0 | 158 |
| 159 mhard-float | |
| 111 | 160 Target RejectNegative Alias(mfloat-abi=, hard) Undocumented |
| 0 | 161 |
| 162 mlittle-endian | |
| 111 | 163 Target Report RejectNegative Negative(mbig-endian) InverseMask(BIG_END) |
| 164 Assume target CPU is configured as little endian. | |
| 0 | 165 |
| 166 mlong-calls | |
| 167 Target Report Mask(LONG_CALLS) | |
| 111 | 168 Generate call insns as indirect calls, if necessary. |
| 169 | |
| 170 mpic-data-is-text-relative | |
| 171 Target Report Var(arm_pic_data_is_text_relative) Init(TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE) | |
| 172 Assume data segments are relative to text segment. | |
| 0 | 173 |
| 174 mpic-register= | |
| 175 Target RejectNegative Joined Var(arm_pic_register_string) | |
| 111 | 176 Specify the register to be used for PIC addressing. |
| 0 | 177 |
| 178 mpoke-function-name | |
| 179 Target Report Mask(POKE_FUNCTION_NAME) | |
| 111 | 180 Store function names in object code. |
| 0 | 181 |
| 182 msched-prolog | |
| 183 Target Report Mask(SCHED_PROLOG) | |
| 111 | 184 Permit scheduling of a function's prologue sequence. |
| 0 | 185 |
| 186 msingle-pic-base | |
| 187 Target Report Mask(SINGLE_PIC_BASE) | |
| 111 | 188 Do not load the PIC register in function prologues. |
| 0 | 189 |
| 190 msoft-float | |
| 111 | 191 Target RejectNegative Alias(mfloat-abi=, soft) Undocumented |
| 0 | 192 |
| 193 mstructure-size-boundary= | |
| 111 | 194 Target RejectNegative Joined UInteger Var(arm_structure_size_boundary) Init(DEFAULT_STRUCTURE_SIZE_BOUNDARY) |
| 195 Specify the minimum bit alignment of structures. (Deprecated). | |
| 0 | 196 |
| 197 mthumb | |
| 111 | 198 Target Report RejectNegative Negative(marm) Mask(THUMB) Save |
| 199 Generate code for Thumb state. | |
| 0 | 200 |
| 201 mthumb-interwork | |
| 202 Target Report Mask(INTERWORK) | |
| 111 | 203 Support calls between Thumb and ARM instruction sets. |
| 204 | |
| 205 mtls-dialect= | |
| 206 Target RejectNegative Joined Enum(tls_type) Var(target_tls_dialect) Init(TLS_GNU) | |
| 207 Specify thread local storage scheme. | |
| 0 | 208 |
| 209 mtp= | |
| 111 | 210 Target RejectNegative Joined Enum(arm_tp_type) Var(target_thread_pointer) Init(TP_AUTO) |
| 211 Specify how to access the thread pointer. | |
| 212 | |
| 213 Enum | |
| 214 Name(arm_tp_type) Type(enum arm_tp_type) | |
| 215 Valid arguments to -mtp=: | |
| 216 | |
| 217 EnumValue | |
| 218 Enum(arm_tp_type) String(soft) Value(TP_SOFT) | |
| 219 | |
| 220 EnumValue | |
| 221 Enum(arm_tp_type) String(auto) Value(TP_AUTO) | |
| 222 | |
| 223 EnumValue | |
| 224 Enum(arm_tp_type) String(cp15) Value(TP_CP15) | |
| 0 | 225 |
| 226 mtpcs-frame | |
| 227 Target Report Mask(TPCS_FRAME) | |
| 111 | 228 Thumb: Generate (non-leaf) stack frames even if not needed. |
| 0 | 229 |
| 230 mtpcs-leaf-frame | |
| 231 Target Report Mask(TPCS_LEAF_FRAME) | |
| 111 | 232 Thumb: Generate (leaf) stack frames even if not needed. |
| 0 | 233 |
| 234 mtune= | |
| 111 | 235 Target RejectNegative ToLower Joined Var(arm_tune_string) |
| 236 Tune code for the given processor. | |
| 0 | 237 |
| 111 | 238 mprint-tune-info |
| 239 Target Report RejectNegative Var(print_tune_info) Init(0) | |
| 240 Print CPU tuning information as comment in assembler file. This is | |
| 241 an option used only for regression testing of the compiler and not | |
| 242 intended for ordinary use in compiling code. | |
| 243 | |
| 244 ; Other processor_type values are loaded from arm-tables.opt | |
| 245 ; but that is a generated file and this is an odd-one-out. | |
| 246 EnumValue | |
| 247 Enum(processor_type) String(native) Value(-1) DriverOnly | |
| 0 | 248 |
| 249 mvectorize-with-neon-quad | |
| 111 | 250 Target Report RejectNegative InverseMask(NEON_VECTORIZE_DOUBLE) |
| 251 Use Neon quad-word (rather than double-word) registers for vectorization. | |
| 252 | |
| 253 mvectorize-with-neon-double | |
| 254 Target Report RejectNegative Mask(NEON_VECTORIZE_DOUBLE) | |
| 255 Use Neon double-word (rather than quad-word) registers for vectorization. | |
| 0 | 256 |
| 131 | 257 mverbose-cost-dump |
| 258 Common Undocumented Var(arm_verbose_cost) Init(0) | |
| 259 Enable more verbose RTX cost dumps during debug. For GCC developers use only. | |
| 260 | |
| 0 | 261 mword-relocations |
| 262 Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS) | |
| 263 Only generate absolute relocations on word sized values. | |
| 264 | |
| 111 | 265 mrestrict-it |
| 266 Target Report Var(arm_restrict_it) Init(2) Save | |
| 267 Generate IT blocks appropriate for ARMv8. | |
| 268 | |
| 0 | 269 mfix-cortex-m3-ldrd |
| 270 Target Report Var(fix_cm3_ldrd) Init(2) | |
| 271 Avoid overlapping destination and address registers on LDRD instructions | |
| 272 that may trigger Cortex-M3 errata. | |
| 111 | 273 |
| 274 munaligned-access | |
| 275 Target Report Var(unaligned_access) Init(2) Save | |
| 276 Enable unaligned word and halfword accesses to packed data. | |
| 277 | |
| 278 mneon-for-64bits | |
| 279 Target Report RejectNegative Var(use_neon_for_64bits) Init(0) | |
| 280 Use Neon to perform 64-bits operations rather than core registers. | |
| 281 | |
| 282 mslow-flash-data | |
| 283 Target Report Var(target_slow_flash_data) Init(0) | |
| 284 Assume loading data from flash is slower than fetching instructions. | |
| 285 | |
| 286 masm-syntax-unified | |
| 287 Target Report Var(inline_asm_unified) Init(0) Save | |
| 288 Assume unified syntax for inline assembly code. | |
| 289 | |
| 290 mpure-code | |
| 291 Target Report Var(target_pure_code) Init(0) | |
| 292 Do not allow constant data to be placed in code sections. | |
| 293 | |
| 294 mbe8 | |
| 295 Target Report RejectNegative Negative(mbe32) Mask(BE8) | |
| 296 When linking for big-endian targets, generate a BE8 format image. | |
| 297 | |
| 298 mbe32 | |
| 299 Target Report RejectNegative Negative(mbe8) InverseMask(BE8) | |
| 300 When linking for big-endian targets, generate a legacy BE32 format image. | |
| 131 | 301 |
| 302 mbranch-cost= | |
| 303 Target RejectNegative Joined UInteger Var(arm_branch_cost) Init(-1) | |
| 304 Cost to assume for a branch insn. |