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annotate gcc/config/arm/cortex-m4.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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1 ;; ARM Cortex-M4 pipeline description
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2 ;; Copyright (C) 2010-2018 Free Software Foundation, Inc.
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3 ;; Contributed by CodeSourcery.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but
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13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 ;; General Public License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_automaton "cortex_m4")
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22
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23 ;; We model the pipelining of LDR instructions by using two artificial units.
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24
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25 (define_cpu_unit "cortex_m4_a" "cortex_m4")
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26
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27 (define_cpu_unit "cortex_m4_b" "cortex_m4")
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28
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29 (define_reservation "cortex_m4_ex" "cortex_m4_a+cortex_m4_b")
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30
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31 ;; ALU and multiply is one cycle.
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32 (define_insn_reservation "cortex_m4_alu" 1
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33 (and (eq_attr "tune" "cortexm4")
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34 (ior (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
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35 alu_sreg,alus_sreg,logic_reg,logics_reg,\
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36 adc_imm,adcs_imm,adc_reg,adcs_reg,\
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37 adr,bfm,clz,rbit,rev,alu_dsp_reg,\
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38 shift_imm,shift_reg,extend,\
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39 alu_shift_imm,alus_shift_imm,\
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40 logic_shift_imm,logics_shift_imm,\
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41 alu_shift_reg,alus_shift_reg,\
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42 logic_shift_reg,logics_shift_reg,\
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43 mov_imm,mov_reg,mov_shift,mov_shift_reg,\
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44 mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
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45 mrs,multiple,no_insn")
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46 (ior (eq_attr "mul32" "yes")
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47 (eq_attr "mul64" "yes"))))
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48 "cortex_m4_ex")
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49
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50 ;; Byte, half-word and word load is two cycles.
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51 (define_insn_reservation "cortex_m4_load1" 2
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52 (and (eq_attr "tune" "cortexm4")
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53 (eq_attr "type" "load_byte,load_4"))
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54 "cortex_m4_a, cortex_m4_b")
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55
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56 ;; str rx, [ry, #imm] is always one cycle.
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57 (define_insn_reservation "cortex_m4_store1_1" 1
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58 (and (and (eq_attr "tune" "cortexm4")
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59 (eq_attr "type" "store_4"))
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60 (match_test "arm_address_offset_is_imm (insn)"))
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61 "cortex_m4_a")
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62
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63 ;; Other byte, half-word and word load is two cycles.
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64 (define_insn_reservation "cortex_m4_store1_2" 2
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65 (and (and (eq_attr "tune" "cortexm4")
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66 (eq_attr "type" "store_4"))
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67 (not (match_test "arm_address_offset_is_imm (insn)")))
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68 "cortex_m4_a*2")
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69
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70 (define_insn_reservation "cortex_m4_load2" 3
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71 (and (eq_attr "tune" "cortexm4")
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72 (eq_attr "type" "load_8"))
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73 "cortex_m4_ex*3")
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74
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75 (define_insn_reservation "cortex_m4_store2" 3
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76 (and (eq_attr "tune" "cortexm4")
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77 (eq_attr "type" "store_8"))
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78 "cortex_m4_ex*3")
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79
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80 (define_insn_reservation "cortex_m4_load3" 4
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81 (and (eq_attr "tune" "cortexm4")
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82 (eq_attr "type" "load_12"))
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83 "cortex_m4_ex*4")
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84
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85 (define_insn_reservation "cortex_m4_store3" 4
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86 (and (eq_attr "tune" "cortexm4")
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87 (eq_attr "type" "store_12"))
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88 "cortex_m4_ex*4")
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89
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90 (define_insn_reservation "cortex_m4_load4" 5
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91 (and (eq_attr "tune" "cortexm4")
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92 (eq_attr "type" "load_16"))
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93 "cortex_m4_ex*5")
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94
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95 (define_insn_reservation "cortex_m4_store4" 5
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96 (and (eq_attr "tune" "cortexm4")
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97 (eq_attr "type" "store_16"))
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98 "cortex_m4_ex*5")
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99
111
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100 (define_bypass 1 "cortex_m4_load1"
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101 "cortex_m4_store1_1,cortex_m4_store1_2"
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102 "arm_no_early_store_addr_dep")
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103
68
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104 ;; If the address of load or store depends on the result of the preceding
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105 ;; instruction, the latency is increased by one.
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106
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107 (define_bypass 2 "cortex_m4_alu"
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108 "cortex_m4_load1"
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109 "arm_early_load_addr_dep")
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110
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111 (define_bypass 2 "cortex_m4_alu"
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112 "cortex_m4_store1_1,cortex_m4_store1_2"
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113 "arm_early_store_addr_dep")
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114
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115 (define_insn_reservation "cortex_m4_branch" 3
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116 (and (eq_attr "tune" "cortexm4")
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117 (eq_attr "type" "branch"))
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118 "cortex_m4_ex*3")
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119
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120 (define_insn_reservation "cortex_m4_call" 3
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121 (and (eq_attr "tune" "cortexm4")
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122 (eq_attr "type" "call"))
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123 "cortex_m4_ex*3")
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124
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125 (define_insn_reservation "cortex_m4_block" 1
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126 (and (eq_attr "tune" "cortexm4")
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127 (eq_attr "type" "block"))
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128 "cortex_m4_ex")