Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/arm/vec-common.md @ 131:84e7813d76e9
gcc-8.2
| author | mir3636 |
|---|---|
| date | Thu, 25 Oct 2018 07:37:49 +0900 |
| parents | 04ced10e8804 |
| children | 1830386684a0 |
| rev | line source |
|---|---|
| 0 | 1 ;; Machine Description for shared bits common to IWMMXT and Neon. |
| 131 | 2 ;; Copyright (C) 2006-2018 Free Software Foundation, Inc. |
| 0 | 3 ;; Written by CodeSourcery. |
| 4 ;; | |
| 5 ;; This file is part of GCC. | |
| 6 ;; | |
| 7 ;; GCC is free software; you can redistribute it and/or modify it | |
| 8 ;; under the terms of the GNU General Public License as published by | |
| 9 ;; the Free Software Foundation; either version 3, or (at your option) | |
| 10 ;; any later version. | |
| 11 ;; | |
| 12 ;; GCC is distributed in the hope that it will be useful, but | |
| 13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 15 ;; General Public License for more details. | |
| 16 ;; | |
| 17 ;; You should have received a copy of the GNU General Public License | |
| 18 ;; along with GCC; see the file COPYING3. If not see | |
| 19 ;; <http://www.gnu.org/licenses/>. | |
| 20 | |
| 21 ;; Vector Moves | |
| 22 | |
| 23 (define_expand "mov<mode>" | |
| 24 [(set (match_operand:VALL 0 "nonimmediate_operand" "") | |
| 25 (match_operand:VALL 1 "general_operand" ""))] | |
| 26 "TARGET_NEON | |
| 27 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" | |
| 28 { | |
|
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29 if (can_create_pseudo_p ()) |
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30 { |
| 111 | 31 if (!REG_P (operands[0])) |
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32 operands[1] = force_reg (<MODE>mode, operands[1]); |
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33 else if (TARGET_NEON && CONSTANT_P (operands[1])) |
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34 { |
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35 operands[1] = neon_make_constant (operands[1]); |
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36 gcc_assert (operands[1] != NULL_RTX); |
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37 } |
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38 } |
| 0 | 39 }) |
| 40 | |
| 41 ;; Vector arithmetic. Expanders are blank, then unnamed insns implement | |
| 42 ;; patterns separately for IWMMXT and Neon. | |
| 43 | |
| 44 (define_expand "add<mode>3" | |
| 45 [(set (match_operand:VALL 0 "s_register_operand" "") | |
| 46 (plus:VALL (match_operand:VALL 1 "s_register_operand" "") | |
| 47 (match_operand:VALL 2 "s_register_operand" "")))] | |
|
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48 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) |
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49 || flag_unsafe_math_optimizations)) |
| 0 | 50 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" |
| 51 { | |
| 52 }) | |
| 53 | |
| 54 (define_expand "sub<mode>3" | |
| 55 [(set (match_operand:VALL 0 "s_register_operand" "") | |
| 56 (minus:VALL (match_operand:VALL 1 "s_register_operand" "") | |
| 57 (match_operand:VALL 2 "s_register_operand" "")))] | |
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58 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) |
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59 || flag_unsafe_math_optimizations)) |
| 0 | 60 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" |
| 61 { | |
| 62 }) | |
| 63 | |
| 64 (define_expand "mul<mode>3" | |
| 65 [(set (match_operand:VALLW 0 "s_register_operand" "") | |
| 66 (mult:VALLW (match_operand:VALLW 1 "s_register_operand" "") | |
| 67 (match_operand:VALLW 2 "s_register_operand" "")))] | |
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68 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) |
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69 || flag_unsafe_math_optimizations)) |
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70 || (<MODE>mode == V4HImode && TARGET_REALLY_IWMMXT)" |
| 0 | 71 { |
| 72 }) | |
| 73 | |
| 74 (define_expand "smin<mode>3" | |
| 75 [(set (match_operand:VALLW 0 "s_register_operand" "") | |
| 76 (smin:VALLW (match_operand:VALLW 1 "s_register_operand" "") | |
| 77 (match_operand:VALLW 2 "s_register_operand" "")))] | |
|
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78 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) |
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parents:
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79 || flag_unsafe_math_optimizations)) |
| 0 | 80 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" |
| 81 { | |
| 82 }) | |
| 83 | |
| 84 (define_expand "umin<mode>3" | |
| 85 [(set (match_operand:VINTW 0 "s_register_operand" "") | |
| 86 (umin:VINTW (match_operand:VINTW 1 "s_register_operand" "") | |
| 87 (match_operand:VINTW 2 "s_register_operand" "")))] | |
| 88 "TARGET_NEON | |
| 89 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" | |
| 90 { | |
| 91 }) | |
| 92 | |
| 93 (define_expand "smax<mode>3" | |
| 94 [(set (match_operand:VALLW 0 "s_register_operand" "") | |
| 95 (smax:VALLW (match_operand:VALLW 1 "s_register_operand" "") | |
| 96 (match_operand:VALLW 2 "s_register_operand" "")))] | |
|
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parents:
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diff
changeset
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97 "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) |
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
55
diff
changeset
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98 || flag_unsafe_math_optimizations)) |
| 0 | 99 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" |
| 100 { | |
| 101 }) | |
| 102 | |
| 103 (define_expand "umax<mode>3" | |
| 104 [(set (match_operand:VINTW 0 "s_register_operand" "") | |
| 105 (umax:VINTW (match_operand:VINTW 1 "s_register_operand" "") | |
| 106 (match_operand:VINTW 2 "s_register_operand" "")))] | |
| 107 "TARGET_NEON | |
| 108 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" | |
| 109 { | |
| 110 }) | |
| 111 | 111 |
| 112 (define_expand "vec_perm<mode>" | |
| 113 [(match_operand:VE 0 "s_register_operand" "") | |
| 114 (match_operand:VE 1 "s_register_operand" "") | |
| 115 (match_operand:VE 2 "s_register_operand" "") | |
| 116 (match_operand:VE 3 "s_register_operand" "")] | |
| 117 "TARGET_NEON && !BYTES_BIG_ENDIAN" | |
| 118 { | |
| 119 arm_expand_vec_perm (operands[0], operands[1], operands[2], operands[3]); | |
| 120 DONE; | |
| 121 }) |