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111
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1 /* Target Definitions for TI C6X.
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131
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2 Copyright (C) 2010-2018 Free Software Foundation, Inc.
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111
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3 Contributed by Andrew Jenner <andrew@codesourcery.com>
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4 Contributed by Bernd Schmidt <bernds@codesourcery.com>
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5
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6 This file is part of GCC.
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7
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8 GCC is free software; you can redistribute it and/or modify it
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9 under the terms of the GNU General Public License as published
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10 by the Free Software Foundation; either version 3, or (at your
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11 option) any later version.
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12
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13 GCC is distributed in the hope that it will be useful, but WITHOUT
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14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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16 License for more details.
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17
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18 You should have received a copy of the GNU General Public License
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19 along with GCC; see the file COPYING3. If not see
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20 <http://www.gnu.org/licenses/>. */
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21
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22 #ifndef GCC_C6X_H
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23 #define GCC_C6X_H
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24
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25 /* Feature bit definitions that enable specific insns. */
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26 #define C6X_INSNS_C62X 1
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27 #define C6X_INSNS_C64X 2
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28 #define C6X_INSNS_C64XP 4
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29 #define C6X_INSNS_C67X 8
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30 #define C6X_INSNS_C67XP 16
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31 #define C6X_INSNS_C674X 32
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32 #define C6X_INSNS_ATOMIC 64
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33 #define C6X_INSNS_ALL_CPU_BITS 127
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34
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35 #define C6X_DEFAULT_INSN_MASK \
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36 (C6X_INSNS_C62X | C6X_INSNS_C64X | C6X_INSNS_C64XP)
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37
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38 /* A mask of allowed insn types, as defined above. */
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39 extern unsigned long c6x_insn_mask;
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40
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41 /* Value of -march= */
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42 extern c6x_cpu_t c6x_arch;
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43 #define C6X_DEFAULT_ARCH C6X_CPU_C64XP
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44
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45 /* True if the target has C64x instructions. */
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46 #define TARGET_INSNS_64 ((c6x_insn_mask & C6X_INSNS_C64X) != 0)
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47 /* True if the target has C64x+ instructions. */
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48 #define TARGET_INSNS_64PLUS ((c6x_insn_mask & C6X_INSNS_C64XP) != 0)
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49 /* True if the target has C67x instructions. */
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50 #define TARGET_INSNS_67 ((c6x_insn_mask & C6X_INSNS_C67X) != 0)
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51 /* True if the target has C67x+ instructions. */
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52 #define TARGET_INSNS_67PLUS ((c6x_insn_mask & C6X_INSNS_C67XP) != 0)
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53
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54 /* True if the target supports doubleword loads. */
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55 #define TARGET_LDDW (TARGET_INSNS_64 || TARGET_INSNS_67)
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56 /* True if the target supports doubleword loads. */
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57 #define TARGET_STDW TARGET_INSNS_64
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58 /* True if the target supports the MPY32 family of instructions. */
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59 #define TARGET_MPY32 TARGET_INSNS_64PLUS
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60 /* True if the target has floating point hardware. */
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61 #define TARGET_FP TARGET_INSNS_67
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62 /* True if the target has C67x+ floating point extensions. */
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63 #define TARGET_FP_EXT TARGET_INSNS_67PLUS
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64
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65 #define TARGET_DEFAULT 0
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66
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67 /* Run-time Target. */
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68
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69 #define TARGET_CPU_CPP_BUILTINS() \
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70 do \
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71 { \
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72 builtin_assert ("machine=tic6x"); \
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73 builtin_assert ("cpu=tic6x"); \
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74 builtin_define ("__TMS320C6X__"); \
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75 builtin_define ("_TMS320C6X"); \
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76 \
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77 if (TARGET_DSBT) \
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78 builtin_define ("__DSBT__"); \
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79 \
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80 if (TARGET_BIG_ENDIAN) \
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81 builtin_define ("_BIG_ENDIAN"); \
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82 else \
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83 builtin_define ("_LITTLE_ENDIAN"); \
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84 \
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85 switch (c6x_arch) \
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86 { \
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87 case unk_isa: \
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88 break; \
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89 case C6X_CPU_C62X: \
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90 builtin_define ("_TMS320C6200"); \
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91 break; \
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92 \
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93 case C6X_CPU_C64XP: \
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94 builtin_define ("_TMS320C6400_PLUS"); \
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95 /* fall through */ \
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96 case C6X_CPU_C64X: \
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97 builtin_define ("_TMS320C6400"); \
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98 break; \
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99 \
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100 case C6X_CPU_C67XP: \
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101 builtin_define ("_TMS320C6700_PLUS"); \
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102 /* fall through */ \
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103 case C6X_CPU_C67X: \
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104 builtin_define ("_TMS320C6700"); \
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105 break; \
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106 \
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107 case C6X_CPU_C674X: \
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108 builtin_define ("_TMS320C6740"); \
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109 builtin_define ("_TMS320C6700_PLUS"); \
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110 builtin_define ("_TMS320C6700"); \
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111 builtin_define ("_TMS320C6400_PLUS"); \
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112 builtin_define ("_TMS320C6400"); \
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113 break; \
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114 } \
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115 } while (0)
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116
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117 #define OPTION_DEFAULT_SPECS \
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118 {"arch", "%{!march=*:-march=%(VALUE)}" }
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119
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120 /* Storage Layout. */
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121
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122 #define BITS_BIG_ENDIAN 0
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123 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
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124 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
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125
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126 #define REG_WORDS_BIG_ENDIAN 0
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127
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128 #define UNITS_PER_WORD 4
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129 #define PARM_BOUNDARY 8
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130 #define STACK_BOUNDARY 64
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131 #define FUNCTION_BOUNDARY 32
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132 #define BIGGEST_ALIGNMENT 64
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133 #define STRICT_ALIGNMENT 1
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134
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135 /* The ABI requires static arrays must be at least 8 byte aligned.
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136 Really only externally visible arrays must be aligned this way, as
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137 only those are directly visible from another compilation unit. But
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138 we don't have that information available here. */
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139 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
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140 (((ALIGN) < BITS_PER_UNIT * 8 && TREE_CODE (TYPE) == ARRAY_TYPE) \
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141 ? BITS_PER_UNIT * 8 : (ALIGN))
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142
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143 /* Type Layout. */
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144
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145 #define DEFAULT_SIGNED_CHAR 1
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146
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147 #undef SIZE_TYPE
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148 #define SIZE_TYPE "unsigned int"
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149 #undef PTRDIFF_TYPE
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150 #define PTRDIFF_TYPE "int"
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151
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152 /* Registers. */
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153
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154 #define FIRST_PSEUDO_REGISTER 67
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155 #define FIXED_REGISTERS \
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156 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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157 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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158 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
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159 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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160 1, 1, 1}
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161 #define CALL_USED_REGISTERS \
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162 { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
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163 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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164 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, \
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165 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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166 1, 1, 1}
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167
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168 /* This lists call-used non-predicate registers first, followed by call-used
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169 registers, followed by predicate registers. We want to avoid allocating
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170 the predicate registers for other uses as much as possible. */
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171 #define REG_ALLOC_ORDER \
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172 { \
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173 REG_A0, REG_A3, REG_A4, REG_A5, REG_A6, REG_A7, REG_A8, REG_A9, \
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174 REG_A16, REG_A17, REG_A18, REG_A19, REG_A20, REG_A21, REG_A22, REG_A23, \
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175 REG_A24, REG_A25, REG_A26, REG_A27, REG_A28, REG_A29, REG_A30, REG_A31, \
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176 REG_B4, REG_B5, REG_B6, REG_B7, REG_B8, REG_B9, REG_B16, \
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177 REG_B17, REG_B18, REG_B19, REG_B20, REG_B21, REG_B22, REG_B23, REG_B24, \
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178 REG_B25, REG_B26, REG_B27, REG_B28, REG_B29, REG_B30, REG_B31, \
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179 REG_A10, REG_A11, REG_A12, REG_A13, REG_A14, REG_A15, \
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180 REG_B3, REG_B10, REG_B11, REG_B12, REG_B13, REG_B14, REG_B15, \
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181 REG_A1, REG_A2, REG_B0, REG_B1, REG_B2, REG_ILC \
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182 }
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183
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184 /* Register Classes. */
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185
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186 enum reg_class
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187 {
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188 NO_REGS,
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189 PREDICATE_A_REGS,
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190 PREDICATE_B_REGS,
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191 PREDICATE_REGS,
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192 PICREG,
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193 SPREG,
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194 CALL_USED_B_REGS,
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195 NONPREDICATE_A_REGS,
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196 NONPREDICATE_B_REGS,
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197 NONPREDICATE_REGS,
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198 A_REGS,
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199 B_REGS,
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200 GENERAL_REGS,
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201 ALL_REGS,
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202 LIM_REG_CLASSES
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203 };
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204
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205 #define N_REG_CLASSES (int) LIM_REG_CLASSES
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206
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207 #define REG_CLASS_NAMES { \
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208 "NO_REGS", \
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209 "PREDICATE_A_REGS", \
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210 "PREDICATE_B_REGS", \
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211 "PREDICATE_REGS", \
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212 "PICREG", \
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213 "SPREG", \
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214 "CALL_USED_B_REGS", \
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215 "NONPREDICATE_A_REGS", \
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216 "NONPREDICATE_B_REGS", \
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217 "NONPREDICATE_REGS", \
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218 "A_REGS", \
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219 "B_REGS", \
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220 "GENERAL_REGS", \
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221 "ALL_REGS" }
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222
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223 #define REG_CLASS_CONTENTS \
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224 { \
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225 /* NO_REGS. */ \
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226 { 0x00000000, 0x00000000, 0 }, \
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227 /* PREDICATE_A_REGS. */ \
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228 { 0x00000006, 0x00000000, 0 }, \
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229 /* PREDICATE_B_REGS. */ \
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230 { 0x00000000, 0x00000007, 0 }, \
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231 /* PREDICATE_REGS. */ \
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232 { 0x00000006, 0x00000007, 0 }, \
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233 /* PICREG. */ \
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234 { 0x00000000, 0x00004000, 0 }, \
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235 /* SPREG. */ \
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236 { 0x00000000, 0x00008000, 0 }, \
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237 /* CALL_USED_B_REGS. */ \
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238 { 0x00000000, 0xFFFF03FF, 0 }, \
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239 /* NONPREDICATE_A_REGS. */ \
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240 { 0xFFFFFFF9, 0x00000000, 0 }, \
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241 /* NONPREDICATE_B_REGS. */ \
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242 { 0x00000000, 0xFFFFFFF8, 0 }, \
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243 /* NONPREDICATE_REGS. */ \
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244 { 0xFFFFFFF9, 0xFFFFFFF8, 0 }, \
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245 /* A_REGS. */ \
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246 { 0xFFFFFFFF, 0x00000000, 3 }, \
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247 /* B_REGS. */ \
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248 { 0x00000000, 0xFFFFFFFF, 3 }, \
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249 /* GENERAL_REGS. */ \
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250 { 0xFFFFFFFF, 0xFFFFFFFF, 3 }, \
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251 /* ALL_REGS. */ \
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252 { 0xFFFFFFFF, 0xFFFFFFFF, 7 }, \
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253 }
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254
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255 #define A_REGNO_P(N) ((N) <= REG_A31)
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256 #define B_REGNO_P(N) ((N) >= REG_B0 && (N) <= REG_B31)
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257
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258 #define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X)))
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259 #define CROSS_OPERANDS(X0,X1) \
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260 (A_REG_P (X0) == A_REG_P (X1) ? CROSS_N : CROSS_Y)
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261
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262 #define REGNO_REG_CLASS(reg) \
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263 ((reg) >= REG_A1 && (reg) <= REG_A2 ? PREDICATE_A_REGS \
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264 : (reg) == REG_A0 && TARGET_INSNS_64 ? PREDICATE_A_REGS \
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265 : (reg) >= REG_B0 && (reg) <= REG_B2 ? PREDICATE_B_REGS \
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266 : A_REGNO_P (reg) ? NONPREDICATE_A_REGS \
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267 : call_used_regs[reg] ? CALL_USED_B_REGS : B_REGS)
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268
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269 #define BASE_REG_CLASS ALL_REGS
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270 #define INDEX_REG_CLASS ALL_REGS
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271
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272 #define REGNO_OK_FOR_BASE_STRICT_P(X) \
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273 ((X) < FIRST_PSEUDO_REGISTER \
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274 || (reg_renumber[X] >= 0 && reg_renumber[X] < FIRST_PSEUDO_REGISTER))
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275 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X) 1
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276
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277 #define REGNO_OK_FOR_INDEX_STRICT_P(X) \
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278 ((X) < FIRST_PSEUDO_REGISTER \
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279 || (reg_renumber[X] >= 0 && reg_renumber[X] < FIRST_PSEUDO_REGISTER))
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280 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(X) 1
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281
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282 #ifdef REG_OK_STRICT
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283 #define REGNO_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_STRICT_P (X)
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284 #define REGNO_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_STRICT_P (X)
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285 #else
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286 #define REGNO_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_NONSTRICT_P (X)
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287 #define REGNO_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_NONSTRICT_P (X)
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288 #endif
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289
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290 #define CLASS_MAX_NREGS(class, mode) \
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291 ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
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292
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293 #define REGNO_OK_FOR_INDIRECT_JUMP_P(REGNO, MODE) B_REGNO_P (REGNO)
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294
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295 /* Stack and Calling. */
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296
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297 /* SP points to 4 bytes below the first word of the frame. */
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298 #define STACK_POINTER_OFFSET 4
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299 /* Likewise for AP (which is the incoming stack pointer). */
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300 #define FIRST_PARM_OFFSET(fundecl) 4
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301 #define FRAME_GROWS_DOWNWARD 1
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302 #define STACK_GROWS_DOWNWARD 1
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303
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304 #define STACK_POINTER_REGNUM REG_B15
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305 #define HARD_FRAME_POINTER_REGNUM REG_A15
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306 /* These two always get eliminated in favour of the stack pointer
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307 or the hard frame pointer. */
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308 #define FRAME_POINTER_REGNUM REG_FRAME
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309 #define ARG_POINTER_REGNUM REG_ARGP
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310
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311 #define PIC_OFFSET_TABLE_REGNUM REG_B14
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312
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313 /* We keep the stack pointer constant rather than using push/pop
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314 instructions. */
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315 #define ACCUMULATE_OUTGOING_ARGS 1
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316
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317 /* Before the prologue, the return address is in the B3 register. */
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318 #define RETURN_ADDR_REGNO REG_B3
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319 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNO)
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320 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (RETURN_ADDR_REGNO)
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321
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322 #define RETURN_ADDR_RTX(COUNT, FRAME) c6x_return_addr_rtx (COUNT)
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323
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324 #define INCOMING_FRAME_SP_OFFSET 0
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325 #define ARG_POINTER_CFA_OFFSET(fundecl) 0
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326
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327 #define STATIC_CHAIN_REGNUM REG_A2
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328
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329 struct c6x_args {
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330 /* Number of arguments to pass in registers. */
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331 int nregs;
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332 /* Number of arguments passed in registers so far. */
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333 int count;
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334 };
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335
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336 #define CUMULATIVE_ARGS struct c6x_args
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337
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338 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
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339 c6x_init_cumulative_args (&cum, fntype, libname, n_named_args)
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340
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341 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
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342 (c6x_block_reg_pad_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD)
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343
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344 #define FUNCTION_ARG_REGNO_P(r) \
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345 (((r) >= REG_A4 && (r) <= REG_A13) || ((r) >= REG_B4 && (r) <= REG_B13))
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346
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347 #define DEFAULT_PCC_STRUCT_RETURN 0
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348
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349 #define FUNCTION_PROFILER(file, labelno) \
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350 fatal_error (input_location, \
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351 "profiling is not yet implemented for this architecture")
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352
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353
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354 /* Trampolines. */
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355 #define TRAMPOLINE_SIZE 32
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356 #define TRAMPOLINE_ALIGNMENT 256
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357
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358 #define ELIMINABLE_REGS \
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359 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
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360 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
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361 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
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362 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
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363
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364 /* Define the offset between two registers, one to be eliminated, and the other
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365 its replacement, at the start of a routine. */
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366
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367 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
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368 ((OFFSET) = c6x_initial_elimination_offset ((FROM), (TO)))
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369
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370 /* Addressing Modes. */
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371
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372 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P(x) && GET_CODE(x) != CONST_DOUBLE)
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373 #define MAX_REGS_PER_ADDRESS 2
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374
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375 #define HAVE_PRE_DECREMENT 1
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376 #define HAVE_POST_DECREMENT 1
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377 #define HAVE_PRE_INCREMENT 1
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378 #define HAVE_POST_INCREMENT 1
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379
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380 /* Register forms are available, but due to scaling we currently don't
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381 support them. */
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382 #define HAVE_PRE_MODIFY_DISP 1
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383 #define HAVE_POST_MODIFY_DISP 1
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384
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385 #define LEGITIMATE_PIC_OPERAND_P(X) \
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386 (!symbolic_operand (X, SImode))
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387
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388 struct GTY(()) machine_function
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389 {
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390 /* True if we expanded a sibling call. */
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391 int contains_sibcall;
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392 };
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393
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394 /* Costs. */
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395 #define NO_FUNCTION_CSE 1
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396
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397 #define SLOW_BYTE_ACCESS 0
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398
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399 #define BRANCH_COST(speed_p, predictable_p) 6
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400
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401
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402 /* Model costs for the vectorizer. */
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403
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404 /* Cost of conditional branch. */
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405 #ifndef TARG_COND_BRANCH_COST
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406 #define TARG_COND_BRANCH_COST 6
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407 #endif
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408
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409 /* Cost of any scalar operation, excluding load and store. */
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410 #ifndef TARG_SCALAR_STMT_COST
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411 #define TARG_SCALAR_STMT_COST 1
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412 #endif
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413
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414 /* Cost of scalar load. */
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415 #undef TARG_SCALAR_LOAD_COST
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416 #define TARG_SCALAR_LOAD_COST 2 /* load + rotate */
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417
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418 /* Cost of scalar store. */
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419 #undef TARG_SCALAR_STORE_COST
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420 #define TARG_SCALAR_STORE_COST 10
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421
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422 /* Cost of any vector operation, excluding load, store,
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423 or vector to scalar operation. */
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424 #undef TARG_VEC_STMT_COST
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425 #define TARG_VEC_STMT_COST 1
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426
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427 /* Cost of vector to scalar operation. */
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428 #undef TARG_VEC_TO_SCALAR_COST
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429 #define TARG_VEC_TO_SCALAR_COST 1
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430
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431 /* Cost of scalar to vector operation. */
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432 #undef TARG_SCALAR_TO_VEC_COST
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433 #define TARG_SCALAR_TO_VEC_COST 1
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434
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435 /* Cost of aligned vector load. */
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436 #undef TARG_VEC_LOAD_COST
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437 #define TARG_VEC_LOAD_COST 1
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438
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439 /* Cost of misaligned vector load. */
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440 #undef TARG_VEC_UNALIGNED_LOAD_COST
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441 #define TARG_VEC_UNALIGNED_LOAD_COST 2
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442
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443 /* Cost of vector store. */
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444 #undef TARG_VEC_STORE_COST
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445 #define TARG_VEC_STORE_COST 1
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446
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447 /* Cost of vector permutation. */
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448 #ifndef TARG_VEC_PERMUTE_COST
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449 #define TARG_VEC_PERMUTE_COST 1
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450 #endif
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451
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452 /* ttype entries (the only interesting data references used) are
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453 sb-relative got-indirect (aka .ehtype). */
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454 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \
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455 (((code) == 0 && (data) == 1) ? (DW_EH_PE_datarel | DW_EH_PE_indirect) \
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456 : DW_EH_PE_absptr)
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457
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458 /* This should be the same as the definition in elfos.h, plus the call
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459 to output special unwinding directives. */
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460 #undef ASM_DECLARE_FUNCTION_NAME
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461 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
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462 do \
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463 { \
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464 c6x_output_file_unwind (FILE); \
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465 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function"); \
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466 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
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467 ASM_OUTPUT_LABEL (FILE, NAME); \
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468 } \
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469 while (0)
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470
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471 /* This should be the same as the definition in elfos.h, plus the call
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472 to output special unwinding directives. */
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473 #undef ASM_DECLARE_FUNCTION_SIZE
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474 #define ASM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
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475 c6x_function_end (STREAM, NAME)
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476
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477 /* Arbitrarily choose A4/A5. */
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478 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N) + 4 : INVALID_REGNUM)
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479
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480 /* The register that holds the return address in exception handlers. */
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481 #define C6X_EH_STACKADJ_REGNUM 3
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482 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, C6X_EH_STACKADJ_REGNUM)
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483
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484
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485 /* Assembler Format. */
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486
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487 #define DWARF2_ASM_LINE_DEBUG_INFO 1
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488
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489 #undef ASM_APP_ON
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490 #define ASM_APP_ON "\t; #APP \n"
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491 #undef ASM_APP_OFF
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492 #define ASM_APP_OFF "\t; #NO_APP \n"
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493
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494 #define ASM_OUTPUT_COMMON(stream, name, size, rounded)
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495 #define ASM_OUTPUT_LOCAL(stream, name, size, rounded)
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496
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497 #define GLOBAL_ASM_OP "\t.global\t"
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498
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499 #define REGISTER_NAMES \
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500 { \
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501 "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", \
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502 "A8", "A9", "A10", "A11", "A12", "A13", "A14", "A15", \
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503 "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23", \
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|
504 "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31", \
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505 "B0", "B1", "B2", "B3", "B4", "B5", "B6", "B7", \
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|
506 "B8", "B9", "B10", "B11", "B12", "B13", "B14", "B15", \
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|
507 "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23", \
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508 "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31", \
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|
509 "FP", "ARGP", "ILC" }
|
|
|
510
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|
|
511 #define DBX_REGISTER_NUMBER(N) (dbx_register_map[(N)])
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512
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|
|
513 extern unsigned const dbx_register_map[FIRST_PSEUDO_REGISTER];
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|
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514
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|
|
515 #define FINAL_PRESCAN_INSN c6x_final_prescan_insn
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|
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516
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|
|
517 #define TEXT_SECTION_ASM_OP ".text;"
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|
|
518 #define DATA_SECTION_ASM_OP ".data;"
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519
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520 #define ASM_OUTPUT_ALIGN(stream, power) \
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521 do \
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|
|
522 { \
|
|
|
523 if (power) \
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|
524 fprintf ((stream), "\t.align\t%d\n", power); \
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|
|
525 } \
|
|
|
526 while (0)
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|
527
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|
|
528 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
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|
529 do { char __buf[256]; \
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|
|
530 fprintf (FILE, "\t.long\t"); \
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|
|
531 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
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|
|
532 assemble_name (FILE, __buf); \
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|
|
533 fputc ('\n', FILE); \
|
|
|
534 } while (0)
|
|
|
535
|
|
|
536 /* Determine whether to place EXP (an expression or a decl) should be
|
|
|
537 placed into one of the small data sections. */
|
|
|
538 #define PLACE_IN_SDATA_P(EXP) \
|
|
|
539 (c6x_sdata_mode == C6X_SDATA_NONE ? false \
|
|
|
540 : c6x_sdata_mode == C6X_SDATA_ALL ? true \
|
|
|
541 : !AGGREGATE_TYPE_P (TREE_TYPE (EXP)))
|
|
|
542
|
|
|
543 #define SCOMMON_ASM_OP "\t.scomm\t"
|
|
|
544
|
|
|
545 #undef ASM_OUTPUT_ALIGNED_DECL_COMMON
|
|
|
546 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(FILE, DECL, NAME, SIZE, ALIGN) \
|
|
|
547 do \
|
|
|
548 { \
|
|
|
549 if (DECL != NULL && PLACE_IN_SDATA_P (DECL)) \
|
|
|
550 fprintf ((FILE), "%s", SCOMMON_ASM_OP); \
|
|
|
551 else \
|
|
|
552 fprintf ((FILE), "%s", COMMON_ASM_OP); \
|
|
|
553 assemble_name ((FILE), (NAME)); \
|
|
|
554 fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\
|
|
|
555 } \
|
|
|
556 while (0)
|
|
|
557
|
|
|
558 /* This says how to output assembler code to declare an
|
|
|
559 uninitialized internal linkage data object. */
|
|
|
560
|
|
|
561 #undef ASM_OUTPUT_ALIGNED_DECL_LOCAL
|
|
|
562 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(FILE, DECL, NAME, SIZE, ALIGN) \
|
|
|
563 do { \
|
|
|
564 if (PLACE_IN_SDATA_P (DECL)) \
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|
|
565 switch_to_section (sbss_section); \
|
|
|
566 else \
|
|
|
567 switch_to_section (bss_section); \
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|
|
568 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \
|
|
|
569 if (!flag_inhibit_size_directive) \
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|
|
570 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
|
|
|
571 ASM_OUTPUT_ALIGN ((FILE), exact_log2((ALIGN) / BITS_PER_UNIT)); \
|
|
|
572 ASM_OUTPUT_LABEL(FILE, NAME); \
|
|
|
573 ASM_OUTPUT_SKIP((FILE), (SIZE) ? (SIZE) : 1); \
|
|
|
574 } while (0)
|
|
|
575
|
|
|
576 #define CASE_VECTOR_PC_RELATIVE flag_pic
|
|
|
577 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
|
|
|
578
|
|
|
579 #define ADDR_VEC_ALIGN(VEC) (JUMP_TABLES_IN_TEXT_SECTION ? 5 : 2)
|
|
|
580
|
|
|
581 /* This is how to output an element of a case-vector that is relative. */
|
|
|
582 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
|
|
|
583 do { char buf[100]; \
|
|
|
584 fputs ("\t.long ", FILE); \
|
|
|
585 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
|
|
|
586 assemble_name (FILE, buf); \
|
|
|
587 putc ('-', FILE); \
|
|
|
588 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
|
|
|
589 assemble_name (FILE, buf); \
|
|
|
590 putc ('\n', FILE); \
|
|
|
591 } while (0)
|
|
|
592
|
|
|
593 /* Misc. */
|
|
|
594
|
|
|
595 #define CASE_VECTOR_MODE SImode
|
|
|
596 #define MOVE_MAX 4
|
|
|
597 #define MOVE_RATIO(SPEED) 4
|
|
|
598 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
|
|
|
599 #define Pmode SImode
|
|
|
600 #define FUNCTION_MODE QImode
|
|
|
601
|
|
|
602 #define CPU_UNITS_QUERY 1
|
|
|
603
|
|
|
604 extern int c6x_initial_flag_pic;
|
|
|
605
|
|
|
606 #endif /* GCC_C6X_H */
|
