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annotate gcc/config/csky/csky_insn_fpu.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents
children 1830386684a0
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131
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1 ;; C-SKY FPU instruction descriptions.
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2 ;; Copyright (C) 2018 Free Software Foundation, Inc.
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3 ;; Contributed by C-SKY Microsystems and Mentor Graphics.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but
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13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 ;; General Public License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>. */
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20
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21 ;; -------------------------------------------------------------------------
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22 ;; Float Abs instructions
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23 ;; -------------------------------------------------------------------------
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24
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25 (define_insn "abssf2"
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26 [(set (match_operand:SF 0 "register_operand" "=v,r")
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27 (abs:SF (match_operand:SF 1 "register_operand" "v, r")))]
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28 "CSKY_ISA_FEATURE (fpv2_sf)"
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29 "@
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30 fabss\t%0, %1
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31 bclri\t%0, %1, 31")
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32
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33 (define_insn "absdf2"
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34 [(set (match_operand:DF 0 "register_operand" "=v")
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35 (abs:DF (match_operand:DF 1 "register_operand" "v")))]
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36 "CSKY_ISA_FEATURE (fpv2_df)"
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37 "fabsd\t%0, %1")
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38
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39
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40 ;; -------------------------------------------------------------------------
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41 ;; Float Neg instructions
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42 ;; -------------------------------------------------------------------------
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43
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44 (define_insn "negsf2"
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45 [(set (match_operand:SF 0 "register_operand" "=v")
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46 (neg:SF (match_operand:SF 1 "register_operand" "v")))]
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47 "CSKY_ISA_FEATURE (fpv2_sf)"
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48 "fnegs\t%0, %1")
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49
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50 (define_insn "negdf2"
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51 [(set (match_operand:DF 0 "register_operand" "=v")
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52 (neg:DF (match_operand:DF 1 "register_operand" "v")))]
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53 "CSKY_ISA_FEATURE (fpv2_df)"
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54 "fnegd\t%0, %1")
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55
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56
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57 ;; -------------------------------------------------------------------------
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58 ;; Float Sqrt instructions
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59 ;; -------------------------------------------------------------------------
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60
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61 (define_insn "sqrtsf2"
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62 [(set (match_operand:SF 0 "register_operand" "=v")
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63 (sqrt:SF (match_operand:SF 1 "register_operand" "v")))]
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64 "CSKY_ISA_FEATURE (fpv2_sf)"
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65 "fsqrts\t%0, %1")
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66
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67 (define_insn "sqrtdf2"
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68 [(set (match_operand:DF 0 "register_operand" "=v")
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69 (sqrt:DF (match_operand:DF 1 "register_operand" "v")))]
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70 "CSKY_ISA_FEATURE (fpv2_divd)"
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71 "fsqrtd\t%0, %1")
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72
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73
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74 ;; -------------------------------------------------------------------------
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75 ;; Float Add instructions
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76 ;; -------------------------------------------------------------------------
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77
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78 (define_insn "addsf3"
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79 [(set (match_operand:SF 0 "register_operand" "=v")
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80 (plus:SF (match_operand:SF 1 "register_operand" "v")
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81 (match_operand:SF 2 "register_operand" "v")))]
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82 "CSKY_ISA_FEATURE (fpv2_sf)"
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83 "fadds\t%0, %1, %2")
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84
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85 (define_insn "adddf3"
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86 [(set (match_operand:DF 0 "register_operand" "=v")
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87 (plus:DF (match_operand:DF 1 "register_operand" "v")
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88 (match_operand:DF 2 "register_operand" "v")))]
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89 "CSKY_ISA_FEATURE (fpv2_df)"
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90 "faddd\t%0, %1, %2")
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91
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92
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93 ;; -------------------------------------------------------------------------
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94 ;; Float Sub instructions
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95 ;; -------------------------------------------------------------------------
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96
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97 (define_insn "subsf3"
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98 [(set (match_operand:SF 0 "register_operand" "=v")
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99 (minus:SF (match_operand:SF 1 "register_operand" "v")
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100 (match_operand:SF 2 "register_operand" "v")))]
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101 "CSKY_ISA_FEATURE (fpv2_sf)"
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102 "fsubs\t%0, %1, %2")
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103
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104 (define_insn "subdf3"
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105 [(set (match_operand:DF 0 "register_operand" "=v")
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106 (minus:DF (match_operand:DF 1 "register_operand" "v")
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107 (match_operand:DF 2 "register_operand" "v")))]
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108 "CSKY_ISA_FEATURE (fpv2_df)"
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109 "fsubd\t%0, %1, %2")
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110
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111
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112 ;; -------------------------------------------------------------------------
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113 ;; Float Mul instructions
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114 ;; -------------------------------------------------------------------------
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115
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116 (define_insn "mulsf3"
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117 [(set (match_operand:SF 0 "register_operand" "=v")
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118 (mult:SF (match_operand:SF 1 "register_operand" "v")
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119 (match_operand:SF 2 "register_operand" "v")))]
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120 "CSKY_ISA_FEATURE (fpv2_sf)"
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121 "fmuls\t%0, %1, %2")
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122
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123 (define_insn "muldf3"
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124 [(set (match_operand:DF 0 "register_operand" "=v")
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125 (mult:DF (match_operand:DF 1 "register_operand" "v")
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126 (match_operand:DF 2 "register_operand" "v")))]
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127 "CSKY_ISA_FEATURE (fpv2_df)"
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128 "fmuld\t%0, %1, %2")
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129
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130 (define_insn "*fpuv2_nmulsf3_1"
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131 [(set (match_operand:SF 0 "register_operand" "=v")
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132 (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "%v"))
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133 (match_operand:SF 2 "register_operand" "v")))]
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134 "CSKY_ISA_FEATURE (fpv2_sf)"
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135 "fnmuls\t%0, %1, %2")
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136
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137 (define_insn "*fpuv2_nmulsf3_2"
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138 [(set (match_operand:SF 0 "register_operand" "=v")
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139 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "v")
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140 (match_operand:SF 2 "register_operand" "v"))))]
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141 "CSKY_ISA_FEATURE (fpv2_sf)"
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142 "fnmuls\t%0, %1, %2")
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143
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144 (define_insn "*fpuv2_nmuldf3_1"
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145 [(set (match_operand:DF 0 "register_operand" "=v")
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146 (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "%v"))
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147 (match_operand:DF 2 "register_operand" "v")))]
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148 "CSKY_ISA_FEATURE (fpv2_df)"
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149 "fnmuld\t%0, %1, %2")
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150
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151 (define_insn "*fpuv2_nmuldf3_2"
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152 [(set (match_operand:DF 0 "register_operand" "=v")
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153 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "v")
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154 (match_operand:DF 2 "register_operand" "v"))))]
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155 "CSKY_ISA_FEATURE (fpv2_df)"
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156 "fnmuld\t%0, %1, %2")
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157
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158
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159 ;; -------------------------------------------------------------------------
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160 ;; Float Div instructions
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161 ;; -------------------------------------------------------------------------
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162
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163 (define_expand "divsf3"
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164 [(set (match_operand:SF 0 "register_operand" "")
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165 (div:SF (match_operand:SF 1 "csky_arith_float1_operand" "")
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166 (match_operand:SF 2 "register_operand" "")))]
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167 "CSKY_ISA_FEATURE (fpv2_sf)"
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168 "")
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169
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170 (define_insn "*fpuv2_divsf3"
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171 [(set (match_operand:SF 0 "register_operand" "=v")
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172 (div:SF (match_operand:SF 1 "register_operand" "v")
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173 (match_operand:SF 2 "register_operand" "v")))]
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174 "CSKY_ISA_FEATURE (fpv2_sf)"
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175 "fdivs\t%0, %1, %2")
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176
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177 (define_insn "*fpuv2_1_divsf3"
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178 [(set (match_operand:SF 0 "register_operand" "=v")
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179 (div:SF (match_operand:SF 1 "csky_const_float1_operand" "i")
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180 (match_operand:SF 2 "register_operand" "v")))]
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181 "CSKY_ISA_FEATURE (fpv2_sf)"
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182 "frecips\t%0, %2")
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183
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184
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185 (define_expand "divdf3"
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186 [(set (match_operand:DF 0 "register_operand" "")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
187 (div:DF (match_operand:DF 1 "csky_arith_float1_operand" "")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
188 (match_operand:DF 2 "register_operand" "")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
189 "CSKY_ISA_FEATURE (fpv2_divd)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
190 "")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
191
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
192 (define_insn "*fpuv2_divdf3"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
193 [(set (match_operand:DF 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
194 (div:DF (match_operand:DF 1 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
195 (match_operand:DF 2 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
196 "CSKY_ISA_FEATURE (fpv2_divd)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
197 "fdivd\t%0, %1, %2")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
198
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
199 (define_insn "*fpuv2_1_divdf3"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
200 [(set (match_operand:DF 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
201 (div:DF (match_operand:DF 1 "csky_const_float1_operand" "i")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
202 (match_operand:DF 2 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
203 "CSKY_ISA_FEATURE (fpv2_divd)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
204 "frecipd\t%0, %2")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
205
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
206
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
207 ;; -------------------------------------------------------------------------
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
208 ;; Float add(sub) with mult instructions
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
209 ;; -------------------------------------------------------------------------
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
210
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
211 ;; vrz <= vrz + vrx * vry
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
212 (define_insn "*fpuv2_fmacs"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
213 [(set (match_operand:SF 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
214 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
215 (match_operand:SF 2 "register_operand" "v"))
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
216 (match_operand:SF 3 "register_operand" "0")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
217 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
218 "fmacs\t%0, %1, %2")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
219
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
220 (define_insn "*fpuv2_fmacd"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
221 [(set (match_operand:DF 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
222 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
223 (match_operand:DF 2 "register_operand" "v"))
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
224 (match_operand:DF 3 "register_operand" "0")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
225 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
226 "fmacd\t%0, %1, %2")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
227
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
228 ;; vrz <= vrz - vrx * vry
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
229 (define_insn "*fpuv2_fnmacs"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
230 [(set (match_operand:SF 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
231 (minus:SF (match_operand:SF 1 "register_operand" "0")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
232 (mult:SF (match_operand:SF 2 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
233 (match_operand:SF 3 "register_operand" "v"))))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
234 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
235 "fnmacs\t%0, %2, %3")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
236
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
237 (define_insn "*fpuv2_fnmacd"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
238 [(set (match_operand:DF 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
239 (minus:DF (match_operand:DF 1 "register_operand" "0")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
240 (mult:DF (match_operand:DF 2 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
241 (match_operand:DF 3 "register_operand" "v"))))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
242 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
243 "fnmacd\t%0, %2, %3")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
244
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
245 ;; vrz <= vrx * vry - vrz
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
246 (define_insn "*fpuv2_fmscs"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
247 [(set (match_operand:SF 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
248 (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
249 (match_operand:SF 2 "register_operand" "v"))
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
250 (match_operand:SF 3 "register_operand" "0")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
251 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
252 "fmscs\t%0, %1, %2")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
253
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
254 (define_insn "*fpuv2_fmscd"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
255 [(set (match_operand:DF 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
256 (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
257 (match_operand:DF 2 "register_operand" "v"))
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
258 (match_operand:DF 3 "register_operand" "0")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
259 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
260 "fmscd\t%0, %1, %2")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
261
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
262 ;; vrz = - (vrz + vrx * vry)
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
263 (define_insn "*fpuv2_fnmscs_1"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
264 [(set (match_operand:SF 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
265 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "%v"))
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
266 (match_operand:SF 2 "register_operand" "v"))
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
267 (match_operand:SF 3 "register_operand" "0")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
268 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
269 "fnmscs\t%0, %1, %2")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
270
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
271 (define_insn "*fpuv2_fnmscs_2"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
272 [(set (match_operand:SF 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
273 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
274 (match_operand:SF 2 "register_operand" "v"))
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
275 (match_operand:SF 3 "register_operand" "0"))))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
276 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
277 "fnmscs\t%0, %1, %2")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
278
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
279 (define_insn "*fpuv2_fnmscd_1"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
280 [(set (match_operand:DF 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
281 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "%v"))
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
282 (match_operand:DF 2 "register_operand" "v"))
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
283 (match_operand:DF 3 "register_operand" "0")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
284 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
285 "fnmscd\t%0, %1, %2")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
286
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
287 (define_insn "*fpuv2_fnmscd_2"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
288 [(set (match_operand:DF 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
289 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
290 (match_operand:DF 2 "register_operand" "v"))
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
291 (match_operand:DF 3 "register_operand" "0"))))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
292 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
293 "fnmscd\t%0, %1, %2")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
294
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
295
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
296 ;; -------------------------------------------------------------------------
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
297 ;; Float compare instructions
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
298 ;; -------------------------------------------------------------------------
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
299
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
300 (define_expand "cbranchsf4"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
301 [(set (pc) (if_then_else (match_operator 0 "csky_float_comparison_operator"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
302 [(match_operand:SF 1 "register_operand")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
303 (match_operand:SF 2 "csky_compare_operand_float")])
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
304 (label_ref (match_operand 3 ""))
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
305 (pc)))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
306 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
307 "
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
308 {
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
309 enum rtx_code code = GET_CODE (operands[0]);
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
310 bool invert = csky_emit_compare_float (code, operands[1], operands[2]);
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
311
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
312 if (invert)
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
313 emit_jump_insn (gen_csky_jbf (operands[3]));
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
314 else
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
315 emit_jump_insn (gen_csky_jbt (operands[3]));
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
316
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
317 DONE;
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
318 }")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
319
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
320 (define_insn "*fpuv2_unordered"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
321 [(set (reg:CC 33) (unordered:CC (match_operand:SF 0 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
322 (match_operand:SF 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
323 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
324 "fcmpuos\t%0, %1")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
325
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
326 (define_insn "*fpuv2_unordered_zero"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
327 [(set (reg:CC 33) (unordered:CC (match_operand:SF 0 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
328 (match_operand:SF 1 "csky_const_float0_operand" "i")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
329 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
330 "fcmpuos\t%0, %0")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
331
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
332 (define_insn "*fpuv2_ne"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
333 [(set (reg:CC 33) (ne:CC (match_operand:SF 0 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
334 (match_operand:SF 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
335 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
336 "fcmpnes\t%0, %1")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
337
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
338 (define_insn "*fpuv2_gt"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
339 [(set (reg:CC 33) (gt:CC (match_operand:SF 0 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
340 (match_operand:SF 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
341 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
342 "fcmplts\t%1, %0")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
343
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
344 (define_insn "*fpuv2_ge"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
345 [(set (reg:CC 33) (ge:CC (match_operand:SF 0 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
346 (match_operand:SF 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
347 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
348 "fcmphss\t%0, %1")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
349
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
350 (define_insn "*fpuv2_lt"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
351 [(set (reg:CC 33) (lt:CC (match_operand:SF 0 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
352 (match_operand:SF 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
353 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
354 "fcmplts\t%0, %1")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
355
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
356 (define_insn "*fpuv2_le"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
357 [(set (reg:CC 33) (le:CC (match_operand:SF 0 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
358 (match_operand:SF 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
359 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
360 "fcmphss\t%1, %0")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
361
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
362 (define_insn "*fpuv2_gez"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
363 [(set (reg:CC 33) (ge:CC (match_operand:SF 0 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
364 (match_operand:SF 1 "csky_const_float0_operand" "i")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
365 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
366 "fcmpzhss\t%0")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
367
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
368 (define_insn "*fpuv2_nez"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
369 [(set (reg:CC 33) (ne:CC (match_operand:SF 0 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
370 (match_operand:SF 1 "csky_const_float0_operand" "i")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
371 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
372 "fcmpznes\t%0")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
373
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
374
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
375 (define_expand "cbranchdf4"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
376 [(set (pc) (if_then_else (match_operator 0 "csky_float_comparison_operator"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
377 [(match_operand:DF 1 "register_operand")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
378 (match_operand:DF 2 "csky_compare_operand_float")])
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
379 (label_ref (match_operand 3 ""))
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
380 (pc)))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
381 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
382 "
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
383 {
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
384 enum rtx_code code = GET_CODE (operands[0]);
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
385 bool invert = csky_emit_compare_float (code, operands[1], operands[2]);
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
386
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
387 if (invert)
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
388 emit_jump_insn (gen_csky_jbf (operands[3]));
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
389 else
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
390 emit_jump_insn (gen_csky_jbt (operands[3]));
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
391
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
392 DONE;
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
393 }")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
394
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
395 (define_insn "*fpuv2_dunordered"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
396 [(set (reg:CC 33) (unordered:CC (match_operand:DF 0 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
397 (match_operand:DF 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
398 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
399 "fcmpuod\t%0, %1")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
400
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
401 (define_insn "*fpuv2_dunordered_zero"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
402 [(set (reg:CC 33) (unordered:CC (match_operand:DF 0 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
403 (match_operand:DF 1 "csky_const_float0_operand" "i")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
404 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
405 "fcmpuod\t%0, %0")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
406
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
407 (define_insn "*fpuv2_dne"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
408 [(set (reg:CC 33) (ne:CC (match_operand:DF 0 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
409 (match_operand:DF 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
410 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
411 "fcmpned\t%0, %1")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
412
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
413 (define_insn "*fpuv2_dgt"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
414 [(set (reg:CC 33) (gt:CC (match_operand:DF 0 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
415 (match_operand:DF 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
416 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
417 "fcmpltd\t%1, %0")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
418
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
419 (define_insn "*fpuv2_dge"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
420 [(set (reg:CC 33) (ge:CC (match_operand:DF 0 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
421 (match_operand:DF 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
422 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
423 "fcmphsd\t%0, %1")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
424
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
425 (define_insn "*fpuv2_dlt"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
426 [(set (reg:CC 33) (lt:CC (match_operand:DF 0 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
427 (match_operand:DF 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
428 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
429 "fcmpltd\t%0, %1")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
430
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
431 (define_insn "*fpuv2_dle"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
432 [(set (reg:CC 33) (le:CC (match_operand:DF 0 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
433 (match_operand:DF 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
434 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
435 "fcmphsd\t%1, %0")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
436
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
437 (define_insn "*fpuv2_dgez"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
438 [(set (reg:CC 33) (ge:CC (match_operand:DF 0 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
439 (match_operand:DF 1 "csky_const_float0_operand" "i")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
440 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
441 "fcmpzhsd\t%0")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
442
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
443 (define_insn "*fpuv2_dnez"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
444 [(set (reg:CC 33) (ne:CC (match_operand:DF 0 "register_operand" "v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
445 (match_operand:DF 1 "csky_const_float0_operand" "i")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
446 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
447 "fcmpzned\t%0")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
448
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
449
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
450 ;; -------------------------------------------------------------------------
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
451 ;; Float convert instructions
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
452 ;; -------------------------------------------------------------------------
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
453
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
454 ;; DF <- SF
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
455 (define_insn "extendsfdf2"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
456 [(set (match_operand:DF 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
457 (float_extend:DF (match_operand:SF 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
458 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
459 "fstod\t%0, %1")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
460
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
461 ;; SF <- DF
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
462 (define_insn "truncdfsf2"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
463 [(set (match_operand:SF 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
464 (float_truncate:SF (match_operand:DF 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
465 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
466 "fdtos\t%0, %1")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
467
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
468 ;; SF <- SI
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
469 (define_insn "floatsisf2"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
470 [(set (match_operand:SF 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
471 (float:SF (match_operand:SI 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
472 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
473 "fsitos\t%0, %1")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
474
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
475 ;; DF <- SI
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
476 (define_insn "floatsidf2"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
477 [(set (match_operand:DF 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
478 (float:DF (match_operand:SI 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
479 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
480 "fsitod\t%0, %1")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
481
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
482 ;; SF <- unsigned SI
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
483 (define_insn "floatunssisf2"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
484 [(set (match_operand:SF 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
485 (unsigned_float:SF (match_operand:SI 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
486 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
487 "fuitos\t%0, %1")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
488
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
489 ;; DF <- unsigned SI
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
490 (define_insn "floatunssidf2"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
491 [(set (match_operand:DF 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
492 (unsigned_float:DF (match_operand:SI 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
493 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
494 "fuitod\t%0, %1")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
495
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
496 ;; SI <- SF
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
497 (define_insn "fix_truncsfsi2"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
498 [(set (match_operand:SI 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
499 (fix:SI (match_operand:SF 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
500 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
501 "fstosi.rz\t%0, %1")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
502
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
503 ;; SI <- DF
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
504 (define_insn "fix_truncdfsi2"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
505 [(set (match_operand:SI 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
506 (fix:SI (match_operand:DF 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
507 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
508 "fdtosi.rz\t%0, %1")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
509
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
510 ;; unsigned SI <- SF
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
511 (define_insn "fixuns_truncsfsi2"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
512 [(set (match_operand:SI 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
513 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
514 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
515 "fstoui.rz\t%0, %1")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
516
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
517 ;; unsigned SI <- DF
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
518 (define_insn "fixuns_truncdfsi2"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
519 [(set (match_operand:SI 0 "register_operand" "=v")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
520 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "v")))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
521 "CSKY_ISA_FEATURE (fpv2_df)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
522 "fdtoui.rz\t%0, %1")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
523
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
524
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
525 ;; -------------------------------------------------------------------------
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
526 ;; Float mov instructions
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
527 ;; -------------------------------------------------------------------------
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
528
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
529 ;; Note: movsf and movdf patterns are in csky.md.
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
530
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
531 ;; cstore SF
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
532 (define_expand "cstoresf4"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
533 [(set (match_operand:SI 0 "register_operand" "")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
534 (match_operator 1 "ordered_comparison_operator"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
535 [(match_operand:SF 2 "register_operand" "")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
536 (match_operand:SF 3 "csky_compare_operand_float" "")]))]
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
537 "CSKY_ISA_FEATURE (fpv2_sf)"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
538 "
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
539 {
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
540 bool invert = csky_emit_compare_float (GET_CODE (operands[1]),
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
541 operands[2], operands[3]);
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
542 if (invert)
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
543 emit_insn (gen_mvcv (operands[0]));
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
544 else
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
545 emit_insn (gen_mvc (operands[0]));
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
546 DONE;
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
547 }"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
548 )
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
549
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550 ;; cstore DF
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551 (define_expand "cstoredf4"
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552 [(set (match_operand:SI 0 "register_operand" "")
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553 (match_operator 1 "ordered_comparison_operator"
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554 [(match_operand:DF 2 "register_operand" "")
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555 (match_operand:DF 3 "csky_compare_operand_float" "")]))]
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556 "CSKY_ISA_FEATURE (fpv2_df)"
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557 "
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558 {
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559 bool invert = csky_emit_compare_float (GET_CODE (operands[1]),
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560 operands[2], operands[3]);
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561 if (invert)
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562 emit_insn (gen_mvcv (operands[0]));
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563 else
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564 emit_insn (gen_mvc (operands[0]));
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565 DONE;
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566 }"
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567 )