annotate gcc/config/ia64/ia64.opt @ 131:84e7813d76e9

gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
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rev   line source
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84e7813d76e9 gcc-8.2
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1 ; Copyright (C) 2005-2018 Free Software Foundation, Inc.
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2 ;
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3 ; This file is part of GCC.
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4 ;
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5 ; GCC is free software; you can redistribute it and/or modify it under
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6 ; the terms of the GNU General Public License as published by the Free
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7 ; Software Foundation; either version 3, or (at your option) any later
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8 ; version.
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9 ;
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10 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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11 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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12 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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13 ; for more details.
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14 ;
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15 ; You should have received a copy of the GNU General Public License
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16 ; along with GCC; see the file COPYING3. If not see
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17 ; <http://www.gnu.org/licenses/>.
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18
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19 HeaderInclude
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20 config/ia64/ia64-opts.h
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21
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22 ; Which cpu are we scheduling for.
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23 Variable
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24 enum processor_type ia64_tune = PROCESSOR_ITANIUM2
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25
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26 mbig-endian
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27 Target Report RejectNegative Mask(BIG_ENDIAN)
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28 Generate big endian code.
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30 mlittle-endian
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31 Target Report RejectNegative InverseMask(BIG_ENDIAN)
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32 Generate little endian code.
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33
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34 mgnu-as
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35 Target Report Mask(GNU_AS)
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36 Generate code for GNU as.
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37
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38 mgnu-ld
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39 Target Report Mask(GNU_LD)
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40 Generate code for GNU ld.
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41
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42 mvolatile-asm-stop
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43 Target Report Mask(VOL_ASM_STOP)
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44 Emit stop bits before and after volatile extended asms.
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45
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46 mregister-names
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47 Target Mask(REG_NAMES)
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48 Use in/loc/out register names.
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49
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50 mno-sdata
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51 Target Report RejectNegative Mask(NO_SDATA)
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52
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53 msdata
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54 Target Report RejectNegative InverseMask(NO_SDATA)
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55 Enable use of sdata/scommon/sbss.
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56
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57 mno-pic
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58 Target Report RejectNegative Mask(NO_PIC)
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59 Generate code without GP reg.
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61 mconstant-gp
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62 Target Report RejectNegative Mask(CONST_GP)
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63 gp is constant (but save/restore gp on indirect calls).
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65 mauto-pic
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66 Target Report RejectNegative Mask(AUTO_PIC)
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67 Generate self-relocatable code.
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68
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69 minline-float-divide-min-latency
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70 Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 1)
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71 Generate inline floating point division, optimize for latency.
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72
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73 minline-float-divide-max-throughput
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74 Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 2) Init(2)
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75 Generate inline floating point division, optimize for throughput.
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77 mno-inline-float-divide
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78 Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 0)
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79
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80 minline-int-divide-min-latency
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81 Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 1)
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82 Generate inline integer division, optimize for latency.
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83
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84 minline-int-divide-max-throughput
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85 Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 2)
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86 Generate inline integer division, optimize for throughput.
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88 mno-inline-int-divide
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89 Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 0)
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90 Do not inline integer division.
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91
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92 minline-sqrt-min-latency
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93 Target Report RejectNegative Var(TARGET_INLINE_SQRT, 1)
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94 Generate inline square root, optimize for latency.
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96 minline-sqrt-max-throughput
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97 Target Report RejectNegative Var(TARGET_INLINE_SQRT, 2)
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98 Generate inline square root, optimize for throughput.
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100 mno-inline-sqrt
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101 Target Report RejectNegative Var(TARGET_INLINE_SQRT, 0)
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102 Do not inline square root.
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103
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104 mdwarf2-asm
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105 Target Report Mask(DWARF2_ASM)
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106 Enable DWARF line debug info via GNU as.
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107
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108 mearly-stop-bits
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109 Target Report Mask(EARLY_STOP_BITS)
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110 Enable earlier placing stop bits for better scheduling.
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111
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112 mfixed-range=
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113 Target RejectNegative Joined Var(ia64_deferred_options) Defer
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114 Specify range of registers to make fixed.
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115
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116 mtls-size=
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117 Target RejectNegative Joined UInteger Var(ia64_tls_size) Init(22)
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118 Specify bit size of immediate TLS offsets.
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119
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120 mtune=
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121 Target RejectNegative Joined Enum(ia64_tune) Var(ia64_tune)
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122 Schedule code for given CPU.
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123
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124 Enum
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125 Name(ia64_tune) Type(enum processor_type)
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126 Known Itanium CPUs (for use with the -mtune= option):
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127
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128 EnumValue
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129 Enum(ia64_tune) String(itanium2) Value(PROCESSOR_ITANIUM2)
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130
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131 EnumValue
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132 Enum(ia64_tune) String(mckinley) Value(PROCESSOR_ITANIUM2)
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133
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134 msched-br-data-spec
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135 Target Report Var(mflag_sched_br_data_spec) Init(0)
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136 Use data speculation before reload.
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137
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138 msched-ar-data-spec
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139 Target Report Var(mflag_sched_ar_data_spec) Init(1)
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140 Use data speculation after reload.
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141
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142 msched-control-spec
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143 Target Report Var(mflag_sched_control_spec) Init(2)
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144 Use control speculation.
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145
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146 msched-br-in-data-spec
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147 Target Report Var(mflag_sched_br_in_data_spec) Init(1)
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148 Use in block data speculation before reload.
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149
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150 msched-ar-in-data-spec
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151 Target Report Var(mflag_sched_ar_in_data_spec) Init(1)
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152 Use in block data speculation after reload.
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153
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154 msched-in-control-spec
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155 Target Report Var(mflag_sched_in_control_spec) Init(1)
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156 Use in block control speculation.
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157
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158 msched-spec-ldc
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159 Target Report Var(mflag_sched_spec_ldc) Init(1)
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160 Use simple data speculation check.
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161
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162 msched-spec-control-ldc
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163 Target Report Var(mflag_sched_spec_control_ldc) Init(0)
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164 Use simple data speculation check for control speculation.
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165
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166 msched-prefer-non-data-spec-insns
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167 Target Deprecated
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168
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169 msched-prefer-non-control-spec-insns
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170 Target Deprecated
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171
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172 msched-count-spec-in-critical-path
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173 Target Report Var(mflag_sched_count_spec_in_critical_path) Init(0)
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174 Count speculative dependencies while calculating priority of instructions.
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175
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176 msched-stop-bits-after-every-cycle
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177 Target Report Var(mflag_sched_stop_bits_after_every_cycle) Init(1)
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178 Place a stop bit after every cycle when scheduling.
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179
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180 msched-fp-mem-deps-zero-cost
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181 Target Report Var(mflag_sched_fp_mem_deps_zero_cost) Init(0)
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182 Assume that floating-point stores and loads are not likely to cause conflict when placed into one instruction group.
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183
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184 msched-max-memory-insns=
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185 Target RejectNegative Joined UInteger Var(ia64_max_memory_insns) Init(1)
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186 Soft limit on number of memory insns per instruction group, giving lower priority to subsequent memory insns attempting to schedule in the same insn group. Frequently useful to prevent cache bank conflicts. Default value is 1.
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187
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188 msched-max-memory-insns-hard-limit
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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189 Target Report Var(mflag_sched_mem_insns_hard_limit) Init(0)
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190 Disallow more than 'msched-max-memory-insns' in instruction group. Otherwise, limit is 'soft' (prefer non-memory operations when limit is reached).
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191
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192 msel-sched-dont-check-control-spec
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193 Target Report Var(mflag_sel_sched_dont_check_control_spec) Init(0)
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194 Don't generate checks for control speculation in selective scheduling.
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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195
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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196 ; This comment is to ensure we retain the blank line above.