Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/ia64/vect.md @ 131:84e7813d76e9
gcc-8.2
author | mir3636 |
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date | Thu, 25 Oct 2018 07:37:49 +0900 |
parents | 04ced10e8804 |
children | 1830386684a0 |
rev | line source |
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0 | 1 ;; IA-64 machine description for vector operations. |
131 | 2 ;; Copyright (C) 2004-2018 Free Software Foundation, Inc. |
0 | 3 ;; |
4 ;; This file is part of GCC. | |
5 ;; | |
6 ;; GCC is free software; you can redistribute it and/or modify | |
7 ;; it under the terms of the GNU General Public License as published by | |
8 ;; the Free Software Foundation; either version 3, or (at your option) | |
9 ;; any later version. | |
10 ;; | |
11 ;; GCC is distributed in the hope that it will be useful, | |
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 ;; GNU General Public License for more details. | |
15 ;; | |
16 ;; You should have received a copy of the GNU General Public License | |
17 ;; along with GCC; see the file COPYING3. If not see | |
18 ;; <http://www.gnu.org/licenses/>. | |
19 | |
20 | |
21 ;; Integer vector operations | |
22 | |
111 | 23 (define_mode_iterator VEC [V8QI V4HI V2SI V2SF]) |
0 | 24 (define_mode_iterator VECINT [V8QI V4HI V2SI]) |
25 (define_mode_iterator VECINT12 [V8QI V4HI]) | |
26 (define_mode_iterator VECINT24 [V4HI V2SI]) | |
27 (define_mode_attr vecsize [(V8QI "1") (V4HI "2") (V2SI "4")]) | |
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28 (define_mode_attr vecwider [(V8QI "V4HI") (V4HI "V2SI")]) |
111 | 29 (define_mode_attr vecint |
30 [(V8QI "V8QI") (V4HI "V4HI") (V2SI "V2SI") (V2SF "V2SI")]) | |
0 | 31 |
32 (define_expand "mov<mode>" | |
33 [(set (match_operand:VECINT 0 "general_operand" "") | |
34 (match_operand:VECINT 1 "general_operand" ""))] | |
35 "" | |
36 { | |
37 rtx op1 = ia64_expand_move (operands[0], operands[1]); | |
38 if (!op1) | |
39 DONE; | |
40 operands[1] = op1; | |
41 }) | |
42 | |
43 (define_insn "*mov<mode>_internal" | |
44 [(set (match_operand:VECINT 0 "destination_operand" | |
45 "=r,r,r,r,m ,*f ,*f,Q ,r ,*f") | |
46 (match_operand:VECINT 1 "move_operand" | |
47 "rU,W,i,m,rU,U*f,Q ,*f,*f,r "))] | |
48 "ia64_move_ok (operands[0], operands[1])" | |
49 "@ | |
50 mov %0 = %r1 | |
51 addl %0 = %v1, r0 | |
52 movl %0 = %v1 | |
53 ld8%O1 %0 = %1%P1 | |
54 st8%Q0 %0 = %r1%P0 | |
55 mov %0 = %F1 | |
56 ldf8 %0 = %1%P1 | |
57 stf8 %0 = %1%P0 | |
58 getf.sig %0 = %1 | |
59 setf.sig %0 = %1" | |
60 [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,fmisc,fld,stf,frfr,tofr")]) | |
61 | |
62 (define_insn "one_cmpl<mode>2" | |
63 [(set (match_operand:VECINT 0 "gr_register_operand" "=r") | |
64 (not:VECINT (match_operand:VECINT 1 "gr_register_operand" "r")))] | |
65 "" | |
66 "andcm %0 = -1, %1" | |
67 [(set_attr "itanium_class" "ilog")]) | |
68 | |
69 (define_insn "and<mode>3" | |
70 [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f") | |
71 (and:VECINT | |
72 (match_operand:VECINT 1 "grfr_register_operand" "r,*f") | |
73 (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))] | |
74 "" | |
75 "@ | |
76 and %0 = %2, %1 | |
77 fand %0 = %2, %1" | |
78 [(set_attr "itanium_class" "ilog,fmisc")]) | |
79 | |
80 (define_insn "*andnot<mode>" | |
81 [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f") | |
82 (and:VECINT | |
83 (not:VECINT (match_operand:VECINT 1 "grfr_register_operand" "r,*f")) | |
84 (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))] | |
85 "" | |
86 "@ | |
87 andcm %0 = %2, %1 | |
88 fandcm %0 = %2, %1" | |
89 [(set_attr "itanium_class" "ilog,fmisc")]) | |
90 | |
91 (define_insn "ior<mode>3" | |
92 [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f") | |
93 (ior:VECINT | |
94 (match_operand:VECINT 1 "grfr_register_operand" "r,*f") | |
95 (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))] | |
96 "" | |
97 "@ | |
98 or %0 = %2, %1 | |
99 for %0 = %2, %1" | |
100 [(set_attr "itanium_class" "ilog,fmisc")]) | |
101 | |
102 (define_insn "xor<mode>3" | |
103 [(set (match_operand:VECINT 0 "grfr_register_operand" "=r,*f") | |
104 (xor:VECINT | |
105 (match_operand:VECINT 1 "grfr_register_operand" "r,*f") | |
106 (match_operand:VECINT 2 "grfr_reg_or_8bit_operand" "r,*f")))] | |
107 "" | |
108 "@ | |
109 xor %0 = %2, %1 | |
110 fxor %0 = %2, %1" | |
111 [(set_attr "itanium_class" "ilog,fmisc")]) | |
112 | |
113 (define_insn "neg<mode>2" | |
114 [(set (match_operand:VECINT 0 "gr_register_operand" "=r") | |
115 (neg:VECINT (match_operand:VECINT 1 "gr_register_operand" "r")))] | |
116 "" | |
117 "psub<vecsize> %0 = r0, %1" | |
118 [(set_attr "itanium_class" "mmalua")]) | |
119 | |
120 (define_insn "add<mode>3" | |
121 [(set (match_operand:VECINT 0 "gr_register_operand" "=r") | |
122 (plus:VECINT (match_operand:VECINT 1 "gr_register_operand" "r") | |
123 (match_operand:VECINT 2 "gr_register_operand" "r")))] | |
124 "" | |
125 "padd<vecsize> %0 = %1, %2" | |
126 [(set_attr "itanium_class" "mmalua")]) | |
127 | |
128 (define_insn "*ssadd<mode>3" | |
129 [(set (match_operand:VECINT12 0 "gr_register_operand" "=r") | |
130 (ss_plus:VECINT12 | |
131 (match_operand:VECINT12 1 "gr_register_operand" "r") | |
132 (match_operand:VECINT12 2 "gr_register_operand" "r")))] | |
133 "" | |
134 "padd<vecsize>.sss %0 = %1, %2" | |
135 [(set_attr "itanium_class" "mmalua")]) | |
136 | |
137 (define_insn "*usadd<mode>3" | |
138 [(set (match_operand:VECINT12 0 "gr_register_operand" "=r") | |
139 (us_plus:VECINT12 | |
140 (match_operand:VECINT12 1 "gr_register_operand" "r") | |
141 (match_operand:VECINT12 2 "gr_register_operand" "r")))] | |
142 "" | |
143 "padd<vecsize>.uuu %0 = %1, %2" | |
144 [(set_attr "itanium_class" "mmalua")]) | |
145 | |
146 (define_insn "sub<mode>3" | |
147 [(set (match_operand:VECINT 0 "gr_register_operand" "=r") | |
148 (minus:VECINT (match_operand:VECINT 1 "gr_register_operand" "r") | |
149 (match_operand:VECINT 2 "gr_register_operand" "r")))] | |
150 "" | |
151 "psub<vecsize> %0 = %1, %2" | |
152 [(set_attr "itanium_class" "mmalua")]) | |
153 | |
154 (define_insn "*sssub<mode>3" | |
155 [(set (match_operand:VECINT12 0 "gr_register_operand" "=r") | |
156 (ss_minus:VECINT12 | |
157 (match_operand:VECINT12 1 "gr_register_operand" "r") | |
158 (match_operand:VECINT12 2 "gr_register_operand" "r")))] | |
159 "" | |
160 "psub<vecsize>.sss %0 = %1, %2" | |
161 [(set_attr "itanium_class" "mmalua")]) | |
162 | |
163 (define_insn "*ussub<mode>3" | |
164 [(set (match_operand:VECINT12 0 "gr_register_operand" "=r") | |
165 (us_minus:VECINT12 | |
166 (match_operand:VECINT12 1 "gr_register_operand" "r") | |
167 (match_operand:VECINT12 2 "gr_register_operand" "r")))] | |
168 "" | |
169 "psub<vecsize>.uuu %0 = %1, %2" | |
170 [(set_attr "itanium_class" "mmalua")]) | |
171 | |
172 (define_expand "mulv8qi3" | |
173 [(set (match_operand:V8QI 0 "gr_register_operand" "") | |
174 (mult:V8QI (match_operand:V8QI 1 "gr_register_operand" "r") | |
175 (match_operand:V8QI 2 "gr_register_operand" "r")))] | |
176 "" | |
177 { | |
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178 rtx l = gen_reg_rtx (V4HImode); |
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179 rtx h = gen_reg_rtx (V4HImode); |
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180 emit_insn (gen_vec_widen_umult_lo_v8qi (l, operands[1], operands[2])); |
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181 emit_insn (gen_vec_widen_umult_hi_v8qi (h, operands[1], operands[2])); |
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182 if (TARGET_BIG_ENDIAN) |
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183 emit_insn (gen_vec_pack_trunc_v4hi (operands[0], h, l)); |
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184 else |
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185 emit_insn (gen_vec_pack_trunc_v4hi (operands[0], l, h)); |
0 | 186 DONE; |
187 }) | |
188 | |
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189 (define_expand "vec_widen_umult_lo_v8qi" |
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190 [(match_operand:V4HI 0 "gr_register_operand" "") |
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191 (match_operand:V8QI 1 "gr_register_operand" "") |
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192 (match_operand:V8QI 2 "gr_register_operand" "")] |
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193 "" |
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194 { |
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195 rtx op1 = gen_reg_rtx (V4HImode); |
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196 rtx op2 = gen_reg_rtx (V4HImode); |
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197 emit_insn (gen_vec_unpacku_lo_v8qi (op1, operands[1])); |
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198 emit_insn (gen_vec_unpacku_lo_v8qi (op2, operands[2])); |
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199 emit_insn (gen_mulv4hi3 (operands[0], op1, op2)); |
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200 DONE; |
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201 }); |
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202 |
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203 (define_expand "vec_widen_umult_hi_v8qi" |
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204 [(match_operand:V4HI 0 "gr_register_operand" "") |
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205 (match_operand:V8QI 1 "gr_register_operand" "") |
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206 (match_operand:V8QI 2 "gr_register_operand" "")] |
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207 "" |
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208 { |
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209 rtx op1 = gen_reg_rtx (V4HImode); |
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210 rtx op2 = gen_reg_rtx (V4HImode); |
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211 emit_insn (gen_vec_unpacku_hi_v8qi (op1, operands[1])); |
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212 emit_insn (gen_vec_unpacku_hi_v8qi (op2, operands[2])); |
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213 emit_insn (gen_mulv4hi3 (operands[0], op1, op2)); |
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214 DONE; |
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215 }); |
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216 |
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217 (define_expand "vec_widen_smult_lo_v8qi" |
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218 [(match_operand:V4HI 0 "gr_register_operand" "") |
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219 (match_operand:V8QI 1 "gr_register_operand" "") |
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220 (match_operand:V8QI 2 "gr_register_operand" "")] |
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221 "" |
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222 { |
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223 rtx op1 = gen_reg_rtx (V4HImode); |
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224 rtx op2 = gen_reg_rtx (V4HImode); |
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225 emit_insn (gen_vec_unpacks_lo_v8qi (op1, operands[1])); |
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226 emit_insn (gen_vec_unpacks_lo_v8qi (op2, operands[2])); |
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227 emit_insn (gen_mulv4hi3 (operands[0], op1, op2)); |
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228 DONE; |
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229 }); |
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230 |
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231 (define_expand "vec_widen_smult_hi_v8qi" |
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232 [(match_operand:V4HI 0 "gr_register_operand" "") |
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233 (match_operand:V8QI 1 "gr_register_operand" "") |
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234 (match_operand:V8QI 2 "gr_register_operand" "")] |
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235 "" |
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236 { |
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237 rtx op1 = gen_reg_rtx (V4HImode); |
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238 rtx op2 = gen_reg_rtx (V4HImode); |
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239 emit_insn (gen_vec_unpacks_hi_v8qi (op1, operands[1])); |
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240 emit_insn (gen_vec_unpacks_hi_v8qi (op2, operands[2])); |
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241 emit_insn (gen_mulv4hi3 (operands[0], op1, op2)); |
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242 DONE; |
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243 }); |
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244 |
0 | 245 (define_insn "mulv4hi3" |
246 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") | |
247 (mult:V4HI (match_operand:V4HI 1 "gr_register_operand" "r") | |
248 (match_operand:V4HI 2 "gr_register_operand" "r")))] | |
249 "" | |
250 "pmpyshr2 %0 = %1, %2, 0" | |
251 [(set_attr "itanium_class" "mmmul")]) | |
252 | |
67
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253 (define_insn "pmpyshr2" |
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254 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") |
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255 (truncate:V4HI |
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256 (ashiftrt:V4SI |
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257 (mult:V4SI |
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258 (sign_extend:V4SI |
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259 (match_operand:V4HI 1 "gr_register_operand" "r")) |
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260 (sign_extend:V4SI |
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261 (match_operand:V4HI 2 "gr_register_operand" "r"))) |
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262 (match_operand:SI 3 "pmpyshr_operand" "n"))))] |
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263 "" |
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264 "pmpyshr2 %0 = %1, %2, %3" |
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265 [(set_attr "itanium_class" "mmmul")]) |
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266 |
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267 (define_insn "pmpyshr2_u" |
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268 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") |
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269 (truncate:V4HI |
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270 (lshiftrt:V4SI |
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271 (mult:V4SI |
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272 (zero_extend:V4SI |
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273 (match_operand:V4HI 1 "gr_register_operand" "r")) |
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274 (zero_extend:V4SI |
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275 (match_operand:V4HI 2 "gr_register_operand" "r"))) |
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276 (match_operand:SI 3 "pmpyshr_operand" "n"))))] |
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277 "" |
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278 "pmpyshr2.u %0 = %1, %2, %3" |
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279 [(set_attr "itanium_class" "mmmul")]) |
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280 |
111 | 281 (define_expand "smulv4hi3_highpart" |
282 [(match_operand:V4HI 0 "gr_register_operand") | |
283 (match_operand:V4HI 1 "gr_register_operand") | |
284 (match_operand:V4HI 2 "gr_register_operand")] | |
285 "" | |
286 { | |
287 emit_insn (gen_pmpyshr2 (operands[0], operands[1], | |
288 operands[2], GEN_INT (16))); | |
289 DONE; | |
290 }) | |
291 | |
292 (define_expand "umulv4hi3_highpart" | |
293 [(match_operand:V4HI 0 "gr_register_operand") | |
294 (match_operand:V4HI 1 "gr_register_operand") | |
295 (match_operand:V4HI 2 "gr_register_operand")] | |
296 "" | |
297 { | |
298 emit_insn (gen_pmpyshr2_u (operands[0], operands[1], | |
299 operands[2], GEN_INT (16))); | |
300 DONE; | |
301 }) | |
302 | |
303 (define_insn "vec_widen_smult_even_v4hi" | |
0 | 304 [(set (match_operand:V2SI 0 "gr_register_operand" "=r") |
305 (mult:V2SI | |
306 (vec_select:V2SI | |
307 (sign_extend:V4SI | |
308 (match_operand:V4HI 1 "gr_register_operand" "r")) | |
309 (parallel [(const_int 0) (const_int 2)])) | |
310 (vec_select:V2SI | |
311 (sign_extend:V4SI | |
312 (match_operand:V4HI 2 "gr_register_operand" "r")) | |
313 (parallel [(const_int 0) (const_int 2)]))))] | |
314 "" | |
67
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315 { |
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316 /* Recall that vector elements are numbered in memory order. */ |
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317 if (TARGET_BIG_ENDIAN) |
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318 return "%,pmpy2.l %0 = %1, %2"; |
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319 else |
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320 return "%,pmpy2.r %0 = %1, %2"; |
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321 } |
0 | 322 [(set_attr "itanium_class" "mmshf")]) |
323 | |
111 | 324 (define_insn "vec_widen_smult_odd_v4hi" |
0 | 325 [(set (match_operand:V2SI 0 "gr_register_operand" "=r") |
326 (mult:V2SI | |
327 (vec_select:V2SI | |
328 (sign_extend:V4SI | |
329 (match_operand:V4HI 1 "gr_register_operand" "r")) | |
330 (parallel [(const_int 1) (const_int 3)])) | |
331 (vec_select:V2SI | |
332 (sign_extend:V4SI | |
333 (match_operand:V4HI 2 "gr_register_operand" "r")) | |
334 (parallel [(const_int 1) (const_int 3)]))))] | |
335 "" | |
67
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336 { |
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337 /* Recall that vector elements are numbered in memory order. */ |
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338 if (TARGET_BIG_ENDIAN) |
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339 return "%,pmpy2.r %0 = %1, %2"; |
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340 else |
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341 return "%,pmpy2.l %0 = %1, %2"; |
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342 } |
0 | 343 [(set_attr "itanium_class" "mmshf")]) |
344 | |
67
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345 (define_expand "vec_widen_smult_lo_v4hi" |
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346 [(match_operand:V2SI 0 "gr_register_operand" "") |
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347 (match_operand:V4HI 1 "gr_register_operand" "") |
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348 (match_operand:V4HI 2 "gr_register_operand" "")] |
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349 "" |
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350 { |
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351 rtx l = gen_reg_rtx (V4HImode); |
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352 rtx h = gen_reg_rtx (V4HImode); |
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353 emit_insn (gen_mulv4hi3 (l, operands[1], operands[2])); |
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354 emit_insn (gen_pmpyshr2 (h, operands[1], operands[2], GEN_INT (16))); |
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355 ia64_unpack_assemble (operands[0], l, h, false); |
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356 DONE; |
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357 }) |
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358 |
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359 (define_expand "vec_widen_smult_hi_v4hi" |
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360 [(match_operand:V2SI 0 "gr_register_operand" "") |
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361 (match_operand:V4HI 1 "gr_register_operand" "") |
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362 (match_operand:V4HI 2 "gr_register_operand" "")] |
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363 "" |
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364 { |
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365 rtx l = gen_reg_rtx (V4HImode); |
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366 rtx h = gen_reg_rtx (V4HImode); |
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367 emit_insn (gen_mulv4hi3 (l, operands[1], operands[2])); |
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368 emit_insn (gen_pmpyshr2 (h, operands[1], operands[2], GEN_INT (16))); |
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369 ia64_unpack_assemble (operands[0], l, h, true); |
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370 DONE; |
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371 }) |
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372 |
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373 (define_expand "vec_widen_umult_lo_v4hi" |
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374 [(match_operand:V2SI 0 "gr_register_operand" "") |
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375 (match_operand:V4HI 1 "gr_register_operand" "") |
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376 (match_operand:V4HI 2 "gr_register_operand" "")] |
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377 "" |
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378 { |
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379 rtx l = gen_reg_rtx (V4HImode); |
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380 rtx h = gen_reg_rtx (V4HImode); |
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381 emit_insn (gen_mulv4hi3 (l, operands[1], operands[2])); |
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382 emit_insn (gen_pmpyshr2_u (h, operands[1], operands[2], GEN_INT (16))); |
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383 ia64_unpack_assemble (operands[0], l, h, false); |
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384 DONE; |
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385 }) |
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386 |
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387 (define_expand "vec_widen_umult_hi_v4hi" |
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388 [(match_operand:V2SI 0 "gr_register_operand" "") |
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389 (match_operand:V4HI 1 "gr_register_operand" "") |
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390 (match_operand:V4HI 2 "gr_register_operand" "")] |
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391 "" |
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392 { |
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393 rtx l = gen_reg_rtx (V4HImode); |
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394 rtx h = gen_reg_rtx (V4HImode); |
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395 emit_insn (gen_mulv4hi3 (l, operands[1], operands[2])); |
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396 emit_insn (gen_pmpyshr2_u (h, operands[1], operands[2], GEN_INT (16))); |
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397 ia64_unpack_assemble (operands[0], l, h, true); |
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398 DONE; |
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399 }) |
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400 |
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401 (define_expand "mulv2si3" |
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402 [(set (match_operand:V2SI 0 "gr_register_operand" "") |
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403 (mult:V2SI (match_operand:V2SI 1 "gr_register_operand" "r") |
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404 (match_operand:V2SI 2 "gr_register_operand" "r")))] |
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405 "" |
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406 { |
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407 rtx t0, t1, t2, t3, t4, t5, t6, t7, x; |
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408 rtx op1h = gen_lowpart (V4HImode, operands[1]); |
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409 rtx op2h = gen_lowpart (V4HImode, operands[2]); |
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410 |
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411 t0 = gen_reg_rtx (V4HImode); |
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412 t1 = gen_reg_rtx (V4HImode); |
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413 t2 = gen_reg_rtx (V4HImode); |
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414 t3 = gen_reg_rtx (V4HImode); |
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415 t4 = gen_reg_rtx (V2SImode); |
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416 t5 = gen_reg_rtx (V2SImode); |
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417 t6 = gen_reg_rtx (V2SImode); |
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418 t7 = gen_reg_rtx (V2SImode); |
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419 |
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420 /* Consider the HImode components of op1 = DCBA, op2 = ZYXW. |
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421 Consider .l and .h suffixes below the low and high 16 bits |
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422 of the full 32-bit product. */ |
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423 |
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424 /* T0 = CDBA. */ |
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425 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4, const1_rtx, const0_rtx, |
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426 GEN_INT (3), const2_rtx)); |
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427 x = gen_rtx_VEC_SELECT (V4HImode, op1h, x); |
111 | 428 emit_insn (gen_rtx_SET (t0, x)); |
67
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429 |
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430 /* T1 = DZ.l, CY.l, BX.l, AW.l. */ |
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431 emit_insn (gen_mulv4hi3 (t1, op1h, op2h)); |
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432 |
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433 /* T2 = DZ.h, CY.h, BX.h, AW.h. */ |
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434 emit_insn (gen_pmpyshr2_u (t2, op1h, op2h, GEN_INT (16))); |
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435 |
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436 /* T3 = CZ.l, DY.l, AX.l, BW.l. */ |
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437 emit_insn (gen_mulv4hi3 (t3, t0, op2h)); |
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438 |
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439 /* T4 = CY.h, CY.l, AW.h, AW.l = CY, AW. */ |
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440 x = gen_lowpart (V4HImode, t4); |
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441 if (TARGET_BIG_ENDIAN) |
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442 x = gen_mix2_odd (x, t2, t1); |
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443 else |
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444 x = gen_mix2_even (x, t1, t2); |
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445 emit_insn (x); |
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446 |
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447 /* T5 = CZ.l, 0, AX.l, 0 = CZ << 16, AX << 16. */ |
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448 x = gen_lowpart (V4HImode, t5); |
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449 if (TARGET_BIG_ENDIAN) |
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450 x = gen_mix2_even (x, t3, CONST0_RTX (V4HImode)); |
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451 else |
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452 x = gen_mix2_odd (x, CONST0_RTX (V4HImode), t3); |
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453 emit_insn (x); |
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454 |
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455 /* T6 = DY.l, 0, BW.l, 0 = DY << 16, BW << 16. */ |
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456 x = gen_lowpart (V4HImode, t6); |
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457 if (TARGET_BIG_ENDIAN) |
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458 x = gen_mix2_odd (x, t3, CONST0_RTX (V4HImode)); |
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459 else |
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460 x = gen_mix2_even (x, CONST0_RTX (V4HImode), t3); |
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461 emit_insn (x); |
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462 |
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463 emit_insn (gen_addv2si3 (t7, t4, t5)); |
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464 emit_insn (gen_addv2si3 (operands[0], t6, t7)); |
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465 DONE; |
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466 }) |
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467 |
0 | 468 (define_expand "umax<mode>3" |
469 [(set (match_operand:VECINT 0 "gr_register_operand" "") | |
470 (umax:VECINT (match_operand:VECINT 1 "gr_register_operand" "") | |
471 (match_operand:VECINT 2 "gr_register_operand" "")))] | |
472 "" | |
473 { | |
474 if (ia64_expand_vecint_minmax (UMAX, <MODE>mode, operands)) | |
475 DONE; | |
476 }) | |
477 | |
478 (define_expand "smax<mode>3" | |
479 [(set (match_operand:VECINT 0 "gr_register_operand" "") | |
480 (smax:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "") | |
481 (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))] | |
482 "" | |
483 { | |
484 if (ia64_expand_vecint_minmax (SMAX, <MODE>mode, operands)) | |
485 DONE; | |
486 }) | |
487 | |
488 (define_expand "umin<mode>3" | |
489 [(set (match_operand:VECINT 0 "gr_register_operand" "") | |
490 (umin:VECINT (match_operand:VECINT 1 "gr_register_operand" "") | |
491 (match_operand:VECINT 2 "gr_register_operand" "")))] | |
492 "" | |
493 { | |
494 if (ia64_expand_vecint_minmax (UMIN, <MODE>mode, operands)) | |
495 DONE; | |
496 }) | |
497 | |
498 (define_expand "smin<mode>3" | |
499 [(set (match_operand:VECINT 0 "gr_register_operand" "") | |
500 (smin:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "") | |
501 (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))] | |
502 "" | |
503 { | |
504 if (ia64_expand_vecint_minmax (SMIN, <MODE>mode, operands)) | |
505 DONE; | |
506 }) | |
507 | |
508 (define_insn "*umaxv8qi3" | |
509 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") | |
510 (umax:V8QI (match_operand:V8QI 1 "gr_register_operand" "r") | |
511 (match_operand:V8QI 2 "gr_register_operand" "r")))] | |
512 "" | |
513 "pmax1.u %0 = %1, %2" | |
514 [(set_attr "itanium_class" "mmshf")]) | |
515 | |
516 (define_insn "*smaxv4hi3" | |
517 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") | |
518 (smax:V4HI (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") | |
519 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")))] | |
520 "" | |
521 "pmax2 %0 = %r1, %r2" | |
522 [(set_attr "itanium_class" "mmshf")]) | |
523 | |
524 (define_insn "*uminv8qi3" | |
525 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") | |
526 (umin:V8QI (match_operand:V8QI 1 "gr_register_operand" "r") | |
527 (match_operand:V8QI 2 "gr_register_operand" "r")))] | |
528 "" | |
529 "pmin1.u %0 = %1, %2" | |
530 [(set_attr "itanium_class" "mmshf")]) | |
531 | |
532 (define_insn "*sminv4hi3" | |
533 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") | |
534 (smin:V4HI (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") | |
535 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")))] | |
536 "" | |
537 "pmin2 %0 = %r1, %r2" | |
538 [(set_attr "itanium_class" "mmshf")]) | |
539 | |
540 (define_insn "ashl<mode>3" | |
541 [(set (match_operand:VECINT24 0 "gr_register_operand" "=r") | |
542 (ashift:VECINT24 | |
543 (match_operand:VECINT24 1 "gr_register_operand" "r") | |
544 (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))] | |
545 "" | |
546 "pshl<vecsize> %0 = %1, %2" | |
547 [(set_attr "itanium_class" "mmshf")]) | |
548 | |
549 (define_insn "ashr<mode>3" | |
550 [(set (match_operand:VECINT24 0 "gr_register_operand" "=r") | |
551 (ashiftrt:VECINT24 | |
552 (match_operand:VECINT24 1 "gr_register_operand" "r") | |
553 (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))] | |
554 "" | |
555 "pshr<vecsize> %0 = %1, %2" | |
556 [(set_attr "itanium_class" "mmshf")]) | |
557 | |
558 (define_insn "lshr<mode>3" | |
559 [(set (match_operand:VECINT24 0 "gr_register_operand" "=r") | |
560 (lshiftrt:VECINT24 | |
561 (match_operand:VECINT24 1 "gr_register_operand" "r") | |
562 (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))] | |
563 "" | |
564 "pshr<vecsize>.u %0 = %1, %2" | |
565 [(set_attr "itanium_class" "mmshf")]) | |
566 | |
567 (define_expand "vec_shl_<mode>" | |
568 [(set (match_operand:VECINT 0 "gr_register_operand" "") | |
569 (ashift:DI (match_operand:VECINT 1 "gr_register_operand" "") | |
570 (match_operand:DI 2 "gr_reg_or_6bit_operand" "")))] | |
571 "" | |
572 { | |
573 operands[0] = gen_lowpart (DImode, operands[0]); | |
574 operands[1] = gen_lowpart (DImode, operands[1]); | |
575 }) | |
576 | |
577 (define_expand "vec_shr_<mode>" | |
578 [(set (match_operand:VECINT 0 "gr_register_operand" "") | |
579 (lshiftrt:DI (match_operand:VECINT 1 "gr_register_operand" "") | |
580 (match_operand:DI 2 "gr_reg_or_6bit_operand" "")))] | |
581 "" | |
582 { | |
583 operands[0] = gen_lowpart (DImode, operands[0]); | |
584 operands[1] = gen_lowpart (DImode, operands[1]); | |
585 }) | |
586 | |
587 (define_expand "widen_usumv8qi3" | |
588 [(match_operand:V4HI 0 "gr_register_operand" "") | |
589 (match_operand:V8QI 1 "gr_register_operand" "") | |
590 (match_operand:V4HI 2 "gr_register_operand" "")] | |
591 "" | |
592 { | |
593 ia64_expand_widen_sum (operands, true); | |
594 DONE; | |
595 }) | |
596 | |
597 (define_expand "widen_usumv4hi3" | |
598 [(match_operand:V2SI 0 "gr_register_operand" "") | |
599 (match_operand:V4HI 1 "gr_register_operand" "") | |
600 (match_operand:V2SI 2 "gr_register_operand" "")] | |
601 "" | |
602 { | |
603 ia64_expand_widen_sum (operands, true); | |
604 DONE; | |
605 }) | |
606 | |
607 (define_expand "widen_ssumv8qi3" | |
608 [(match_operand:V4HI 0 "gr_register_operand" "") | |
609 (match_operand:V8QI 1 "gr_register_operand" "") | |
610 (match_operand:V4HI 2 "gr_register_operand" "")] | |
611 "" | |
612 { | |
613 ia64_expand_widen_sum (operands, false); | |
614 DONE; | |
615 }) | |
616 | |
617 (define_expand "widen_ssumv4hi3" | |
618 [(match_operand:V2SI 0 "gr_register_operand" "") | |
619 (match_operand:V4HI 1 "gr_register_operand" "") | |
620 (match_operand:V2SI 2 "gr_register_operand" "")] | |
621 "" | |
622 { | |
623 ia64_expand_widen_sum (operands, false); | |
624 DONE; | |
625 }) | |
626 | |
111 | 627 (define_expand "vcond<mode><mode>" |
0 | 628 [(set (match_operand:VECINT 0 "gr_register_operand" "") |
629 (if_then_else:VECINT | |
630 (match_operator 3 "" | |
631 [(match_operand:VECINT 4 "gr_reg_or_0_operand" "") | |
632 (match_operand:VECINT 5 "gr_reg_or_0_operand" "")]) | |
633 (match_operand:VECINT 1 "gr_reg_or_0_operand" "") | |
634 (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))] | |
635 "" | |
636 { | |
637 ia64_expand_vecint_cmov (operands); | |
638 DONE; | |
639 }) | |
640 | |
111 | 641 (define_expand "vcondu<mode><mode>" |
0 | 642 [(set (match_operand:VECINT 0 "gr_register_operand" "") |
643 (if_then_else:VECINT | |
644 (match_operator 3 "" | |
645 [(match_operand:VECINT 4 "gr_reg_or_0_operand" "") | |
646 (match_operand:VECINT 5 "gr_reg_or_0_operand" "")]) | |
647 (match_operand:VECINT 1 "gr_reg_or_0_operand" "") | |
648 (match_operand:VECINT 2 "gr_reg_or_0_operand" "")))] | |
649 "" | |
650 { | |
651 ia64_expand_vecint_cmov (operands); | |
652 DONE; | |
653 }) | |
654 | |
655 (define_insn "*cmpeq_<mode>" | |
656 [(set (match_operand:VECINT 0 "gr_register_operand" "=r") | |
657 (eq:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "rU") | |
658 (match_operand:VECINT 2 "gr_reg_or_0_operand" "rU")))] | |
659 "" | |
660 "pcmp<vecsize>.eq %0 = %r1, %r2" | |
661 [(set_attr "itanium_class" "mmalua")]) | |
662 | |
663 (define_insn "*cmpgt_<mode>" | |
664 [(set (match_operand:VECINT 0 "gr_register_operand" "=r") | |
665 (gt:VECINT (match_operand:VECINT 1 "gr_reg_or_0_operand" "rU") | |
666 (match_operand:VECINT 2 "gr_reg_or_0_operand" "rU")))] | |
667 "" | |
668 "pcmp<vecsize>.gt %0 = %r1, %r2" | |
669 [(set_attr "itanium_class" "mmalua")]) | |
670 | |
67
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671 (define_insn "vec_pack_ssat_v4hi" |
0 | 672 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") |
673 (vec_concat:V8QI | |
674 (ss_truncate:V4QI | |
675 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")) | |
676 (ss_truncate:V4QI | |
677 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))))] | |
678 "" | |
67
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679 { |
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680 /* Recall that vector elements are numbered in memory order. */ |
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681 if (TARGET_BIG_ENDIAN) |
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682 return "%,pack2.sss %0 = %r2, %r1"; |
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683 else |
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684 return "%,pack2.sss %0 = %r1, %r2"; |
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685 } |
0 | 686 [(set_attr "itanium_class" "mmshf")]) |
687 | |
67
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688 (define_insn "vec_pack_usat_v4hi" |
0 | 689 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") |
690 (vec_concat:V8QI | |
691 (us_truncate:V4QI | |
692 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU")) | |
693 (us_truncate:V4QI | |
694 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU"))))] | |
695 "" | |
67
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696 { |
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697 /* Recall that vector elements are numbered in memory order. */ |
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698 if (TARGET_BIG_ENDIAN) |
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699 return "%,pack2.uss %0 = %r2, %r1"; |
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700 else |
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701 return "%,pack2.uss %0 = %r1, %r2"; |
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702 } |
0 | 703 [(set_attr "itanium_class" "mmshf")]) |
704 | |
67
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705 (define_insn "vec_pack_ssat_v2si" |
0 | 706 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") |
707 (vec_concat:V4HI | |
708 (ss_truncate:V2HI | |
709 (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU")) | |
710 (ss_truncate:V2HI | |
711 (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU"))))] | |
712 "" | |
67
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713 { |
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714 /* Recall that vector elements are numbered in memory order. */ |
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715 if (TARGET_BIG_ENDIAN) |
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716 return "%,pack4.sss %0 = %r2, %r1"; |
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717 else |
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718 return "%,pack4.sss %0 = %r1, %r2"; |
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719 } |
0 | 720 [(set_attr "itanium_class" "mmshf")]) |
721 | |
111 | 722 (define_insn "*vec_interleave_lowv8qi" |
0 | 723 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") |
724 (vec_select:V8QI | |
725 (vec_concat:V16QI | |
726 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU") | |
727 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU")) | |
67
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728 (parallel [(const_int 0) (const_int 8) |
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729 (const_int 1) (const_int 9) |
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730 (const_int 2) (const_int 10) |
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731 (const_int 3) (const_int 11)])))] |
0 | 732 "" |
67
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733 { |
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734 /* Recall that vector elements are numbered in memory order. */ |
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735 if (TARGET_BIG_ENDIAN) |
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736 return "%,unpack1.l %0 = %r1, %r2"; |
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737 else |
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|
738 return "%,unpack1.l %0 = %r2, %r1"; |
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diff
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|
739 } |
0 | 740 [(set_attr "itanium_class" "mmshf")]) |
741 | |
111 | 742 (define_insn "*vec_interleave_highv8qi" |
0 | 743 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") |
744 (vec_select:V8QI | |
745 (vec_concat:V16QI | |
746 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU") | |
747 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU")) | |
67
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diff
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|
748 (parallel [(const_int 4) (const_int 12) |
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|
749 (const_int 5) (const_int 13) |
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|
750 (const_int 6) (const_int 14) |
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|
751 (const_int 7) (const_int 15)])))] |
0 | 752 "" |
67
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|
753 { |
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|
754 /* Recall that vector elements are numbered in memory order. */ |
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|
755 if (TARGET_BIG_ENDIAN) |
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|
756 return "%,unpack1.h %0 = %r1, %r2"; |
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|
757 else |
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|
758 return "%,unpack1.h %0 = %r2, %r1"; |
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|
759 } |
0 | 760 [(set_attr "itanium_class" "mmshf")]) |
761 | |
111 | 762 (define_insn "*mix1_even" |
0 | 763 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") |
764 (vec_select:V8QI | |
765 (vec_concat:V16QI | |
766 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU") | |
767 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU")) | |
67
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|
768 (parallel [(const_int 0) (const_int 8) |
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|
769 (const_int 2) (const_int 10) |
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|
770 (const_int 4) (const_int 12) |
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|
771 (const_int 6) (const_int 14)])))] |
0 | 772 "" |
67
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|
773 { |
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|
774 /* Recall that vector elements are numbered in memory order. */ |
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|
775 if (TARGET_BIG_ENDIAN) |
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|
776 return "%,mix1.l %0 = %r1, %r2"; |
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|
777 else |
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|
778 return "%,mix1.r %0 = %r2, %r1"; |
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diff
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|
779 } |
0 | 780 [(set_attr "itanium_class" "mmshf")]) |
781 | |
111 | 782 (define_insn "*mix1_odd" |
0 | 783 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") |
784 (vec_select:V8QI | |
785 (vec_concat:V16QI | |
786 (match_operand:V8QI 1 "gr_reg_or_0_operand" "rU") | |
787 (match_operand:V8QI 2 "gr_reg_or_0_operand" "rU")) | |
67
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|
788 (parallel [(const_int 1) (const_int 9) |
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|
789 (const_int 3) (const_int 11) |
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|
790 (const_int 5) (const_int 13) |
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|
791 (const_int 7) (const_int 15)])))] |
0 | 792 "" |
67
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|
793 { |
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|
794 /* Recall that vector elements are numbered in memory order. */ |
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|
795 if (TARGET_BIG_ENDIAN) |
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|
796 return "%,mix1.r %0 = %r1, %r2"; |
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|
797 else |
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|
798 return "%,mix1.l %0 = %r2, %r1"; |
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|
799 } |
0 | 800 [(set_attr "itanium_class" "mmshf")]) |
801 | |
802 (define_insn "*mux1_rev" | |
803 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") | |
804 (vec_select:V8QI | |
805 (match_operand:V8QI 1 "gr_register_operand" "r") | |
67
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|
806 (parallel [(const_int 7) (const_int 6) |
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|
807 (const_int 5) (const_int 4) |
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|
808 (const_int 3) (const_int 2) |
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|
809 (const_int 1) (const_int 0)])))] |
0 | 810 "" |
811 "mux1 %0 = %1, @rev" | |
812 [(set_attr "itanium_class" "mmshf")]) | |
813 | |
814 (define_insn "*mux1_mix" | |
815 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") | |
816 (vec_select:V8QI | |
817 (match_operand:V8QI 1 "gr_register_operand" "r") | |
67
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|
818 (parallel [(const_int 0) (const_int 4) |
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|
819 (const_int 2) (const_int 6) |
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|
820 (const_int 1) (const_int 5) |
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|
821 (const_int 3) (const_int 7)])))] |
0 | 822 "" |
823 "mux1 %0 = %1, @mix" | |
824 [(set_attr "itanium_class" "mmshf")]) | |
825 | |
826 (define_insn "*mux1_shuf" | |
827 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") | |
828 (vec_select:V8QI | |
829 (match_operand:V8QI 1 "gr_register_operand" "r") | |
67
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diff
changeset
|
830 (parallel [(const_int 0) (const_int 4) |
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|
831 (const_int 1) (const_int 5) |
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|
832 (const_int 2) (const_int 6) |
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|
833 (const_int 3) (const_int 7)])))] |
0 | 834 "" |
835 "mux1 %0 = %1, @shuf" | |
836 [(set_attr "itanium_class" "mmshf")]) | |
837 | |
111 | 838 (define_insn "*mux1_alt" |
0 | 839 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") |
840 (vec_select:V8QI | |
841 (match_operand:V8QI 1 "gr_register_operand" "r") | |
67
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changeset
|
842 (parallel [(const_int 0) (const_int 2) |
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|
843 (const_int 4) (const_int 6) |
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|
844 (const_int 1) (const_int 3) |
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|
845 (const_int 5) (const_int 7)])))] |
0 | 846 "" |
847 "mux1 %0 = %1, @alt" | |
848 [(set_attr "itanium_class" "mmshf")]) | |
849 | |
850 (define_insn "*mux1_brcst_v8qi" | |
851 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") | |
852 (vec_select:V8QI | |
853 (match_operand:V8QI 1 "gr_register_operand" "r") | |
67
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diff
changeset
|
854 (parallel [(match_operand 2 "mux1_brcst_element" "") |
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|
855 (match_dup 2) |
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|
856 (match_dup 2) |
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|
857 (match_dup 2) |
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|
858 (match_dup 2) |
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|
859 (match_dup 2) |
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|
860 (match_dup 2) |
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diff
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|
861 (match_dup 2)])))] |
0 | 862 "" |
863 "mux1 %0 = %1, @brcst" | |
864 [(set_attr "itanium_class" "mmshf")]) | |
865 | |
111 | 866 (define_insn "mux1_brcst_qi" |
0 | 867 [(set (match_operand:V8QI 0 "gr_register_operand" "=r") |
868 (vec_duplicate:V8QI | |
869 (match_operand:QI 1 "gr_register_operand" "r")))] | |
870 "" | |
871 "mux1 %0 = %1, @brcst" | |
872 [(set_attr "itanium_class" "mmshf")]) | |
873 | |
111 | 874 (define_insn "*vec_interleave_lowv4hi" |
0 | 875 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") |
876 (vec_select:V4HI | |
877 (vec_concat:V8HI | |
878 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") | |
879 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")) | |
67
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diff
changeset
|
880 (parallel [(const_int 0) (const_int 4) |
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|
881 (const_int 1) (const_int 5)])))] |
0 | 882 "" |
67
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diff
changeset
|
883 { |
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|
884 /* Recall that vector elements are numbered in memory order. */ |
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|
885 if (TARGET_BIG_ENDIAN) |
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|
886 return "%,unpack2.l %0 = %r1, %r2"; |
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|
887 else |
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changeset
|
888 return "%,unpack2.l %0 = %r2, %r1"; |
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changeset
|
889 } |
0 | 890 [(set_attr "itanium_class" "mmshf")]) |
891 | |
111 | 892 (define_insn "*vec_interleave_highv4hi" |
0 | 893 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") |
894 (vec_select:V4HI | |
895 (vec_concat:V8HI | |
896 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") | |
897 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")) | |
67
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diff
changeset
|
898 (parallel [(const_int 2) (const_int 6) |
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|
899 (const_int 3) (const_int 7)])))] |
0 | 900 "" |
67
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diff
changeset
|
901 { |
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diff
changeset
|
902 /* Recall that vector elements are numbered in memory order. */ |
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diff
changeset
|
903 if (TARGET_BIG_ENDIAN) |
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55
diff
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|
904 return "%,unpack2.h %0 = %r1, %r2"; |
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55
diff
changeset
|
905 else |
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parents:
55
diff
changeset
|
906 return "%,unpack2.h %0 = %r2, %r1"; |
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55
diff
changeset
|
907 } |
0 | 908 [(set_attr "itanium_class" "mmshf")]) |
909 | |
67
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55
diff
changeset
|
910 (define_insn "mix2_even" |
0 | 911 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") |
912 (vec_select:V4HI | |
913 (vec_concat:V8HI | |
914 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") | |
915 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")) | |
67
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55
diff
changeset
|
916 (parallel [(const_int 0) (const_int 4) |
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55
diff
changeset
|
917 (const_int 2) (const_int 6)])))] |
0 | 918 "" |
67
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55
diff
changeset
|
919 { |
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55
diff
changeset
|
920 /* Recall that vector elements are numbered in memory order. */ |
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55
diff
changeset
|
921 if (TARGET_BIG_ENDIAN) |
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diff
changeset
|
922 return "%,mix2.l %0 = %r1, %r2"; |
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diff
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|
923 else |
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diff
changeset
|
924 return "%,mix2.r %0 = %r2, %r1"; |
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55
diff
changeset
|
925 } |
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diff
changeset
|
926 [(set_attr "itanium_class" "mmshf")]) |
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55
diff
changeset
|
927 |
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55
diff
changeset
|
928 (define_insn "mix2_odd" |
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diff
changeset
|
929 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") |
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diff
changeset
|
930 (vec_select:V4HI |
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55
diff
changeset
|
931 (vec_concat:V8HI |
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diff
changeset
|
932 (match_operand:V4HI 1 "gr_reg_or_0_operand" "rU") |
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diff
changeset
|
933 (match_operand:V4HI 2 "gr_reg_or_0_operand" "rU")) |
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diff
changeset
|
934 (parallel [(const_int 1) (const_int 5) |
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diff
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|
935 (const_int 3) (const_int 7)])))] |
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diff
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|
936 "" |
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55
diff
changeset
|
937 { |
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55
diff
changeset
|
938 /* Recall that vector elements are numbered in memory order. */ |
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diff
changeset
|
939 if (TARGET_BIG_ENDIAN) |
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diff
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|
940 return "%,mix2.r %0 = %r1, %r2"; |
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diff
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|
941 else |
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diff
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|
942 return "%,mix2.l %0 = %r2, %r1"; |
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diff
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|
943 } |
0 | 944 [(set_attr "itanium_class" "mmshf")]) |
945 | |
946 (define_insn "*mux2" | |
947 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") | |
948 (vec_select:V4HI | |
949 (match_operand:V4HI 1 "gr_register_operand" "r") | |
950 (parallel [(match_operand 2 "const_int_2bit_operand" "") | |
951 (match_operand 3 "const_int_2bit_operand" "") | |
952 (match_operand 4 "const_int_2bit_operand" "") | |
953 (match_operand 5 "const_int_2bit_operand" "")])))] | |
954 "" | |
955 { | |
67
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diff
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|
956 int mask = 0; |
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diff
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|
957 if (TARGET_BIG_ENDIAN) |
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diff
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|
958 { |
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|
959 mask |= (3 - INTVAL (operands[2])) << 6; |
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|
960 mask |= (3 - INTVAL (operands[3])) << 4; |
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|
961 mask |= (3 - INTVAL (operands[4])) << 2; |
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|
962 mask |= 3 - INTVAL (operands[5]); |
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|
963 } |
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|
964 else |
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diff
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|
965 { |
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diff
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|
966 mask |= INTVAL (operands[2]); |
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|
967 mask |= INTVAL (operands[3]) << 2; |
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|
968 mask |= INTVAL (operands[4]) << 4; |
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|
969 mask |= INTVAL (operands[5]) << 6; |
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diff
changeset
|
970 } |
0 | 971 operands[2] = GEN_INT (mask); |
972 return "%,mux2 %0 = %1, %2"; | |
973 } | |
974 [(set_attr "itanium_class" "mmshf")]) | |
975 | |
976 (define_insn "*mux2_brcst_hi" | |
977 [(set (match_operand:V4HI 0 "gr_register_operand" "=r") | |
978 (vec_duplicate:V4HI | |
979 (match_operand:HI 1 "gr_register_operand" "r")))] | |
980 "" | |
981 "mux2 %0 = %1, 0" | |
982 [(set_attr "itanium_class" "mmshf")]) | |
983 | |
111 | 984 (define_insn "*vec_interleave_lowv2si" |
67
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diff
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|
985 [(set (match_operand:V2SI 0 "gr_register_operand" "=r") |
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diff
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|
986 (vec_select:V2SI |
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diff
changeset
|
987 (vec_concat:V4SI |
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diff
changeset
|
988 (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU") |
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diff
changeset
|
989 (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU")) |
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diff
changeset
|
990 (parallel [(const_int 0) (const_int 2)])))] |
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diff
changeset
|
991 "" |
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changeset
|
992 { |
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|
993 /* Recall that vector elements are numbered in memory order. */ |
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diff
changeset
|
994 if (TARGET_BIG_ENDIAN) |
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diff
changeset
|
995 return "%,unpack4.l %0 = %r1, %r2"; |
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changeset
|
996 else |
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changeset
|
997 return "%,unpack4.l %0 = %r2, %r1"; |
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diff
changeset
|
998 } |
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diff
changeset
|
999 [(set_attr "itanium_class" "mmshf")]) |
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diff
changeset
|
1000 |
111 | 1001 (define_insn "*vec_interleave_highv2si" |
0 | 1002 [(set (match_operand:V2SI 0 "gr_register_operand" "=r") |
1003 (vec_select:V2SI | |
1004 (vec_concat:V4SI | |
1005 (match_operand:V2SI 1 "gr_reg_or_0_operand" "rU") | |
1006 (match_operand:V2SI 2 "gr_reg_or_0_operand" "rU")) | |
67
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diff
changeset
|
1007 (parallel [(const_int 1) (const_int 3)])))] |
0 | 1008 "" |
67
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diff
changeset
|
1009 { |
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diff
changeset
|
1010 /* Recall that vector elements are numbered in memory order. */ |
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diff
changeset
|
1011 if (TARGET_BIG_ENDIAN) |
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changeset
|
1012 return "%,unpack4.h %0 = %r1, %r2"; |
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changeset
|
1013 else |
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|
1014 return "%,unpack4.h %0 = %r2, %r1"; |
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diff
changeset
|
1015 } |
0 | 1016 [(set_attr "itanium_class" "mmshf")]) |
1017 | |
111 | 1018 (define_expand "vec_initv2sisi" |
0 | 1019 [(match_operand:V2SI 0 "gr_register_operand" "") |
1020 (match_operand 1 "" "")] | |
1021 "" | |
1022 { | |
1023 rtx op1 = XVECEXP (operands[1], 0, 0); | |
1024 rtx op2 = XVECEXP (operands[1], 0, 1); | |
1025 rtx x; | |
1026 | |
1027 if (GET_CODE (op1) == CONST_INT && GET_CODE (op2) == CONST_INT) | |
1028 { | |
1029 x = gen_rtx_CONST_VECTOR (V2SImode, XVEC (operands[1], 0)); | |
1030 emit_move_insn (operands[0], x); | |
1031 DONE; | |
1032 } | |
1033 | |
1034 if (!gr_reg_or_0_operand (op1, SImode)) | |
1035 op1 = force_reg (SImode, op1); | |
1036 if (!gr_reg_or_0_operand (op2, SImode)) | |
1037 op2 = force_reg (SImode, op2); | |
1038 | |
67
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diff
changeset
|
1039 x = gen_rtx_VEC_CONCAT (V2SImode, op1, op2); |
111 | 1040 emit_insn (gen_rtx_SET (operands[0], x)); |
0 | 1041 DONE; |
1042 }) | |
1043 | |
1044 (define_insn "*vecinit_v2si" | |
1045 [(set (match_operand:V2SI 0 "gr_register_operand" "=r") | |
1046 (vec_concat:V2SI | |
1047 (match_operand:SI 1 "gr_reg_or_0_operand" "rO") | |
1048 (match_operand:SI 2 "gr_reg_or_0_operand" "rO")))] | |
1049 "" | |
67
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diff
changeset
|
1050 { |
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diff
changeset
|
1051 /* Recall that vector elements are numbered in memory order. */ |
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diff
changeset
|
1052 if (TARGET_BIG_ENDIAN) |
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diff
changeset
|
1053 return "%,unpack4.l %0 = %r1, %r2"; |
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1054 else |
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1055 return "%,unpack4.l %0 = %r2, %r1"; |
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1056 } |
0 | 1057 [(set_attr "itanium_class" "mmshf")]) |
1058 | |
1059 ;; Missing operations | |
1060 ;; padd.uus | |
1061 ;; pavg | |
1062 ;; pavgsub | |
1063 ;; psad | |
1064 ;; pshladd | |
1065 ;; pshradd | |
1066 ;; psub.uus | |
1067 | |
1068 ;; Floating point vector operations | |
1069 | |
1070 (define_expand "movv2sf" | |
1071 [(set (match_operand:V2SF 0 "general_operand" "") | |
1072 (match_operand:V2SF 1 "general_operand" ""))] | |
1073 "" | |
1074 { | |
1075 rtx op1 = ia64_expand_move (operands[0], operands[1]); | |
1076 if (!op1) | |
1077 DONE; | |
1078 operands[1] = op1; | |
1079 }) | |
1080 | |
1081 (define_insn "*movv2sf_internal" | |
1082 [(set (match_operand:V2SF 0 "destination_operand" | |
1083 "=f,f,f,Q,*r ,*r,*r,*r,m ,f ,*r") | |
1084 (match_operand:V2SF 1 "move_operand" | |
1085 "fU,Y,Q,f,U*r,W ,i ,m ,*r,*r,f "))] | |
1086 "ia64_move_ok (operands[0], operands[1])" | |
1087 { | |
1088 static const char * const alt[] = { | |
1089 "%,mov %0 = %F1", | |
1090 "%,fpack %0 = %F2, %F1", | |
1091 "%,ldf8 %0 = %1%P1", | |
1092 "%,stf8 %0 = %1%P0", | |
1093 "%,mov %0 = %r1", | |
1094 "%,addl %0 = %v1, r0", | |
1095 "%,movl %0 = %v1", | |
1096 "%,ld8%O1 %0 = %1%P1", | |
1097 "%,st8%Q0 %0 = %r1%P0", | |
1098 "%,setf.sig %0 = %1", | |
1099 "%,getf.sig %0 = %1" | |
1100 }; | |
1101 | |
1102 if (which_alternative == 1) | |
1103 { | |
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1104 operands[2] = XVECEXP (operands[1], 0, TARGET_BIG_ENDIAN ? 0 : 1); |
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1105 operands[1] = XVECEXP (operands[1], 0, TARGET_BIG_ENDIAN ? 1 : 0); |
0 | 1106 } |
1107 | |
1108 return alt[which_alternative]; | |
1109 } | |
1110 [(set_attr "itanium_class" "fmisc,fmisc,fld,stf,ialu,ialu,long_i,ld,st,tofr,frfr")]) | |
1111 | |
1112 (define_insn "absv2sf2" | |
1113 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | |
1114 (abs:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")))] | |
1115 "" | |
1116 "fpabs %0 = %1" | |
1117 [(set_attr "itanium_class" "fmisc")]) | |
1118 | |
1119 (define_insn "negv2sf2" | |
1120 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | |
1121 (neg:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")))] | |
1122 "" | |
1123 "fpneg %0 = %1" | |
1124 [(set_attr "itanium_class" "fmisc")]) | |
1125 | |
1126 (define_insn "*negabsv2sf2" | |
1127 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | |
1128 (neg:V2SF | |
1129 (abs:V2SF (match_operand:V2SF 1 "fr_register_operand" "f"))))] | |
1130 "" | |
1131 "fpnegabs %0 = %1" | |
1132 [(set_attr "itanium_class" "fmisc")]) | |
1133 | |
1134 (define_expand "addv2sf3" | |
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1135 [(set (match_operand:V2SF 0 "fr_register_operand" "") |
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1136 (fma:V2SF (match_operand:V2SF 1 "fr_register_operand" "") |
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1137 (match_dup 3) |
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1138 (match_operand:V2SF 2 "fr_register_operand" "")))] |
0 | 1139 "" |
1140 { | |
131 | 1141 operands[3] = force_reg (V2SFmode, CONST1_RTX (V2SFmode)); |
0 | 1142 }) |
1143 | |
1144 (define_expand "subv2sf3" | |
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1145 [(set (match_operand:V2SF 0 "fr_register_operand" "") |
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1146 (fma:V2SF |
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1147 (match_operand:V2SF 1 "fr_register_operand" "") |
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1148 (match_dup 3) |
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1149 (neg:V2SF (match_operand:V2SF 2 "fr_register_operand" ""))))] |
0 | 1150 "" |
1151 { | |
131 | 1152 operands[3] = force_reg (V2SFmode, CONST1_RTX (V2SFmode)); |
0 | 1153 }) |
1154 | |
1155 (define_insn "mulv2sf3" | |
1156 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | |
1157 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") | |
1158 (match_operand:V2SF 2 "fr_register_operand" "f")))] | |
1159 "" | |
1160 "fpmpy %0 = %1, %2" | |
1161 [(set_attr "itanium_class" "fmac")]) | |
1162 | |
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1163 (define_insn "fmav2sf4" |
0 | 1164 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") |
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1165 (fma:V2SF |
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1166 (match_operand:V2SF 1 "fr_register_operand" "f") |
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1167 (match_operand:V2SF 2 "fr_register_operand" "f") |
0 | 1168 (match_operand:V2SF 3 "fr_register_operand" "f")))] |
1169 "" | |
1170 "fpma %0 = %1, %2, %3" | |
1171 [(set_attr "itanium_class" "fmac")]) | |
1172 | |
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1173 (define_insn "fmsv2sf4" |
0 | 1174 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") |
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1175 (fma:V2SF |
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1176 (match_operand:V2SF 1 "fr_register_operand" "f") |
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1177 (match_operand:V2SF 2 "fr_register_operand" "f") |
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1178 (neg:V2SF (match_operand:V2SF 3 "fr_register_operand" "f"))))] |
0 | 1179 "" |
1180 "fpms %0 = %1, %2, %3" | |
1181 [(set_attr "itanium_class" "fmac")]) | |
1182 | |
1183 (define_insn "*fpnmpy" | |
1184 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | |
1185 (neg:V2SF | |
1186 (mult:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") | |
1187 (match_operand:V2SF 2 "fr_register_operand" "f"))))] | |
1188 "" | |
1189 "fpnmpy %0 = %1, %2" | |
1190 [(set_attr "itanium_class" "fmac")]) | |
1191 | |
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1192 (define_insn "fnmav2sf4" |
0 | 1193 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") |
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1194 (fma:V2SF |
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1195 (neg:V2SF (match_operand:V2SF 1 "fr_register_operand" "f")) |
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1196 (match_operand:V2SF 2 "fr_register_operand" "f") |
0 | 1197 (match_operand:V2SF 3 "fr_register_operand" "f")))] |
1198 "" | |
1199 "fpnma %0 = %1, %2, %3" | |
1200 [(set_attr "itanium_class" "fmac")]) | |
1201 | |
1202 (define_insn "smaxv2sf3" | |
1203 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | |
1204 (smax:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") | |
1205 (match_operand:V2SF 2 "fr_register_operand" "f")))] | |
1206 "" | |
1207 "fpmax %0 = %1, %2" | |
1208 [(set_attr "itanium_class" "fmisc")]) | |
1209 | |
1210 (define_insn "sminv2sf3" | |
1211 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | |
1212 (smin:V2SF (match_operand:V2SF 1 "fr_register_operand" "f") | |
1213 (match_operand:V2SF 2 "fr_register_operand" "f")))] | |
1214 "" | |
1215 "fpmin %0 = %1, %2" | |
1216 [(set_attr "itanium_class" "fmisc")]) | |
1217 | |
1218 (define_expand "reduc_splus_v2sf" | |
1219 [(match_operand:V2SF 0 "fr_register_operand" "") | |
1220 (match_operand:V2SF 1 "fr_register_operand" "")] | |
1221 "" | |
1222 { | |
1223 rtx tmp = gen_reg_rtx (V2SFmode); | |
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1224 if (TARGET_BIG_ENDIAN) |
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1225 emit_insn (gen_fswap (tmp, CONST0_RTX (V2SFmode), operands[1])); |
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1226 else |
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1227 emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode))); |
0 | 1228 emit_insn (gen_addv2sf3 (operands[0], operands[1], tmp)); |
1229 DONE; | |
1230 }) | |
1231 | |
1232 (define_expand "reduc_smax_v2sf" | |
1233 [(match_operand:V2SF 0 "fr_register_operand" "") | |
1234 (match_operand:V2SF 1 "fr_register_operand" "")] | |
1235 "" | |
1236 { | |
1237 rtx tmp = gen_reg_rtx (V2SFmode); | |
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1238 if (TARGET_BIG_ENDIAN) |
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1239 emit_insn (gen_fswap (tmp, CONST0_RTX (V2SFmode), operands[1])); |
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1240 else |
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1241 emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode))); |
0 | 1242 emit_insn (gen_smaxv2sf3 (operands[0], operands[1], tmp)); |
1243 DONE; | |
1244 }) | |
1245 | |
1246 (define_expand "reduc_smin_v2sf" | |
1247 [(match_operand:V2SF 0 "fr_register_operand" "") | |
1248 (match_operand:V2SF 1 "fr_register_operand" "")] | |
1249 "" | |
1250 { | |
1251 rtx tmp = gen_reg_rtx (V2SFmode); | |
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1252 if (TARGET_BIG_ENDIAN) |
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1253 emit_insn (gen_fswap (tmp, CONST0_RTX (V2SFmode), operands[1])); |
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1254 else |
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1255 emit_insn (gen_fswap (tmp, operands[1], CONST0_RTX (V2SFmode))); |
0 | 1256 emit_insn (gen_sminv2sf3 (operands[0], operands[1], tmp)); |
1257 DONE; | |
1258 }) | |
1259 | |
111 | 1260 (define_expand "vcondv2sfv2sf" |
0 | 1261 [(set (match_operand:V2SF 0 "fr_register_operand" "") |
1262 (if_then_else:V2SF | |
1263 (match_operator 3 "" | |
1264 [(match_operand:V2SF 4 "fr_reg_or_0_operand" "") | |
1265 (match_operand:V2SF 5 "fr_reg_or_0_operand" "")]) | |
1266 (match_operand:V2SF 1 "fr_reg_or_0_operand" "") | |
1267 (match_operand:V2SF 2 "fr_reg_or_0_operand" "")))] | |
1268 "" | |
1269 { | |
1270 rtx x, cmp; | |
1271 | |
1272 cmp = gen_reg_rtx (V2SFmode); | |
1273 PUT_MODE (operands[3], V2SFmode); | |
111 | 1274 emit_insn (gen_rtx_SET (cmp, operands[3])); |
0 | 1275 |
1276 x = gen_rtx_IF_THEN_ELSE (V2SFmode, cmp, operands[1], operands[2]); | |
111 | 1277 emit_insn (gen_rtx_SET (operands[0], x)); |
0 | 1278 DONE; |
1279 }) | |
1280 | |
1281 (define_insn "*fpcmp" | |
1282 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | |
1283 (match_operator:V2SF 3 "comparison_operator" | |
1284 [(match_operand:V2SF 1 "fr_reg_or_0_operand" "fU") | |
1285 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")]))] | |
1286 "" | |
1287 "fpcmp.%D3 %0 = %F1, %F2" | |
1288 [(set_attr "itanium_class" "fmisc")]) | |
1289 | |
1290 (define_insn "*fselect" | |
1291 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | |
1292 (if_then_else:V2SF | |
1293 (match_operand:V2SF 1 "fr_register_operand" "f") | |
1294 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU") | |
1295 (match_operand:V2SF 3 "fr_reg_or_0_operand" "fU")))] | |
1296 "" | |
1297 "fselect %0 = %F2, %F3, %1" | |
1298 [(set_attr "itanium_class" "fmisc")]) | |
1299 | |
111 | 1300 (define_expand "vec_initv2sfsf" |
0 | 1301 [(match_operand:V2SF 0 "fr_register_operand" "") |
1302 (match_operand 1 "" "")] | |
1303 "" | |
1304 { | |
1305 rtx op1 = XVECEXP (operands[1], 0, 0); | |
1306 rtx op2 = XVECEXP (operands[1], 0, 1); | |
1307 rtx x; | |
1308 | |
1309 if (GET_CODE (op1) == CONST_DOUBLE && GET_CODE (op2) == CONST_DOUBLE) | |
1310 { | |
1311 x = gen_rtx_CONST_VECTOR (V2SFmode, XVEC (operands[1], 0)); | |
1312 emit_move_insn (operands[0], x); | |
1313 DONE; | |
1314 } | |
1315 | |
1316 if (!fr_reg_or_fp01_operand (op1, SFmode)) | |
1317 op1 = force_reg (SFmode, op1); | |
1318 if (!fr_reg_or_fp01_operand (op2, SFmode)) | |
1319 op2 = force_reg (SFmode, op2); | |
1320 | |
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1321 emit_insn (gen_fpack (operands[0], op1, op2)); |
0 | 1322 DONE; |
1323 }) | |
1324 | |
1325 (define_insn "fpack" | |
1326 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | |
1327 (vec_concat:V2SF | |
1328 (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") | |
1329 (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))] | |
1330 "" | |
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1331 { |
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|
1332 /* Recall that vector elements are numbered in memory order. */ |
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1333 if (TARGET_BIG_ENDIAN) |
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1334 return "%,fpack %0 = %F1, %F2"; |
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1335 else |
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1336 return "%,fpack %0 = %F2, %F1"; |
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|
1337 } |
0 | 1338 [(set_attr "itanium_class" "fmisc")]) |
1339 | |
1340 (define_insn "fswap" | |
1341 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | |
1342 (vec_select:V2SF | |
1343 (vec_concat:V4SF | |
1344 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU") | |
1345 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")) | |
1346 (parallel [(const_int 1) (const_int 2)])))] | |
1347 "" | |
67
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1348 { |
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|
1349 /* Recall that vector elements are numbered in memory order. */ |
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|
1350 if (TARGET_BIG_ENDIAN) |
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1351 return "%,fswap %0 = %F2, %F1"; |
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1352 else |
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1353 return "%,fswap %0 = %F1, %F2"; |
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1354 } |
0 | 1355 [(set_attr "itanium_class" "fmisc")]) |
1356 | |
111 | 1357 (define_insn "*vec_interleave_highv2sf" |
0 | 1358 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") |
1359 (vec_select:V2SF | |
1360 (vec_concat:V4SF | |
1361 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU") | |
1362 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")) | |
1363 (parallel [(const_int 1) (const_int 3)])))] | |
1364 "" | |
67
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|
1365 { |
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1366 /* Recall that vector elements are numbered in memory order. */ |
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1367 if (TARGET_BIG_ENDIAN) |
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1368 return "%,fmix.l %0 = %F1, %F2"; |
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1369 else |
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1370 return "%,fmix.l %0 = %F2, %F1"; |
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1371 } |
0 | 1372 [(set_attr "itanium_class" "fmisc")]) |
1373 | |
111 | 1374 (define_insn "*vec_interleave_lowv2sf" |
0 | 1375 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") |
1376 (vec_select:V2SF | |
1377 (vec_concat:V4SF | |
1378 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU") | |
1379 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")) | |
1380 (parallel [(const_int 0) (const_int 2)])))] | |
1381 "" | |
67
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1382 { |
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|
1383 /* Recall that vector elements are numbered in memory order. */ |
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1384 if (TARGET_BIG_ENDIAN) |
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1385 return "%,fmix.r %0 = %F1, %F2"; |
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1386 else |
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1387 return "%,fmix.r %0 = %F2, %F1"; |
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1388 } |
0 | 1389 [(set_attr "itanium_class" "fmisc")]) |
1390 | |
1391 (define_insn "fmix_lr" | |
1392 [(set (match_operand:V2SF 0 "fr_register_operand" "=f") | |
1393 (vec_select:V2SF | |
1394 (vec_concat:V4SF | |
1395 (match_operand:V2SF 1 "fr_reg_or_0_operand" "fU") | |
1396 (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")) | |
1397 (parallel [(const_int 0) (const_int 3)])))] | |
1398 "" | |
67
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|
1399 { |
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|
1400 /* Recall that vector elements are numbered in memory order. */ |
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|
1401 if (TARGET_BIG_ENDIAN) |
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1402 return "%,fmix.lr %0 = %F1, %F2"; |
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1403 else |
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1404 return "%,fmix.lr %0 = %F2, %F1"; |
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1405 } |
0 | 1406 [(set_attr "itanium_class" "fmisc")]) |
1407 | |
1408 (define_expand "vec_setv2sf" | |
1409 [(match_operand:V2SF 0 "fr_register_operand" "") | |
1410 (match_operand:SF 1 "fr_register_operand" "") | |
1411 (match_operand 2 "const_int_operand" "")] | |
1412 "" | |
1413 { | |
111 | 1414 ia64_expand_vec_setv2sf (operands); |
0 | 1415 DONE; |
1416 }) | |
1417 | |
1418 (define_insn_and_split "*vec_extractv2sf_0_le" | |
1419 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,f,m") | |
1420 (unspec:SF [(match_operand:V2SF 1 "nonimmediate_operand" "rfm,rm,r") | |
1421 (const_int 0)] | |
1422 UNSPEC_VECT_EXTR))] | |
1423 "!TARGET_BIG_ENDIAN" | |
1424 "#" | |
1425 "reload_completed" | |
1426 [(set (match_dup 0) (match_dup 1))] | |
1427 { | |
1428 if (REG_P (operands[1]) && FR_REGNO_P (REGNO (operands[1]))) | |
1429 operands[0] = gen_rtx_REG (V2SFmode, REGNO (operands[0])); | |
1430 else if (MEM_P (operands[1])) | |
1431 operands[1] = adjust_address (operands[1], SFmode, 0); | |
1432 else | |
1433 operands[1] = gen_rtx_REG (SFmode, REGNO (operands[1])); | |
1434 }) | |
1435 | |
1436 (define_insn_and_split "*vec_extractv2sf_0_be" | |
67
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|
1437 [(set (match_operand:SF 0 "register_operand" "=rf,r") |
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|
1438 (unspec:SF [(match_operand:V2SF 1 "nonimmediate_operand" "m,r") |
0 | 1439 (const_int 0)] |
1440 UNSPEC_VECT_EXTR))] | |
1441 "TARGET_BIG_ENDIAN" | |
1442 "#" | |
1443 "reload_completed" | |
1444 [(set (match_dup 0) (match_dup 1))] | |
1445 { | |
67
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|
1446 if (MEM_P (operands[1])) |
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|
1447 operands[1] = adjust_address (operands[1], SFmode, 0); |
0 | 1448 else |
67
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|
1449 { |
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|
1450 emit_insn (gen_lshrdi3 (operands[0], operands[1], GEN_INT (32))); |
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|
1451 DONE; |
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|
1452 } |
0 | 1453 }) |
1454 | |
67
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diff
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|
1455 (define_insn_and_split "*vec_extractv2sf_1_le" |
0 | 1456 [(set (match_operand:SF 0 "register_operand" "=r") |
1457 (unspec:SF [(match_operand:V2SF 1 "register_operand" "r") | |
1458 (const_int 1)] | |
1459 UNSPEC_VECT_EXTR))] | |
67
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diff
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|
1460 "!TARGET_BIG_ENDIAN" |
0 | 1461 "#" |
67
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diff
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|
1462 "&& reload_completed" |
0 | 1463 [(const_int 0)] |
1464 { | |
1465 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0])); | |
1466 operands[1] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
67
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|
1467 emit_insn (gen_lshrdi3 (operands[0], operands[1], GEN_INT (32))); |
0 | 1468 DONE; |
1469 }) | |
1470 | |
67
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|
1471 (define_insn_and_split "*vec_extractv2sf_1_be" |
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|
1472 [(set (match_operand:SF 0 "register_operand" "=rf") |
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|
1473 (unspec:SF [(match_operand:V2SF 1 "register_operand" "r") |
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|
1474 (const_int 1)] |
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|
1475 UNSPEC_VECT_EXTR))] |
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|
1476 "TARGET_BIG_ENDIAN" |
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|
1477 "#" |
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|
1478 "&& reload_completed" |
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|
1479 [(set (match_dup 0) (match_dup 1))] |
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|
1480 { |
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changeset
|
1481 operands[1] = gen_rtx_REG (SFmode, REGNO (operands[1])); |
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|
1482 }) |
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|
1483 |
111 | 1484 (define_expand "vec_extractv2sfsf" |
0 | 1485 [(set (match_operand:SF 0 "register_operand" "") |
1486 (unspec:SF [(match_operand:V2SF 1 "register_operand" "") | |
1487 (match_operand:DI 2 "const_int_operand" "")] | |
1488 UNSPEC_VECT_EXTR))] | |
1489 "" | |
1490 "") | |
1491 | |
67
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changeset
|
1492 (define_expand "vec_unpacku_lo_<mode>" |
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|
1493 [(match_operand:<vecwider> 0 "register_operand" "") |
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|
1494 (match_operand:VECINT12 1 "register_operand" "")] |
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|
1495 "" |
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changeset
|
1496 { |
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diff
changeset
|
1497 ia64_expand_unpack (operands, true, false); |
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changeset
|
1498 DONE; |
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|
1499 }) |
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changeset
|
1500 |
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diff
changeset
|
1501 (define_expand "vec_unpacku_hi_<mode>" |
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changeset
|
1502 [(match_operand:<vecwider> 0 "register_operand" "") |
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changeset
|
1503 (match_operand:VECINT12 1 "register_operand" "")] |
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1504 "" |
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1505 { |
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1506 ia64_expand_unpack (operands, true, true); |
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1507 DONE; |
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1508 }) |
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1509 |
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1510 (define_expand "vec_unpacks_lo_<mode>" |
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1511 [(match_operand:<vecwider> 0 "register_operand" "") |
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1512 (match_operand:VECINT12 1 "register_operand" "")] |
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1513 "" |
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1514 { |
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1515 ia64_expand_unpack (operands, false, false); |
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1516 DONE; |
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1517 }) |
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1518 |
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1519 (define_expand "vec_unpacks_hi_<mode>" |
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1520 [(match_operand:<vecwider> 0 "register_operand" "") |
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1521 (match_operand:VECINT12 1 "register_operand" "")] |
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1522 "" |
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1523 { |
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1524 ia64_expand_unpack (operands, false, true); |
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1525 DONE; |
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1526 }) |
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1527 |
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1528 (define_expand "vec_pack_trunc_v4hi" |
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1529 [(match_operand:V8QI 0 "gr_register_operand" "") |
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1530 (match_operand:V4HI 1 "gr_register_operand" "") |
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1531 (match_operand:V4HI 2 "gr_register_operand" "")] |
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1532 "" |
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1533 { |
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1534 rtx op1 = gen_lowpart (V8QImode, operands[1]); |
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1535 rtx op2 = gen_lowpart (V8QImode, operands[2]); |
111 | 1536 ia64_expand_vec_perm_even_odd (operands[0], op1, op2, TARGET_BIG_ENDIAN); |
67
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1537 DONE; |
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1538 }) |
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1539 |
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1540 (define_expand "vec_pack_trunc_v2si" |
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1541 [(match_operand:V4HI 0 "gr_register_operand" "") |
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1542 (match_operand:V2SI 1 "gr_register_operand" "") |
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1543 (match_operand:V2SI 2 "gr_register_operand" "")] |
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1544 "" |
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1545 { |
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1546 rtx op1 = gen_lowpart (V4HImode, operands[1]); |
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1547 rtx op2 = gen_lowpart (V4HImode, operands[2]); |
111 | 1548 ia64_expand_vec_perm_even_odd (operands[0], op1, op2, TARGET_BIG_ENDIAN); |
1549 DONE; | |
1550 }) | |
1551 | |
0 | 1552 ;; Missing operations |
1553 ;; fprcpa | |
1554 ;; fpsqrta |