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1 ;; Machine Descriptions for R8C/M16C/M32C
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2 ;; Copyright (C) 2005-2018 Free Software Foundation, Inc.
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3 ;; Contributed by Red Hat.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; multiply and divide
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22
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23 ; Here is the pattern for the const_int.
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24 (define_insn "mulqihi3_c"
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25 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
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26 (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
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27 (match_operand 2 "immediate_operand" "i,i")))]
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28 ""
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29 "mul.b\t%2,%1"
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30 [(set_attr "flags" "o")]
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31 )
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32
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33 ; Here is the pattern for registers and such.
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34 (define_insn "mulqihi3_r"
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35 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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36 (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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37 (sign_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
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38 ""
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39 "mul.b\t%2,%1"
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40 [(set_attr "flags" "o")]
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41 )
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42
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43 ; Don't try to sign_extend a const_int. Same for all other multiplies.
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44 (define_expand "mulqihi3"
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45 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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46 (mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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47 (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
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48 ""
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49 "{ if (GET_MODE (operands[2]) != VOIDmode)
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50 operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]); }"
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51 )
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52
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53 (define_insn "umulqihi3_c"
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54 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
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55 (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0"))
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56 (match_operand 2 "immediate_operand" "i,i")))]
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57 ""
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58 "mulu.b\t%U2,%1"
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59 [(set_attr "flags" "o")]
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60 )
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61
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62 (define_insn "umulqihi3_r"
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63 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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64 (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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65 (zero_extend:HI (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm"))))]
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66 ""
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67 "mulu.b\t%U2,%1"
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68 [(set_attr "flags" "o")]
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69 )
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70
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71 (define_expand "umulqihi3"
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72 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
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73 (mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0"))
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74 (match_operand:QI 2 "mra_operand" "RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
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75 ""
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76 "{ if (GET_MODE (operands[2]) != VOIDmode)
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77 operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]); }"
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78 )
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79
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80 (define_insn "mulhisi3_c"
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81 [(set (match_operand:SI 0 "ra_operand" "=Rsi")
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82 (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0"))
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83 (match_operand:HI 2 "immediate_operand" "i")))]
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84 ""
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85 "mul.w\t%2,%1"
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86 [(set_attr "flags" "o")]
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87 )
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88
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89 (define_insn "mulhisi3_r"
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90 [(set (match_operand:SI 0 "mra_operand" "=Rsi,Rsi")
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91 (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
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92 (sign_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm"))))]
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93 ""
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94 "mul.w\t%2,%1"
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95 [(set_attr "flags" "o")]
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96 )
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97
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98 (define_expand "mulhisi3"
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99 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
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100 (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
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101 (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
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102 ""
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103 "{ if (GET_MODE (operands[2]) != VOIDmode)
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104 operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]); }"
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105 )
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106
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107 (define_insn "umulhisi3_c"
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108 [(set (match_operand:SI 0 "ra_operand" "=Rsi")
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109 (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0"))
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110 (match_operand 2 "immediate_operand" "i")))]
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111 ""
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112 "mulu.w\t%u2,%1"
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113 [(set_attr "flags" "o")]
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114 )
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115
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116 (define_insn "umulhisi3_r"
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117 [(set (match_operand:SI 0 "mra_operand" "=Rsi,Rsi")
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118 (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0"))
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119 (zero_extend:SI (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm"))))]
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120 ""
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121 "mulu.w\t%u2,%1"
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122 [(set_attr "flags" "o")]
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123 )
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124
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125 (define_expand "umulhisi3"
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126 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
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127 (mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand" "%0,0,0,0"))
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128 (match_operand:HI 2 "mra_operand" "RhiSd,?Rmm,RhiSd,?Rmm")))]
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129 ""
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130 "{ if (GET_MODE (operands[2]) != VOIDmode)
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131 operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]); }"
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132 )
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133
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134
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135 ; GCC expects to be able to multiply pointer-sized integers too, but
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136 ; fortunately it only multiplies by powers of two, although sometimes
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137 ; they're negative.
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138 (define_insn "mulpsi3_op"
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139 [(set (match_operand:PSI 0 "mra_operand" "=RsiSd")
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140 (mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
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141 (match_operand 2 "m32c_psi_scale" "Ilb")))]
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142 "TARGET_A24"
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143 "shl.l\t%b2,%0"
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144 [(set_attr "flags" "szc")]
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145 )
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146
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147 (define_expand "mulpsi3"
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148 [(set (match_operand:PSI 0 "mra_operand" "=RsiSd")
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149 (mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
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150 (match_operand 2 "m32c_psi_scale" "Ilb")))]
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151 "TARGET_A24"
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152 "if (GET_CODE (operands[2]) != CONST_INT
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153 || ! m32c_psi_scale (operands[2], PSImode))
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154 {
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155 m32c_expand_neg_mulpsi3 (operands);
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156 DONE;
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157 }"
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158 )
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159
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160 (define_insn "mulsi3"
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161 [(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
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162 (mult:SI (match_operand:SI 1 "r0123_operand" "%0,0")
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163 (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
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164 "TARGET_M32C"
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165 "mul.l\t%2,%1"
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166 [(set_attr "flags" "o")]
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167 )
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168
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169 (define_expand "divmodqi4"
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170 [(set (match_dup 4)
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171 (sign_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
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172 (parallel [(set (match_operand:QI 0 "register_operand" "=R0w,R0w")
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173 (div:QI (match_dup 4)
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174 (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
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175 (set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
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176 (mod:QI (match_dup 4) (match_dup 2)))
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177 ])]
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178 "0"
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179 "operands[4] = gen_reg_rtx (HImode);"
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180 )
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181
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182 (define_insn "divmodqi4_n"
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183 [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
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184 (div:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
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185 (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
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186 (set (match_operand:QI 3 "register_operand" "=R0h,R0h")
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187 (mod:QI (match_dup 1) (match_dup 2)))
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188 ]
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189 "0"
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190 "div.b\t%2"
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191 [(set_attr "flags" "o")]
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192 )
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193
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194 (define_expand "udivmodqi4"
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195 [(set (match_dup 4)
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196 (zero_extend:HI (match_operand:QI 1 "register_operand" "0,0")))
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197 (parallel [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
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198 (udiv:QI (match_dup 4)
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199 (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
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200 (set (match_operand:QI 3 "register_operand" "=&R0h,&R0h")
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201 (umod:QI (match_dup 4) (match_dup 2)))
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202 ])]
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203 "0"
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204 "operands[4] = gen_reg_rtx (HImode);"
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205 )
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206
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207 (define_insn "udivmodqi4_n"
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208 [(set (match_operand:QI 0 "register_operand" "=R0l,R0l")
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209 (udiv:QI (match_operand:HI 1 "register_operand" "R0w,R0w")
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210 (match_operand:QI 2 "general_operand" "iRqiSd,?Rmm")))
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211 (set (match_operand:QI 3 "register_operand" "=R0h,R0h")
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212 (umod:QI (match_dup 1) (match_dup 2)))
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213 ]
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214 "0"
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215 "divu.b\t%2"
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216 [(set_attr "flags" "o")]
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217 )
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218
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219 (define_expand "divmodhi4"
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220 [(set (match_dup 4)
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221 (sign_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
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222 (parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
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223 (div:HI (match_dup 4)
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224 (match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
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225 (set (match_operand:HI 3 "register_operand" "=R2w,R2w")
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226 (mod:HI (match_dup 4) (match_dup 2)))
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227 ])]
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228 ""
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229 "operands[4] = gen_reg_rtx (SImode);"
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230 )
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231
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232 (define_insn "divmodhi4_n"
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233 [(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
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234 (div:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
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235 (match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
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236 (set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
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237 (mod:HI (match_dup 1) (match_dup 2)))
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238 ]
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239 ""
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240 "div.w\t%2"
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241 [(set_attr "flags" "o")]
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242 )
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243
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244 (define_expand "udivmodhi4"
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245 [(set (match_dup 4)
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246 (zero_extend:SI (match_operand:HI 1 "register_operand" "0,0")))
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247 (parallel [(set (match_operand:HI 0 "register_operand" "=R0w,R0w")
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248 (udiv:HI (match_dup 4)
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249 (match_operand:HI 2 "general_operand" "iRhiSd,?Rmm")))
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250 (set (match_operand:HI 3 "register_operand" "=R2w,R2w")
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251 (umod:HI (match_dup 4) (match_dup 2)))
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252 ])]
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253 ""
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254 "operands[4] = gen_reg_rtx (SImode);"
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255 )
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256
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257 (define_insn "udivmodhi4_n"
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258 [(set (match_operand:HI 0 "m32c_r0_operand" "=R0w,R0w")
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259 (udiv:HI (match_operand:SI 1 "m32c_r0_operand" "R02,R02")
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260 (match_operand:HI 2 "m32c_notr2_operand" "iR1wR3wRaaSd,?Rmm")))
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261 (set (match_operand:HI 3 "m32c_r2_operand" "=R2w,R2w")
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262 (umod:HI (match_dup 1) (match_dup 2)))
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263 ]
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264 ""
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265 "divu.w\t%2"
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266 [(set_attr "flags" "o")]
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267 )
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268
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269 (define_insn "divsi3"
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270 [(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
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271 (div:SI (match_operand:SI 1 "r0123_operand" "0,0")
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272 (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
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273 "TARGET_M32C"
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274 "div.l\t%2"
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275 [(set_attr "flags" "o")]
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276 )
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277
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278 (define_insn "udivsi3"
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279 [(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
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280 (udiv:SI (match_operand:SI 1 "r0123_operand" "0,0")
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281 (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
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282 "TARGET_M32C"
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283 "divu.l\t%2"
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284 [(set_attr "flags" "o")]
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285 )
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286
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287
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