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annotate gcc/config/mips/sync.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
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1 ;; Machine Description for MIPS based processor synchronization
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2 ;; instructions.
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3 ;; Copyright (C) 2007-2018 Free Software Foundation, Inc.
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4
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify
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8 ;; it under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful,
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13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 ;; GNU General Public License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
67
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21 (define_c_enum "unspec" [
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22 UNSPEC_COMPARE_AND_SWAP
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23 UNSPEC_COMPARE_AND_SWAP_12
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24 UNSPEC_SYNC_OLD_OP
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25 UNSPEC_SYNC_NEW_OP
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26 UNSPEC_SYNC_NEW_OP_12
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27 UNSPEC_SYNC_OLD_OP_12
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28 UNSPEC_SYNC_EXCHANGE
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29 UNSPEC_SYNC_EXCHANGE_12
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30 UNSPEC_MEMORY_BARRIER
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31 UNSPEC_ATOMIC_COMPARE_AND_SWAP
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32 UNSPEC_ATOMIC_EXCHANGE
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33 UNSPEC_ATOMIC_FETCH_OP
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34 ])
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35
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36 ;; Atomic fetch bitwise operations.
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37 (define_code_iterator fetchop_bit [ior xor and])
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38
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39 ;; Atomic HI and QI operations
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40 (define_code_iterator atomic_hiqi_op [plus minus ior xor and])
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41
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42 ;; Atomic memory operations.
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43
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44 (define_expand "memory_barrier"
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45 [(set (match_dup 0)
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46 (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))]
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47 "GENERATE_SYNC"
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48 {
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49 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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50 MEM_VOLATILE_P (operands[0]) = 1;
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51 })
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52
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53 (define_insn "*memory_barrier"
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54 [(set (match_operand:BLK 0 "" "")
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55 (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))]
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56 "GENERATE_SYNC"
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57 { return mips_output_sync (); })
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58
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59 ;; Can be removed in favor of atomic_compare_and_swap below.
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60 (define_insn "sync_compare_and_swap<mode>"
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61 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
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62 (match_operand:GPR 1 "memory_operand" "+ZC,ZC"))
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63 (set (match_dup 1)
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64 (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "dJ,dJ")
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65 (match_operand:GPR 3 "arith_operand" "I,d")]
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66 UNSPEC_COMPARE_AND_SWAP))]
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67 "GENERATE_LL_SC"
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68 { return mips_output_sync_loop (insn, operands); }
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69 [(set_attr "sync_insn1" "li,move")
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70 (set_attr "sync_oldval" "0")
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71 (set_attr "sync_mem" "1")
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72 (set_attr "sync_required_oldval" "2")
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73 (set_attr "sync_insn1_op2" "3")])
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74
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75 (define_expand "sync_compare_and_swap<mode>"
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76 [(match_operand:SHORT 0 "register_operand")
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77 (match_operand:SHORT 1 "memory_operand")
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78 (match_operand:SHORT 2 "general_operand")
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79 (match_operand:SHORT 3 "general_operand")]
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80 "GENERATE_LL_SC"
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81 {
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82 union mips_gen_fn_ptrs generator;
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83 generator.fn_6 = gen_compare_and_swap_12;
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84 mips_expand_atomic_qihi (generator,
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85 operands[0], operands[1], operands[2], operands[3]);
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86 DONE;
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87 })
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88
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89 ;; Helper insn for mips_expand_atomic_qihi.
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90 (define_insn "compare_and_swap_12"
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91 [(set (match_operand:SI 0 "register_operand" "=&d,&d")
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92 (match_operand:SI 1 "memory_operand" "+ZC,ZC"))
0
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93 (set (match_dup 1)
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94 (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d,d")
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95 (match_operand:SI 3 "register_operand" "d,d")
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96 (match_operand:SI 4 "reg_or_0_operand" "dJ,dJ")
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97 (match_operand:SI 5 "reg_or_0_operand" "d,J")]
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98 UNSPEC_COMPARE_AND_SWAP_12))]
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99 "GENERATE_LL_SC"
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100 { return mips_output_sync_loop (insn, operands); }
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101 [(set_attr "sync_oldval" "0")
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102 (set_attr "sync_mem" "1")
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103 (set_attr "sync_inclusive_mask" "2")
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104 (set_attr "sync_exclusive_mask" "3")
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105 (set_attr "sync_required_oldval" "4")
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106 (set_attr "sync_insn1_op2" "5")])
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107
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108 (define_insn "sync_add<mode>"
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109 [(set (match_operand:GPR 0 "memory_operand" "+ZC,ZC")
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110 (unspec_volatile:GPR
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111 [(plus:GPR (match_dup 0)
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112 (match_operand:GPR 1 "arith_operand" "I,d"))]
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113 UNSPEC_SYNC_OLD_OP))]
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114 "GENERATE_LL_SC"
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115 { return mips_output_sync_loop (insn, operands); }
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116 [(set_attr "sync_insn1" "addiu,addu")
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117 (set_attr "sync_mem" "0")
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118 (set_attr "sync_insn1_op2" "1")])
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119
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120 (define_expand "sync_<optab><mode>"
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121 [(set (match_operand:SHORT 0 "memory_operand")
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122 (unspec_volatile:SHORT
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123 [(atomic_hiqi_op:SHORT (match_dup 0)
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124 (match_operand:SHORT 1 "general_operand"))]
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125 UNSPEC_SYNC_OLD_OP))]
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126 "GENERATE_LL_SC"
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127 {
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128 union mips_gen_fn_ptrs generator;
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129 generator.fn_4 = gen_sync_<optab>_12;
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130 mips_expand_atomic_qihi (generator,
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131 NULL, operands[0], operands[1], NULL);
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132 DONE;
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133 })
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134
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135 ;; Helper insn for sync_<optab><mode>
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136 (define_insn "sync_<optab>_12"
111
kono
parents: 67
diff changeset
137 [(set (match_operand:SI 0 "memory_operand" "+ZC")
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
138 (unspec_volatile:SI
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
139 [(match_operand:SI 1 "register_operand" "d")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
140 (match_operand:SI 2 "register_operand" "d")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
141 (atomic_hiqi_op:SI (match_dup 0)
111
kono
parents: 67
diff changeset
142 (match_operand:SI 3 "reg_or_0_operand" "dJ"))]
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
143 UNSPEC_SYNC_OLD_OP_12))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
144 (clobber (match_scratch:SI 4 "=&d"))]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
145 "GENERATE_LL_SC"
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
146 { return mips_output_sync_loop (insn, operands); }
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
147 [(set_attr "sync_insn1" "<insn>")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
148 (set_attr "sync_insn2" "and")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
149 (set_attr "sync_mem" "0")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
150 (set_attr "sync_inclusive_mask" "1")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
151 (set_attr "sync_exclusive_mask" "2")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
152 (set_attr "sync_insn1_op2" "3")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
153 (set_attr "sync_oldval" "4")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
154 (set_attr "sync_newval" "4")])
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
155
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
156 (define_expand "sync_old_<optab><mode>"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
157 [(parallel [
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
158 (set (match_operand:SHORT 0 "register_operand")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
159 (match_operand:SHORT 1 "memory_operand"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
160 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
161 (unspec_volatile:SHORT [(atomic_hiqi_op:SHORT
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
162 (match_dup 1)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
163 (match_operand:SHORT 2 "general_operand"))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
164 UNSPEC_SYNC_OLD_OP))])]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
165 "GENERATE_LL_SC"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
166 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
167 union mips_gen_fn_ptrs generator;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
168 generator.fn_5 = gen_sync_old_<optab>_12;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
169 mips_expand_atomic_qihi (generator,
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
170 operands[0], operands[1], operands[2], NULL);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
171 DONE;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
172 })
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
173
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
174 ;; Helper insn for sync_old_<optab><mode>
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
175 (define_insn "sync_old_<optab>_12"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
176 [(set (match_operand:SI 0 "register_operand" "=&d")
111
kono
parents: 67
diff changeset
177 (match_operand:SI 1 "memory_operand" "+ZC"))
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
178 (set (match_dup 1)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
179 (unspec_volatile:SI
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
180 [(match_operand:SI 2 "register_operand" "d")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
181 (match_operand:SI 3 "register_operand" "d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
182 (atomic_hiqi_op:SI (match_dup 0)
111
kono
parents: 67
diff changeset
183 (match_operand:SI 4 "reg_or_0_operand" "dJ"))]
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
184 UNSPEC_SYNC_OLD_OP_12))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
185 (clobber (match_scratch:SI 5 "=&d"))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
186 "GENERATE_LL_SC"
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
187 { return mips_output_sync_loop (insn, operands); }
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
188 [(set_attr "sync_insn1" "<insn>")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
189 (set_attr "sync_insn2" "and")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
190 (set_attr "sync_oldval" "0")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
191 (set_attr "sync_mem" "1")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
192 (set_attr "sync_inclusive_mask" "2")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
193 (set_attr "sync_exclusive_mask" "3")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
194 (set_attr "sync_insn1_op2" "4")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
195 (set_attr "sync_newval" "5")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
196
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
197 (define_expand "sync_new_<optab><mode>"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
198 [(parallel [
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
199 (set (match_operand:SHORT 0 "register_operand")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
200 (unspec_volatile:SHORT [(atomic_hiqi_op:SHORT
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
201 (match_operand:SHORT 1 "memory_operand")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
202 (match_operand:SHORT 2 "general_operand"))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
203 UNSPEC_SYNC_NEW_OP))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
204 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
205 (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
206 UNSPEC_SYNC_NEW_OP))])]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
207 "GENERATE_LL_SC"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
208 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
209 union mips_gen_fn_ptrs generator;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
210 generator.fn_5 = gen_sync_new_<optab>_12;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
211 mips_expand_atomic_qihi (generator,
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
212 operands[0], operands[1], operands[2], NULL);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
213 DONE;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
214 })
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
215
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
216 ;; Helper insn for sync_new_<optab><mode>
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
217 (define_insn "sync_new_<optab>_12"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
218 [(set (match_operand:SI 0 "register_operand" "=&d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
219 (unspec_volatile:SI
111
kono
parents: 67
diff changeset
220 [(match_operand:SI 1 "memory_operand" "+ZC")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
221 (match_operand:SI 2 "register_operand" "d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
222 (match_operand:SI 3 "register_operand" "d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
223 (atomic_hiqi_op:SI (match_dup 0)
111
kono
parents: 67
diff changeset
224 (match_operand:SI 4 "reg_or_0_operand" "dJ"))]
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
225 UNSPEC_SYNC_NEW_OP_12))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
226 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
227 (unspec_volatile:SI
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
228 [(match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
229 (match_dup 2)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
230 (match_dup 3)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
231 (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
232 "GENERATE_LL_SC"
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
233 { return mips_output_sync_loop (insn, operands); }
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
234 [(set_attr "sync_insn1" "<insn>")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
235 (set_attr "sync_insn2" "and")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
236 (set_attr "sync_oldval" "0")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
237 (set_attr "sync_newval" "0")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
238 (set_attr "sync_mem" "1")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
239 (set_attr "sync_inclusive_mask" "2")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
240 (set_attr "sync_exclusive_mask" "3")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
241 (set_attr "sync_insn1_op2" "4")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
242
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
243 (define_expand "sync_nand<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
244 [(set (match_operand:SHORT 0 "memory_operand")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
245 (unspec_volatile:SHORT
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
246 [(match_dup 0)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
247 (match_operand:SHORT 1 "general_operand")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
248 UNSPEC_SYNC_OLD_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
249 "GENERATE_LL_SC"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
250 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
251 union mips_gen_fn_ptrs generator;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
252 generator.fn_4 = gen_sync_nand_12;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
253 mips_expand_atomic_qihi (generator,
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
254 NULL, operands[0], operands[1], NULL);
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
255 DONE;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
256 })
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
257
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
258 ;; Helper insn for sync_nand<mode>
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
259 (define_insn "sync_nand_12"
111
kono
parents: 67
diff changeset
260 [(set (match_operand:SI 0 "memory_operand" "+ZC")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
261 (unspec_volatile:SI
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
262 [(match_operand:SI 1 "register_operand" "d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
263 (match_operand:SI 2 "register_operand" "d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
264 (match_dup 0)
111
kono
parents: 67
diff changeset
265 (match_operand:SI 3 "reg_or_0_operand" "dJ")]
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
266 UNSPEC_SYNC_OLD_OP_12))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
267 (clobber (match_scratch:SI 4 "=&d"))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
268 "GENERATE_LL_SC"
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
269 { return mips_output_sync_loop (insn, operands); }
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
270 [(set_attr "sync_insn1" "and")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
271 (set_attr "sync_insn2" "xor")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
272 (set_attr "sync_mem" "0")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
273 (set_attr "sync_inclusive_mask" "1")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
274 (set_attr "sync_exclusive_mask" "2")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
275 (set_attr "sync_insn1_op2" "3")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
276 (set_attr "sync_oldval" "4")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
277 (set_attr "sync_newval" "4")])
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
278
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
279 (define_expand "sync_old_nand<mode>"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
280 [(parallel [
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
281 (set (match_operand:SHORT 0 "register_operand")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
282 (match_operand:SHORT 1 "memory_operand"))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
283 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
284 (unspec_volatile:SHORT [(match_dup 1)
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
285 (match_operand:SHORT 2 "general_operand")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
286 UNSPEC_SYNC_OLD_OP))])]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
287 "GENERATE_LL_SC"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
288 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
289 union mips_gen_fn_ptrs generator;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
290 generator.fn_5 = gen_sync_old_nand_12;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
291 mips_expand_atomic_qihi (generator,
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
292 operands[0], operands[1], operands[2], NULL);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
293 DONE;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
294 })
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
295
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
296 ;; Helper insn for sync_old_nand<mode>
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
297 (define_insn "sync_old_nand_12"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
298 [(set (match_operand:SI 0 "register_operand" "=&d")
111
kono
parents: 67
diff changeset
299 (match_operand:SI 1 "memory_operand" "+ZC"))
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
300 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
301 (unspec_volatile:SI
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
302 [(match_operand:SI 2 "register_operand" "d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
303 (match_operand:SI 3 "register_operand" "d")
111
kono
parents: 67
diff changeset
304 (match_operand:SI 4 "reg_or_0_operand" "dJ")]
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
305 UNSPEC_SYNC_OLD_OP_12))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
306 (clobber (match_scratch:SI 5 "=&d"))]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
307 "GENERATE_LL_SC"
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
308 { return mips_output_sync_loop (insn, operands); }
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
309 [(set_attr "sync_insn1" "and")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
310 (set_attr "sync_insn2" "xor")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
311 (set_attr "sync_oldval" "0")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
312 (set_attr "sync_mem" "1")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
313 (set_attr "sync_inclusive_mask" "2")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
314 (set_attr "sync_exclusive_mask" "3")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
315 (set_attr "sync_insn1_op2" "4")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
316 (set_attr "sync_newval" "5")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
317
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
318 (define_expand "sync_new_nand<mode>"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
319 [(parallel [
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
320 (set (match_operand:SHORT 0 "register_operand")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
321 (unspec_volatile:SHORT [(match_operand:SHORT 1 "memory_operand")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
322 (match_operand:SHORT 2 "general_operand")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
323 UNSPEC_SYNC_NEW_OP))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
324 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
325 (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
326 UNSPEC_SYNC_NEW_OP))])]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
327 "GENERATE_LL_SC"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
328 {
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
329 union mips_gen_fn_ptrs generator;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
330 generator.fn_5 = gen_sync_new_nand_12;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
331 mips_expand_atomic_qihi (generator,
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
332 operands[0], operands[1], operands[2], NULL);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
333 DONE;
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
334 })
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
335
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
336 ;; Helper insn for sync_new_nand<mode>
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
337 (define_insn "sync_new_nand_12"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
338 [(set (match_operand:SI 0 "register_operand" "=&d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
339 (unspec_volatile:SI
111
kono
parents: 67
diff changeset
340 [(match_operand:SI 1 "memory_operand" "+ZC")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
341 (match_operand:SI 2 "register_operand" "d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
342 (match_operand:SI 3 "register_operand" "d")
111
kono
parents: 67
diff changeset
343 (match_operand:SI 4 "reg_or_0_operand" "dJ")]
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
344 UNSPEC_SYNC_NEW_OP_12))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
345 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
346 (unspec_volatile:SI
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
347 [(match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
348 (match_dup 2)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
349 (match_dup 3)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
350 (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
351 "GENERATE_LL_SC"
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
352 { return mips_output_sync_loop (insn, operands); }
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
353 [(set_attr "sync_insn1" "and")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
354 (set_attr "sync_insn2" "xor")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
355 (set_attr "sync_oldval" "0")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
356 (set_attr "sync_newval" "0")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
357 (set_attr "sync_mem" "1")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
358 (set_attr "sync_inclusive_mask" "2")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
359 (set_attr "sync_exclusive_mask" "3")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
360 (set_attr "sync_insn1_op2" "4")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
361
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
362 (define_insn "sync_sub<mode>"
111
kono
parents: 67
diff changeset
363 [(set (match_operand:GPR 0 "memory_operand" "+ZC")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
364 (unspec_volatile:GPR
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
365 [(minus:GPR (match_dup 0)
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
366 (match_operand:GPR 1 "register_operand" "d"))]
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
367 UNSPEC_SYNC_OLD_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
368 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
369 { return mips_output_sync_loop (insn, operands); }
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
370 [(set_attr "sync_insn1" "subu")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
371 (set_attr "sync_mem" "0")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
372 (set_attr "sync_insn1_op2" "1")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
373
111
kono
parents: 67
diff changeset
374 ;; Can be removed in favor of atomic_fetch_add below.
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
375 (define_insn "sync_old_add<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
376 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
111
kono
parents: 67
diff changeset
377 (match_operand:GPR 1 "memory_operand" "+ZC,ZC"))
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
378 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
379 (unspec_volatile:GPR
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
380 [(plus:GPR (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
381 (match_operand:GPR 2 "arith_operand" "I,d"))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
382 UNSPEC_SYNC_OLD_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
383 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
384 { return mips_output_sync_loop (insn, operands); }
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
385 [(set_attr "sync_insn1" "addiu,addu")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
386 (set_attr "sync_oldval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
387 (set_attr "sync_mem" "1")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
388 (set_attr "sync_insn1_op2" "2")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
389
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
390 (define_insn "sync_old_sub<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
391 [(set (match_operand:GPR 0 "register_operand" "=&d")
111
kono
parents: 67
diff changeset
392 (match_operand:GPR 1 "memory_operand" "+ZC"))
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
393 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
394 (unspec_volatile:GPR
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
395 [(minus:GPR (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
396 (match_operand:GPR 2 "register_operand" "d"))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
397 UNSPEC_SYNC_OLD_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
398 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
399 { return mips_output_sync_loop (insn, operands); }
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
400 [(set_attr "sync_insn1" "subu")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
401 (set_attr "sync_oldval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
402 (set_attr "sync_mem" "1")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
403 (set_attr "sync_insn1_op2" "2")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
404
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
405 (define_insn "sync_new_add<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
406 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
111
kono
parents: 67
diff changeset
407 (plus:GPR (match_operand:GPR 1 "memory_operand" "+ZC,ZC")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
408 (match_operand:GPR 2 "arith_operand" "I,d")))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
409 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
410 (unspec_volatile:GPR
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
411 [(plus:GPR (match_dup 1) (match_dup 2))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
412 UNSPEC_SYNC_NEW_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
413 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
414 { return mips_output_sync_loop (insn, operands); }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
415 [(set_attr "sync_insn1" "addiu,addu")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
416 (set_attr "sync_oldval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
417 (set_attr "sync_newval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
418 (set_attr "sync_mem" "1")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
419 (set_attr "sync_insn1_op2" "2")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
420
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
421 (define_insn "sync_new_sub<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
422 [(set (match_operand:GPR 0 "register_operand" "=&d")
111
kono
parents: 67
diff changeset
423 (minus:GPR (match_operand:GPR 1 "memory_operand" "+ZC")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
424 (match_operand:GPR 2 "register_operand" "d")))
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
425 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
426 (unspec_volatile:GPR
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
427 [(minus:GPR (match_dup 1) (match_dup 2))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
428 UNSPEC_SYNC_NEW_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
429 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
430 { return mips_output_sync_loop (insn, operands); }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
431 [(set_attr "sync_insn1" "subu")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
432 (set_attr "sync_oldval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
433 (set_attr "sync_newval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
434 (set_attr "sync_mem" "1")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
435 (set_attr "sync_insn1_op2" "2")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
436
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
437 (define_insn "sync_<optab><mode>"
111
kono
parents: 67
diff changeset
438 [(set (match_operand:GPR 0 "memory_operand" "+ZC,ZC")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
439 (unspec_volatile:GPR
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
440 [(fetchop_bit:GPR (match_operand:GPR 1 "uns_arith_operand" "K,d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
441 (match_dup 0))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
442 UNSPEC_SYNC_OLD_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
443 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
444 { return mips_output_sync_loop (insn, operands); }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
445 [(set_attr "sync_insn1" "<immediate_insn>,<insn>")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
446 (set_attr "sync_mem" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
447 (set_attr "sync_insn1_op2" "1")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
448
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
449 (define_insn "sync_old_<optab><mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
450 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
111
kono
parents: 67
diff changeset
451 (match_operand:GPR 1 "memory_operand" "+ZC,ZC"))
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
452 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
453 (unspec_volatile:GPR
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
454 [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
455 (match_dup 1))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
456 UNSPEC_SYNC_OLD_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
457 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
458 { return mips_output_sync_loop (insn, operands); }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
459 [(set_attr "sync_insn1" "<immediate_insn>,<insn>")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
460 (set_attr "sync_oldval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
461 (set_attr "sync_mem" "1")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
462 (set_attr "sync_insn1_op2" "2")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
463
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
464 (define_insn "sync_new_<optab><mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
465 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
111
kono
parents: 67
diff changeset
466 (match_operand:GPR 1 "memory_operand" "+ZC,ZC"))
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
467 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
468 (unspec_volatile:GPR
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
469 [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
470 (match_dup 1))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
471 UNSPEC_SYNC_NEW_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
472 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
473 { return mips_output_sync_loop (insn, operands); }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
474 [(set_attr "sync_insn1" "<immediate_insn>,<insn>")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
475 (set_attr "sync_oldval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
476 (set_attr "sync_newval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
477 (set_attr "sync_mem" "1")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
478 (set_attr "sync_insn1_op2" "2")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
479
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
480 (define_insn "sync_nand<mode>"
111
kono
parents: 67
diff changeset
481 [(set (match_operand:GPR 0 "memory_operand" "+ZC,ZC")
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
482 (unspec_volatile:GPR [(match_operand:GPR 1 "uns_arith_operand" "K,d")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
483 UNSPEC_SYNC_OLD_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
484 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
485 { return mips_output_sync_loop (insn, operands); }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
486 [(set_attr "sync_insn1" "andi,and")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
487 (set_attr "sync_insn2" "not")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
488 (set_attr "sync_mem" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
489 (set_attr "sync_insn1_op2" "1")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
490
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
491 (define_insn "sync_old_nand<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
492 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
111
kono
parents: 67
diff changeset
493 (match_operand:GPR 1 "memory_operand" "+ZC,ZC"))
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
494 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
495 (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
496 UNSPEC_SYNC_OLD_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
497 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
498 { return mips_output_sync_loop (insn, operands); }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
499 [(set_attr "sync_insn1" "andi,and")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
500 (set_attr "sync_insn2" "not")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
501 (set_attr "sync_oldval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
502 (set_attr "sync_mem" "1")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
503 (set_attr "sync_insn1_op2" "2")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
504
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
505 (define_insn "sync_new_nand<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
506 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
111
kono
parents: 67
diff changeset
507 (match_operand:GPR 1 "memory_operand" "+ZC,ZC"))
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
508 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
509 (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
510 UNSPEC_SYNC_NEW_OP))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
511 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
512 { return mips_output_sync_loop (insn, operands); }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
513 [(set_attr "sync_insn1" "andi,and")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
514 (set_attr "sync_insn2" "not")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
515 (set_attr "sync_oldval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
516 (set_attr "sync_newval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
517 (set_attr "sync_mem" "1")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
518 (set_attr "sync_insn1_op2" "2")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
519
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
520 (define_insn "sync_lock_test_and_set<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
521 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
111
kono
parents: 67
diff changeset
522 (match_operand:GPR 1 "memory_operand" "+ZC,ZC"))
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
523 (set (match_dup 1)
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
524 (unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
525 UNSPEC_SYNC_EXCHANGE))]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
526 "GENERATE_LL_SC"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
527 { return mips_output_sync_loop (insn, operands); }
111
kono
parents: 67
diff changeset
528 [(set_attr "sync_memmodel" "11")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
529 (set_attr "sync_insn1" "li,move")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
530 (set_attr "sync_oldval" "0")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
531 (set_attr "sync_mem" "1")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
532 (set_attr "sync_insn1_op2" "2")])
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
533
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
534 (define_expand "sync_lock_test_and_set<mode>"
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
535 [(match_operand:SHORT 0 "register_operand")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
536 (match_operand:SHORT 1 "memory_operand")
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
537 (match_operand:SHORT 2 "general_operand")]
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
538 "GENERATE_LL_SC"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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539 {
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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540 union mips_gen_fn_ptrs generator;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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541 generator.fn_5 = gen_test_and_set_12;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
542 mips_expand_atomic_qihi (generator,
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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543 operands[0], operands[1], operands[2], NULL);
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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544 DONE;
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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545 })
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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546
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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547 (define_insn "test_and_set_12"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
548 [(set (match_operand:SI 0 "register_operand" "=&d")
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549 (match_operand:SI 1 "memory_operand" "+ZC"))
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
550 (set (match_dup 1)
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
551 (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
552 (match_operand:SI 3 "register_operand" "d")
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553 (match_operand:SI 4 "reg_or_0_operand" "dJ")]
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
554 UNSPEC_SYNC_EXCHANGE_12))]
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
555 "GENERATE_LL_SC"
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
556 { return mips_output_sync_loop (insn, operands); }
111
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diff changeset
557 [(set_attr "sync_memmodel" "11")
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
558 (set_attr "sync_oldval" "0")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
559 (set_attr "sync_mem" "1")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
560 ;; Unused, but needed to give the number of operands expected by
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
561 ;; the expander.
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
562 (set_attr "sync_inclusive_mask" "2")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
563 (set_attr "sync_exclusive_mask" "3")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
564 (set_attr "sync_insn1_op2" "4")])
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565
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566 (define_insn "atomic_compare_and_swap<mode>"
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567 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
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568 ;; Logically this unspec is an "eq" operator, but we need to obscure
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569 ;; reads and writes from/to memory with an unspec to prevent
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570 ;; optimizations on shared memory locations. Otherwise, comparison in
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571 ;; { mem = 2; if (atomic_cmp_swap(mem,...) == 2) ...; }
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572 ;; would be optimized away. In addition to that we need to use
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573 ;; unspec_volatile, not just plain unspec -- for the sake of other
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574 ;; threads -- to make sure we don't remove the entirety of the pattern
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575 ;; just because current thread doesn't observe any effect from it.
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576 ;; TODO: the obscuring unspec can be relaxed for permissive memory
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577 ;; models.
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578 ;; Same applies to other atomic_* patterns.
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579 (unspec_volatile:GPR [(match_operand:GPR 2 "memory_operand" "+ZC,ZC")
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580 (match_operand:GPR 3 "reg_or_0_operand" "dJ,dJ")]
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581 UNSPEC_ATOMIC_COMPARE_AND_SWAP))
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582 (set (match_operand:GPR 1 "register_operand" "=&d,&d")
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583 (unspec_volatile:GPR [(match_dup 2)]
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584 UNSPEC_ATOMIC_COMPARE_AND_SWAP))
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585 (set (match_dup 2)
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586 (unspec_volatile:GPR [(match_dup 2)
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587 (match_dup 3)
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588 (match_operand:GPR 4 "arith_operand" "I,d")]
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589 UNSPEC_ATOMIC_COMPARE_AND_SWAP))
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590 (unspec_volatile:GPR [(match_operand:SI 5 "const_int_operand")
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591 (match_operand:SI 6 "const_int_operand")
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592 (match_operand:SI 7 "const_int_operand")]
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593 UNSPEC_ATOMIC_COMPARE_AND_SWAP)]
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594 "GENERATE_LL_SC"
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595 { return mips_output_sync_loop (insn, operands); }
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596 [(set_attr "sync_insn1" "li,move")
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597 (set_attr "sync_oldval" "1")
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598 (set_attr "sync_cmp" "0")
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599 (set_attr "sync_mem" "2")
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600 (set_attr "sync_required_oldval" "3")
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601 (set_attr "sync_insn1_op2" "4")
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602 (set_attr "sync_memmodel" "6")])
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603
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604 (define_expand "atomic_exchange<mode>"
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605 [(match_operand:GPR 0 "register_operand")
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606 (match_operand:GPR 1 "memory_operand")
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607 (match_operand:GPR 2 "arith_operand")
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608 (match_operand:SI 3 "const_int_operand")]
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609 "GENERATE_LL_SC || ISA_HAS_SWAP"
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610 {
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611 if (ISA_HAS_SWAP)
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612 {
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613 if (!mem_noofs_operand (operands[1], <MODE>mode))
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614 {
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615 rtx addr;
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616
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617 addr = force_reg (Pmode, XEXP (operands[1], 0));
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618 operands[1] = replace_equiv_address (operands[1], addr);
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619 }
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620 operands[2] = force_reg (<MODE>mode, operands[2]);
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621 emit_insn (gen_atomic_exchange<mode>_swap (operands[0], operands[1],
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622 operands[2]));
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623 }
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624 else
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625 emit_insn (gen_atomic_exchange<mode>_llsc (operands[0], operands[1],
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626 operands[2], operands[3]));
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627 DONE;
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628 })
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629
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630 (define_insn "atomic_exchange<mode>_llsc"
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631 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
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632 (unspec_volatile:GPR [(match_operand:GPR 1 "memory_operand" "+ZC,ZC")]
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633 UNSPEC_ATOMIC_EXCHANGE))
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diff changeset
634 (set (match_dup 1)
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635 (unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")]
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636 UNSPEC_ATOMIC_EXCHANGE))
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parents: 67
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637 (unspec_volatile:GPR [(match_operand:SI 3 "const_int_operand")]
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638 UNSPEC_ATOMIC_EXCHANGE)]
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639 "GENERATE_LL_SC && !ISA_HAS_SWAP"
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640 { return mips_output_sync_loop (insn, operands); }
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641 [(set_attr "sync_insn1" "li,move")
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642 (set_attr "sync_oldval" "0")
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643 (set_attr "sync_mem" "1")
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644 (set_attr "sync_insn1_op2" "2")
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645 (set_attr "sync_memmodel" "3")])
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646
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647 ;; XLP issues implicit sync for SWAP/LDADD, so no need for an explicit one.
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diff changeset
648 (define_insn "atomic_exchange<mode>_swap"
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649 [(set (match_operand:GPR 0 "register_operand" "=d")
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650 (unspec_volatile:GPR [(match_operand:GPR 1 "mem_noofs_operand" "+ZR")]
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651 UNSPEC_ATOMIC_EXCHANGE))
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diff changeset
652 (set (match_dup 1)
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653 (unspec_volatile:GPR [(match_operand:GPR 2 "register_operand" "0")]
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654 UNSPEC_ATOMIC_EXCHANGE))]
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655 "ISA_HAS_SWAP"
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656 "swap<size>\t%0,%b1"
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657 [(set_attr "type" "atomic")])
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658
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659 (define_expand "atomic_fetch_add<mode>"
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660 [(match_operand:GPR 0 "register_operand")
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661 (match_operand:GPR 1 "memory_operand")
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662 (match_operand:GPR 2 "arith_operand")
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663 (match_operand:SI 3 "const_int_operand")]
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664 "GENERATE_LL_SC || ISA_HAS_LDADD"
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665 {
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666 if (ISA_HAS_LDADD)
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667 {
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668 if (!mem_noofs_operand (operands[1], <MODE>mode))
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669 {
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670 rtx addr;
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671
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672 addr = force_reg (Pmode, XEXP (operands[1], 0));
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673 operands[1] = replace_equiv_address (operands[1], addr);
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674 }
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675 operands[2] = force_reg (<MODE>mode, operands[2]);
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676 emit_insn (gen_atomic_fetch_add<mode>_ldadd (operands[0], operands[1],
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677 operands[2]));
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678 }
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679 else
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680 emit_insn (gen_atomic_fetch_add<mode>_llsc (operands[0], operands[1],
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681 operands[2], operands[3]));
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682 DONE;
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parents: 67
diff changeset
683 })
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684
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685 (define_insn "atomic_fetch_add<mode>_llsc"
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diff changeset
686 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
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parents: 67
diff changeset
687 (unspec_volatile:GPR [(match_operand:GPR 1 "memory_operand" "+ZC,ZC")]
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688 UNSPEC_ATOMIC_FETCH_OP))
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diff changeset
689 (set (match_dup 1)
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690 (unspec_volatile:GPR
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diff changeset
691 [(plus:GPR (match_dup 1)
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692 (match_operand:GPR 2 "arith_operand" "I,d"))]
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693 UNSPEC_ATOMIC_FETCH_OP))
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parents: 67
diff changeset
694 (unspec_volatile:GPR [(match_operand:SI 3 "const_int_operand")]
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695 UNSPEC_ATOMIC_FETCH_OP)]
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diff changeset
696 "GENERATE_LL_SC && !ISA_HAS_LDADD"
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diff changeset
697 { return mips_output_sync_loop (insn, operands); }
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698 [(set_attr "sync_insn1" "addiu,addu")
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699 (set_attr "sync_oldval" "0")
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diff changeset
700 (set_attr "sync_mem" "1")
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701 (set_attr "sync_insn1_op2" "2")
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parents: 67
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702 (set_attr "sync_memmodel" "3")])
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703
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diff changeset
704 ;; XLP issues implicit sync for SWAP/LDADD, so no need for an explicit one.
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diff changeset
705 (define_insn "atomic_fetch_add<mode>_ldadd"
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diff changeset
706 [(set (match_operand:GPR 0 "register_operand" "=d")
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diff changeset
707 (unspec_volatile:GPR [(match_operand:GPR 1 "mem_noofs_operand" "+ZR")]
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708 UNSPEC_ATOMIC_FETCH_OP))
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diff changeset
709 (set (match_dup 1)
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diff changeset
710 (unspec_volatile:GPR
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diff changeset
711 [(plus:GPR (match_dup 1)
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712 (match_operand:GPR 2 "register_operand" "0"))]
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713 UNSPEC_ATOMIC_FETCH_OP))]
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714 "ISA_HAS_LDADD"
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715 "ldadd<size>\t%0,%b1"
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716 [(set_attr "type" "atomic")])