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1 ;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler
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2 ;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
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3 ;; Contributed by Andes Technology Corporation.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21
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22 ;; ------------------------------------------------------------------------
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23 ;; Define N8 pipeline settings.
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24 ;; ------------------------------------------------------------------------
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25
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26 (define_automaton "nds32_n8_machine")
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27
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28 ;; ------------------------------------------------------------------------
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29 ;; Pipeline Stages
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30 ;; ------------------------------------------------------------------------
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31 ;; IF - Instruction Fetch
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32 ;; II - Instruction Issue / Address Generation
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33 ;; EX - Instruction Execution
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34 ;; EXD - Psuedo Stage / Load Data Completion
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35
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36 (define_cpu_unit "n8_ii" "nds32_n8_machine")
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37 (define_cpu_unit "n8_ex" "nds32_n8_machine")
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38
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39 (define_insn_reservation "nds_n8_unknown" 1
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40 (and (eq_attr "type" "unknown")
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41 (eq_attr "pipeline_model" "n8"))
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42 "n8_ii, n8_ex")
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43
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44 (define_insn_reservation "nds_n8_misc" 1
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45 (and (eq_attr "type" "misc")
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46 (eq_attr "pipeline_model" "n8"))
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47 "n8_ii, n8_ex")
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48
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49 (define_insn_reservation "nds_n8_alu" 1
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50 (and (eq_attr "type" "alu")
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51 (eq_attr "pipeline_model" "n8"))
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52 "n8_ii, n8_ex")
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53
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54 (define_insn_reservation "nds_n8_load" 1
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55 (and (match_test "nds32::load_single_p (insn)")
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56 (eq_attr "pipeline_model" "n8"))
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57 "n8_ii, n8_ex")
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58
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59 (define_insn_reservation "nds_n8_store" 1
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60 (and (match_test "nds32::store_single_p (insn)")
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61 (eq_attr "pipeline_model" "n8"))
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62 "n8_ii, n8_ex")
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63
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64 (define_insn_reservation "nds_n8_load_multiple_1" 1
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65 (and (and (eq_attr "type" "load_multiple")
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66 (eq_attr "combo" "1"))
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67 (eq_attr "pipeline_model" "n8"))
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68 "n8_ii, n8_ex")
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69
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70 (define_insn_reservation "nds_n8_load_multiple_2" 1
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71 (and (ior (and (eq_attr "type" "load_multiple")
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72 (eq_attr "combo" "2"))
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73 (match_test "nds32::load_double_p (insn)"))
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74 (eq_attr "pipeline_model" "n8"))
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75 "n8_ii, n8_ii+n8_ex, n8_ex")
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76
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77 (define_insn_reservation "nds_n8_load_multiple_3" 1
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78 (and (and (eq_attr "type" "load_multiple")
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79 (eq_attr "combo" "3"))
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80 (eq_attr "pipeline_model" "n8"))
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81 "n8_ii, (n8_ii+n8_ex)*2, n8_ex")
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82
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83 (define_insn_reservation "nds_n8_load_multiple_4" 1
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84 (and (and (eq_attr "type" "load_multiple")
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85 (eq_attr "combo" "4"))
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86 (eq_attr "pipeline_model" "n8"))
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87 "n8_ii, (n8_ii+n8_ex)*3, n8_ex")
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88
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89 (define_insn_reservation "nds_n8_load_multiple_5" 1
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90 (and (and (eq_attr "type" "load_multiple")
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91 (eq_attr "combo" "5"))
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92 (eq_attr "pipeline_model" "n8"))
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93 "n8_ii, (n8_ii+n8_ex)*4, n8_ex")
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94
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95 (define_insn_reservation "nds_n8_load_multiple_6" 1
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96 (and (and (eq_attr "type" "load_multiple")
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97 (eq_attr "combo" "6"))
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98 (eq_attr "pipeline_model" "n8"))
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99 "n8_ii, (n8_ii+n8_ex)*5, n8_ex")
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100
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101 (define_insn_reservation "nds_n8_load_multiple_7" 1
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102 (and (and (eq_attr "type" "load_multiple")
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103 (eq_attr "combo" "7"))
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104 (eq_attr "pipeline_model" "n8"))
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105 "n8_ii, (n8_ii+n8_ex)*6, n8_ex")
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106
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107 (define_insn_reservation "nds_n8_load_multiple_8" 1
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108 (and (and (eq_attr "type" "load_multiple")
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109 (eq_attr "combo" "8"))
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110 (eq_attr "pipeline_model" "n8"))
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111 "n8_ii, (n8_ii+n8_ex)*7, n8_ex")
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112
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113 (define_insn_reservation "nds_n8_load_multiple_12" 1
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114 (and (and (eq_attr "type" "load_multiple")
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115 (eq_attr "combo" "12"))
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116 (eq_attr "pipeline_model" "n8"))
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117 "n8_ii, (n8_ii+n8_ex)*11, n8_ex")
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118
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119 (define_insn_reservation "nds_n8_store_multiple_1" 1
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120 (and (and (eq_attr "type" "store_multiple")
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121 (eq_attr "combo" "1"))
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122 (eq_attr "pipeline_model" "n8"))
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123 "n8_ii, n8_ex")
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124
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125 (define_insn_reservation "nds_n8_store_multiple_2" 1
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126 (and (ior (and (eq_attr "type" "store_multiple")
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127 (eq_attr "combo" "2"))
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128 (match_test "nds32::store_double_p (insn)"))
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129 (eq_attr "pipeline_model" "n8"))
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130 "n8_ii, n8_ii+n8_ex, n8_ex")
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131
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132 (define_insn_reservation "nds_n8_store_multiple_3" 1
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133 (and (and (eq_attr "type" "store_multiple")
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134 (eq_attr "combo" "3"))
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135 (eq_attr "pipeline_model" "n8"))
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136 "n8_ii, (n8_ii+n8_ex)*2, n8_ex")
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137
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138 (define_insn_reservation "nds_n8_store_multiple_4" 1
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139 (and (and (eq_attr "type" "store_multiple")
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140 (eq_attr "combo" "4"))
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141 (eq_attr "pipeline_model" "n8"))
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142 "n8_ii, (n8_ii+n8_ex)*3, n8_ex")
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143
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144 (define_insn_reservation "nds_n8_store_multiple_5" 1
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145 (and (and (eq_attr "type" "store_multiple")
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146 (eq_attr "combo" "5"))
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147 (eq_attr "pipeline_model" "n8"))
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148 "n8_ii, (n8_ii+n8_ex)*4, n8_ex")
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149
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150 (define_insn_reservation "nds_n8_store_multiple_6" 1
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151 (and (and (eq_attr "type" "store_multiple")
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152 (eq_attr "combo" "6"))
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153 (eq_attr "pipeline_model" "n8"))
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154 "n8_ii, (n8_ii+n8_ex)*5, n8_ex")
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155
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156 (define_insn_reservation "nds_n8_store_multiple_7" 1
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157 (and (and (eq_attr "type" "store_multiple")
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158 (eq_attr "combo" "7"))
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159 (eq_attr "pipeline_model" "n8"))
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160 "n8_ii, (n8_ii+n8_ex)*6, n8_ex")
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161
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162 (define_insn_reservation "nds_n8_store_multiple_8" 1
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163 (and (and (eq_attr "type" "store_multiple")
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164 (eq_attr "combo" "8"))
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165 (eq_attr "pipeline_model" "n8"))
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166 "n8_ii, (n8_ii+n8_ex)*7, n8_ex")
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167
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168 (define_insn_reservation "nds_n8_store_multiple_12" 1
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169 (and (and (eq_attr "type" "store_multiple")
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170 (eq_attr "combo" "12"))
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171 (eq_attr "pipeline_model" "n8"))
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172 "n8_ii, (n8_ii+n8_ex)*11, n8_ex")
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173
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174 (define_insn_reservation "nds_n8_mul_fast" 1
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175 (and (match_test "nds32_mul_config != MUL_TYPE_SLOW")
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176 (and (eq_attr "type" "mul")
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177 (eq_attr "pipeline_model" "n8")))
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178 "n8_ii, n8_ex")
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179
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180 (define_insn_reservation "nds_n8_mul_slow" 1
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181 (and (match_test "nds32_mul_config == MUL_TYPE_SLOW")
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182 (and (eq_attr "type" "mul")
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183 (eq_attr "pipeline_model" "n8")))
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184 "n8_ii, n8_ex*16")
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185
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186 (define_insn_reservation "nds_n8_mac_fast" 1
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187 (and (match_test "nds32_mul_config != MUL_TYPE_SLOW")
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188 (and (eq_attr "type" "mac")
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189 (eq_attr "pipeline_model" "n8")))
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190 "n8_ii, n8_ii+n8_ex, n8_ex")
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191
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192 (define_insn_reservation "nds_n8_mac_slow" 1
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193 (and (match_test "nds32_mul_config == MUL_TYPE_SLOW")
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194 (and (eq_attr "type" "mac")
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195 (eq_attr "pipeline_model" "n8")))
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196 "n8_ii, (n8_ii+n8_ex)*16, n8_ex")
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197
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198 (define_insn_reservation "nds_n8_div" 1
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199 (and (eq_attr "type" "div")
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200 (eq_attr "pipeline_model" "n8"))
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201 "n8_ii, (n8_ii+n8_ex)*36, n8_ex")
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202
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203 (define_insn_reservation "nds_n8_branch" 1
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204 (and (eq_attr "type" "branch")
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205 (eq_attr "pipeline_model" "n8"))
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206 "n8_ii, n8_ex")
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207
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208 ;; ------------------------------------------------------------------------
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209 ;; Comment Notations and Bypass Rules
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210 ;; ------------------------------------------------------------------------
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211 ;; Producers (LHS)
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212 ;; LD_!bi
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213 ;; Load data from the memory (without updating the base register) and
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214 ;; produce the loaded data. The result is ready at EXD.
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215 ;; LD_bi
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216 ;; Load data from the memory (with updating the base register) and
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217 ;; produce the loaded data. The result is ready at EXD. Because the
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218 ;; register port is 2R1W, two micro-operations are required in order
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219 ;; to write two registers. The base register is updated by the second
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220 ;; micro-operation and the result is ready at EX.
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221 ;; LMW(N, M)
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222 ;; There are N micro-operations within an instruction that loads multiple
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223 ;; words. The result produced by the M-th micro-operation is sent to
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224 ;; consumers. The result is ready at EXD. If the base register should be
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225 ;; updated, an extra micro-operation is inserted to the sequence, and the
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226 ;; result is ready at EX.
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227 ;; ADDR_OUT
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228 ;; Most load/store instructions can produce an address output if updating
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229 ;; the base register is required. The result is ready at EX, which is
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230 ;; produced by ALU.
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231 ;; ALU, MUL, MAC
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232 ;; The result is ready at EX.
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233 ;; MOVD44_O
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234 ;; A double-word move instruction needs to write registers twice. Because
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235 ;; the register port is 2R1W, two micro-operations are required. The even
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236 ;; number reigster is updated by the first one, and the odd number register
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237 ;; is updated by the second one. Each of the results is ready at EX.
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238 ;; The letter 'O' stands for odd.
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239 ;; DIV_Rs
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240 ;; A division instruction saves the quotient result to Rt and saves the
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241 ;; remainder result to Rs. It requires two micro-operations because the
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242 ;; register port is 2R1W. The first micro-operation writes to Rt, and
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243 ;; the seconde one writes to Rs. Each of the results is ready at EX.
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244 ;;
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245 ;; Consumers (RHS)
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246 ;; ALU, MUL, DIV
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247 ;; Require operands at EX.
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248 ;; MOVD44_E
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249 ;; The letter 'E' stands for even, which is accessed by the first micro-
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250 ;; operation and a movd44 instruction. The operand is required at EX.
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251 ;; MAC_RaRb
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252 ;; A MAC instruction is separated into two micro-operations. The first
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253 ;; micro-operation does the multiplication, which requires operands Ra
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254 ;; and Rb at EX. The second micro-options does the accumulation, which
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255 ;; requires the operand Rt at EX.
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256 ;; ADDR_IN_MOP(N)
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257 ;; Because the reigster port is 2R1W, some load/store instructions are
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258 ;; separated into many micro-operations. N denotes the address input is
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259 ;; required by the N-th micro-operation. Such operand is required at II.
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260 ;; ST_bi
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261 ;; A post-increment store instruction requires its data at EX.
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262 ;; ST_!bi_RI
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263 ;; A store instruction with an immediate offset requires its data at EX.
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264 ;; If the offset field is a register (ST_!bi_RR), the instruction will be
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265 ;; separated into two micro-operations, and the second one requires the
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266 ;; input operand at EX in order to store it to the memory.
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267 ;; SMW(N, M)
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268 ;; There are N micro-operations within an instruction that stores multiple
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269 ;; words. Each M-th micro-operation requires its data at EX. If the base
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270 ;; register should be updated, an extra micro-operation is inserted to the
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271 ;; sequence.
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272 ;; BR_COND
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273 ;; If a branch instruction is conditional, its input data is required at EX.
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274
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275 ;; LD_!bi -> ADDR_IN_MOP(1)
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276 (define_bypass 3
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277 "nds_n8_load"
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278 "nds_n8_branch,\
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279 nds_n8_load, nds_n8_store,\
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280 nds_n8_load_multiple_1,nds_n8_load_multiple_2, nds_n8_load_multiple_3,\
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281 nds_n8_load_multiple_4,nds_n8_load_multiple_5, nds_n8_load_multiple_6,\
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282 nds_n8_load_multiple_7,nds_n8_load_multiple_8, nds_n8_load_multiple_12,\
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283 nds_n8_store_multiple_1,nds_n8_store_multiple_2, nds_n8_store_multiple_3,\
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284 nds_n8_store_multiple_4,nds_n8_store_multiple_5, nds_n8_store_multiple_6,\
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285 nds_n8_store_multiple_7,nds_n8_store_multiple_8, nds_n8_store_multiple_12"
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286 "nds32_n8_load_to_ii_p"
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287 )
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288
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289 ;; LMW(N, N) -> ADDR_IN_MOP(1)
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290 (define_bypass 3
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291 "nds_n8_load_multiple_1,nds_n8_load_multiple_2, nds_n8_load_multiple_3,\
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292 nds_n8_load_multiple_4,nds_n8_load_multiple_5, nds_n8_load_multiple_6,\
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293 nds_n8_load_multiple_7,nds_n8_load_multiple_8, nds_n8_load_multiple_12"
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294 "nds_n8_branch,\
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295 nds_n8_load, nds_n8_store,\
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296 nds_n8_load_multiple_1,nds_n8_load_multiple_2, nds_n8_load_multiple_3,\
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297 nds_n8_load_multiple_4,nds_n8_load_multiple_5, nds_n8_load_multiple_6,\
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298 nds_n8_load_multiple_7,nds_n8_load_multiple_8, nds_n8_load_multiple_12,\
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299 nds_n8_store_multiple_1,nds_n8_store_multiple_2, nds_n8_store_multiple_3,\
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300 nds_n8_store_multiple_4,nds_n8_store_multiple_5, nds_n8_store_multiple_6,\
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301 nds_n8_store_multiple_7,nds_n8_store_multiple_8, nds_n8_store_multiple_12"
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302 "nds32_n8_last_load_to_ii_p"
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303 )
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304
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305 ;; LMW(N, N - 1) -> ADDR_IN_MOP(1)
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306 (define_bypass 2
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307 "nds_n8_load_multiple_1,nds_n8_load_multiple_2, nds_n8_load_multiple_3,\
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308 nds_n8_load_multiple_4,nds_n8_load_multiple_5, nds_n8_load_multiple_6,\
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309 nds_n8_load_multiple_7,nds_n8_load_multiple_8, nds_n8_load_multiple_12"
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310 "nds_n8_branch,\
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311 nds_n8_load, nds_n8_store,\
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312 nds_n8_load_multiple_1,nds_n8_load_multiple_2, nds_n8_load_multiple_3,\
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313 nds_n8_load_multiple_4,nds_n8_load_multiple_5, nds_n8_load_multiple_6,\
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314 nds_n8_load_multiple_7,nds_n8_load_multiple_8, nds_n8_load_multiple_12,\
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315 nds_n8_store_multiple_1,nds_n8_store_multiple_2, nds_n8_store_multiple_3,\
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316 nds_n8_store_multiple_4,nds_n8_store_multiple_5, nds_n8_store_multiple_6,\
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317 nds_n8_store_multiple_7,nds_n8_store_multiple_8, nds_n8_store_multiple_12"
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318 "nds32_n8_last_load_two_to_ii_p"
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319 )
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320
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321 ;; LD_bi -> ADDR_IN_MOP(1)
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322 (define_bypass 2
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323 "nds_n8_load"
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324 "nds_n8_branch,\
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325 nds_n8_load, nds_n8_store,\
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326 nds_n8_load_multiple_1,nds_n8_load_multiple_2, nds_n8_load_multiple_3,\
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327 nds_n8_load_multiple_4,nds_n8_load_multiple_5, nds_n8_load_multiple_6,\
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328 nds_n8_load_multiple_7,nds_n8_load_multiple_8, nds_n8_load_multiple_12,\
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329 nds_n8_store_multiple_1,nds_n8_store_multiple_2, nds_n8_store_multiple_3,\
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330 nds_n8_store_multiple_4,nds_n8_store_multiple_5, nds_n8_store_multiple_6,\
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331 nds_n8_store_multiple_7,nds_n8_store_multiple_8, nds_n8_store_multiple_12"
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332 "nds32_n8_load_bi_to_ii_p"
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333 )
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334
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335 ;; LD_!bi -> ALU, MOVD44_E, MUL, MAC_RaRb, DIV, BR_COND, ST_bi, ST_!bi_RI, SMW(N, 1)
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336 (define_bypass 2
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337 "nds_n8_load"
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338 "nds_n8_alu,
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339 nds_n8_mul_fast, nds_n8_mul_slow,\
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340 nds_n8_mac_fast, nds_n8_mac_slow,\
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341 nds_n8_div,\
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342 nds_n8_branch,\
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343 nds_n8_store,\
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344 nds_n8_store_multiple_1,nds_n8_store_multiple_2, nds_n8_store_multiple_3,\
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345 nds_n8_store_multiple_4,nds_n8_store_multiple_5, nds_n8_store_multiple_6,\
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346 nds_n8_store_multiple_7,nds_n8_store_multiple_8, nds_n8_store_multiple_12"
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347 "nds32_n8_load_to_ex_p"
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348 )
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349
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350 ;; ALU, MOVD44_O, MUL, MAC, DIV_Rs, LD_bi, ADDR_OUT -> ADDR_IN_MOP(1)
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351 (define_bypass 2
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352 "nds_n8_alu,
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353 nds_n8_mul_fast, nds_n8_mul_slow,\
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354 nds_n8_mac_fast, nds_n8_mac_slow,\
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355 nds_n8_div,\
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356 nds_n8_load, nds_n8_store,\
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357 nds_n8_load_multiple_1,nds_n8_load_multiple_2, nds_n8_load_multiple_3,\
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358 nds_n8_load_multiple_4,nds_n8_load_multiple_5, nds_n8_load_multiple_6,\
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359 nds_n8_load_multiple_7,nds_n8_load_multiple_8, nds_n8_load_multiple_12,\
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360 nds_n8_store_multiple_1,nds_n8_store_multiple_2, nds_n8_store_multiple_3,\
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361 nds_n8_store_multiple_4,nds_n8_store_multiple_5, nds_n8_store_multiple_6,\
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362 nds_n8_store_multiple_7,nds_n8_store_multiple_8, nds_n8_store_multiple_12"
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363 "nds_n8_branch,\
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364 nds_n8_load, nds_n8_store,\
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365 nds_n8_load_multiple_1,nds_n8_load_multiple_2, nds_n8_load_multiple_3,\
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366 nds_n8_load_multiple_4,nds_n8_load_multiple_5, nds_n8_load_multiple_6,\
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367 nds_n8_load_multiple_7,nds_n8_load_multiple_8, nds_n8_load_multiple_12,\
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368 nds_n8_store_multiple_1,nds_n8_store_multiple_2, nds_n8_store_multiple_3,\
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369 nds_n8_store_multiple_4,nds_n8_store_multiple_5, nds_n8_store_multiple_6,\
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370 nds_n8_store_multiple_7,nds_n8_store_multiple_8, nds_n8_store_multiple_12"
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371 "nds32_n8_ex_to_ii_p"
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372 )
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373
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374 ;; LMW(N, N) -> ALU, MOVD44_E, MUL, MAC_RaRb, DIV, BR_COND, ST_bi, ST_!bi_RI, SMW(N, 1)
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375 (define_bypass 2
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376 "nds_n8_load_multiple_1,nds_n8_load_multiple_2, nds_n8_load_multiple_3,\
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377 nds_n8_load_multiple_4,nds_n8_load_multiple_5, nds_n8_load_multiple_6,\
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378 nds_n8_load_multiple_7,nds_n8_load_multiple_8, nds_n8_load_multiple_12"
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379 "nds_n8_alu,
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380 nds_n8_mul_fast, nds_n8_mul_slow,\
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381 nds_n8_mac_fast, nds_n8_mac_slow,\
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382 nds_n8_div,\
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383 nds_n8_branch,\
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384 nds_n8_store,\
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385 nds_n8_store_multiple_1,nds_n8_store_multiple_2, nds_n8_store_multiple_3,\
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386 nds_n8_store_multiple_4,nds_n8_store_multiple_5, nds_n8_store_multiple_6,\
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387 nds_n8_store_multiple_7,nds_n8_store_multiple_8, nds_n8_store_multiple_12"
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388 "nds32_n8_last_load_to_ex_p"
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389 )
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