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annotate gcc/config/powerpcspe/40x.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children
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1 ;; Scheduling description for IBM PowerPC 403 and PowerPC 405 processors.
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84e7813d76e9 gcc-8.2
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2 ;; Copyright (C) 2003-2018 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5
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6 ;; GCC is free software; you can redistribute it and/or modify it
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7 ;; under the terms of the GNU General Public License as published
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8 ;; by the Free Software Foundation; either version 3, or (at your
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9 ;; option) any later version.
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10
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11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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14 ;; License for more details.
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15
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_automaton "ppc40x,ppc40xiu")
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21 (define_cpu_unit "bpu_40x,fpu_405" "ppc40x")
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22 (define_cpu_unit "iu_40x" "ppc40xiu")
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23
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24 ;; PPC401 / PPC403 / PPC405 32-bit integer only IU BPU
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25 ;; Embedded PowerPC controller
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26 ;; In-order execution
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27 ;; Max issue two insns/cycle (includes one branch)
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28 (define_insn_reservation "ppc403-load" 2
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29 (and (eq_attr "type" "load,load_l,store_c,sync")
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30 (eq_attr "cpu" "ppc403,ppc405"))
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31 "iu_40x")
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32
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33 (define_insn_reservation "ppc403-store" 2
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34 (and (eq_attr "type" "store")
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35 (eq_attr "cpu" "ppc403,ppc405"))
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36 "iu_40x")
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37
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38 (define_insn_reservation "ppc403-integer" 1
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39 (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
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40 (and (eq_attr "type" "add,logical,shift,exts")
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41 (eq_attr "dot" "no")))
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42 (eq_attr "cpu" "ppc403,ppc405"))
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43 "iu_40x")
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44
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45 (define_insn_reservation "ppc403-two" 1
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46 (and (eq_attr "type" "two")
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47 (eq_attr "cpu" "ppc403,ppc405"))
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48 "iu_40x,iu_40x")
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49
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50 (define_insn_reservation "ppc403-three" 1
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51 (and (eq_attr "type" "three")
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52 (eq_attr "cpu" "ppc403,ppc405"))
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53 "iu_40x,iu_40x,iu_40x")
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54
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55 (define_insn_reservation "ppc403-compare" 3
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56 (and (ior (eq_attr "type" "cmp")
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57 (and (eq_attr "type" "add,logical,shift,exts")
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58 (eq_attr "dot" "yes")))
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59 (eq_attr "cpu" "ppc403,ppc405"))
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60 "iu_40x,nothing,bpu_40x")
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61
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62 (define_insn_reservation "ppc403-imul" 4
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63 (and (eq_attr "type" "mul")
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64 (eq_attr "cpu" "ppc403"))
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65 "iu_40x*4")
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66
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67 (define_insn_reservation "ppc405-imul" 5
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68 (and (eq_attr "type" "mul")
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69 (eq_attr "size" "32")
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70 (eq_attr "cpu" "ppc405"))
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71 "iu_40x*4")
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72
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73 (define_insn_reservation "ppc405-imul2" 3
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74 (and (eq_attr "type" "mul")
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75 (eq_attr "size" "16")
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76 (eq_attr "cpu" "ppc405"))
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77 "iu_40x*2")
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78
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79 (define_insn_reservation "ppc405-imul3" 2
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80 (and (ior (eq_attr "type" "halfmul")
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81 (and (eq_attr "type" "mul")
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82 (eq_attr "size" "8")))
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83 (eq_attr "cpu" "ppc405"))
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84 "iu_40x")
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85
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86 (define_insn_reservation "ppc403-idiv" 33
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87 (and (eq_attr "type" "div")
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88 (eq_attr "cpu" "ppc403,ppc405"))
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89 "iu_40x*33")
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90
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91 (define_insn_reservation "ppc403-mfcr" 2
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92 (and (eq_attr "type" "mfcr")
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93 (eq_attr "cpu" "ppc403,ppc405"))
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94 "iu_40x")
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95
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96 (define_insn_reservation "ppc403-mtcr" 3
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97 (and (eq_attr "type" "mtcr")
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98 (eq_attr "cpu" "ppc403,ppc405"))
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99 "iu_40x")
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100
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101 (define_insn_reservation "ppc403-mtjmpr" 4
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102 (and (eq_attr "type" "mtjmpr")
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103 (eq_attr "cpu" "ppc403,ppc405"))
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104 "iu_40x")
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105
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106 (define_insn_reservation "ppc403-mfjmpr" 2
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107 (and (eq_attr "type" "mfjmpr")
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108 (eq_attr "cpu" "ppc403,ppc405"))
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109 "iu_40x")
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110
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111 (define_insn_reservation "ppc403-jmpreg" 1
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112 (and (eq_attr "type" "jmpreg,branch,isync")
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113 (eq_attr "cpu" "ppc403,ppc405"))
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114 "bpu_40x")
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115
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116 (define_insn_reservation "ppc403-cr" 2
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117 (and (eq_attr "type" "cr_logical,delayed_cr")
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118 (eq_attr "cpu" "ppc403,ppc405"))
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119 "bpu_40x")
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120
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121 (define_insn_reservation "ppc405-float" 11
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122 (and (eq_attr "type" "fpload,fpstore,fpcompare,fp,fpsimple,dmul,sdiv,ddiv")
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123 (eq_attr "cpu" "ppc405"))
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124 "fpu_405*10")