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annotate gcc/config/powerpcspe/6xx.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 ;; Scheduling description for PowerPC 604, PowerPC 604e, PowerPC 620,
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2 ;; and PowerPC 630 processors.
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84e7813d76e9 gcc-8.2
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3 ;; Copyright (C) 2003-2018 Free Software Foundation, Inc.
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4 ;;
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_automaton "ppc6xx,ppc6xxfp,ppc6xxfp2")
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22 (define_cpu_unit "iu1_6xx,iu2_6xx,mciu_6xx" "ppc6xx")
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23 (define_cpu_unit "fpu_6xx" "ppc6xxfp")
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24 (define_cpu_unit "fpu1_6xx,fpu2_6xx" "ppc6xxfp2")
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25 (define_cpu_unit "lsu_6xx,bpu_6xx,cru_6xx" "ppc6xx")
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26
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27 ;; PPC604 32-bit 2xSCIU, MCIU, LSU, FPU, BPU
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28 ;; PPC604e 32-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
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29 ;; MCIU used for imul/idiv and moves from/to spr
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30 ;; LSU 2 stage pipelined
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31 ;; FPU 3 stage pipelined
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32 ;; Max issue 4 insns/clock cycle
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33
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34 ;; PPC604e is PPC604 with larger caches and a CRU. In the 604
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35 ;; the CR logical operations are handled in the BPU.
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36 ;; In the 604e, the CRU shares bus with BPU so only one condition
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37 ;; register or branch insn can be issued per clock. Not modelled.
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38
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39 ;; PPC620 64-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
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40 ;; PPC630 64-bit 2xSCIU, MCIU, LSU, 2xFPU, BPU, CRU
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41 ;; Max issue 4 insns/clock cycle
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42 ;; Out-of-order execution, in-order completion
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43
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44 ;; No following instruction can dispatch in the same cycle as a branch
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45 ;; instruction. Not modelled. This is no problem if RCSP is not
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46 ;; enabled since the scheduler stops a schedule when it gets to a branch.
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47
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48 ;; Four insns can be dispatched per cycle.
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49
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50 (define_insn_reservation "ppc604-load" 2
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51 (and (eq_attr "type" "load")
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52 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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53 "lsu_6xx")
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54
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55 (define_insn_reservation "ppc604-fpload" 3
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56 (and (eq_attr "type" "fpload")
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57 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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58 "lsu_6xx")
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59
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60 (define_insn_reservation "ppc604-store" 3
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61 (and (eq_attr "type" "store,fpstore")
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62 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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63 "lsu_6xx")
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64
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65 (define_insn_reservation "ppc604-llsc" 3
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66 (and (eq_attr "type" "load_l,store_c")
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67 (eq_attr "cpu" "ppc604,ppc604e"))
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68 "lsu_6xx")
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69
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70 (define_insn_reservation "ppc630-llsc" 4
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71 (and (eq_attr "type" "load_l,store_c")
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72 (eq_attr "cpu" "ppc620,ppc630"))
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73 "lsu_6xx")
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74
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75 (define_insn_reservation "ppc604-integer" 1
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76 (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
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77 (and (eq_attr "type" "add,logical,shift,exts")
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78 (eq_attr "dot" "no")))
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79 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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80 "iu1_6xx|iu2_6xx")
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81
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82 (define_insn_reservation "ppc604-two" 1
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83 (and (eq_attr "type" "two")
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84 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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85 "iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
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86
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87 (define_insn_reservation "ppc604-three" 1
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88 (and (eq_attr "type" "three")
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89 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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90 "iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
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91
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92 (define_insn_reservation "ppc604-imul" 4
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93 (and (eq_attr "type" "mul")
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94 (eq_attr "cpu" "ppc604"))
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95 "mciu_6xx*2")
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96
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97 (define_insn_reservation "ppc604e-imul" 2
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98 (and (eq_attr "type" "mul")
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99 (eq_attr "cpu" "ppc604e"))
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100 "mciu_6xx")
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101
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102 (define_insn_reservation "ppc620-imul" 5
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103 (and (eq_attr "type" "mul")
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104 (eq_attr "size" "32")
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105 (eq_attr "cpu" "ppc620,ppc630"))
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106 "mciu_6xx*3")
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107
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108 (define_insn_reservation "ppc620-imul2" 4
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109 (and (eq_attr "type" "mul")
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110 (eq_attr "size" "16")
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111 (eq_attr "cpu" "ppc620,ppc630"))
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112 "mciu_6xx*3")
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113
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114 (define_insn_reservation "ppc620-imul3" 3
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115 (and (eq_attr "type" "mul")
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116 (eq_attr "size" "8")
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117 (eq_attr "cpu" "ppc620,ppc630"))
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118 "mciu_6xx*3")
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119
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120 (define_insn_reservation "ppc620-lmul" 7
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121 (and (eq_attr "type" "mul")
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122 (eq_attr "size" "64")
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123 (eq_attr "cpu" "ppc620,ppc630"))
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124 "mciu_6xx*5")
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125
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126 (define_insn_reservation "ppc604-idiv" 20
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127 (and (eq_attr "type" "div")
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128 (eq_attr "cpu" "ppc604,ppc604e"))
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129 "mciu_6xx*19")
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130
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131 (define_insn_reservation "ppc620-idiv" 37
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132 (and (eq_attr "type" "div")
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133 (eq_attr "size" "32")
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134 (eq_attr "cpu" "ppc620"))
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135 "mciu_6xx*36")
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136
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137 (define_insn_reservation "ppc630-idiv" 21
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138 (and (eq_attr "type" "div")
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139 (eq_attr "size" "32")
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140 (eq_attr "cpu" "ppc630"))
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141 "mciu_6xx*20")
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142
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143 (define_insn_reservation "ppc620-ldiv" 37
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144 (and (eq_attr "type" "div")
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145 (eq_attr "size" "64")
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146 (eq_attr "cpu" "ppc620,ppc630"))
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147 "mciu_6xx*36")
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148
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149 (define_insn_reservation "ppc604-compare" 3
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150 (and (ior (eq_attr "type" "cmp")
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151 (and (eq_attr "type" "add,logical,shift,exts")
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152 (eq_attr "dot" "yes")))
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153 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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154 "(iu1_6xx|iu2_6xx)")
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155
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156 ; FPU PPC604{,e},PPC620
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157 (define_insn_reservation "ppc604-fpcompare" 5
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158 (and (eq_attr "type" "fpcompare")
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159 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
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160 "fpu_6xx")
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161
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162 (define_insn_reservation "ppc604-fp" 3
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163 (and (eq_attr "type" "fp,fpsimple")
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164 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
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165 "fpu_6xx")
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166
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167 (define_insn_reservation "ppc604-dmul" 3
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168 (and (eq_attr "type" "dmul")
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169 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
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170 "fpu_6xx")
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171
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172 ; Divides are not pipelined
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173 (define_insn_reservation "ppc604-sdiv" 18
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174 (and (eq_attr "type" "sdiv")
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175 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
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176 "fpu_6xx*18")
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177
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178 (define_insn_reservation "ppc604-ddiv" 32
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179 (and (eq_attr "type" "ddiv")
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180 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
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181 "fpu_6xx*32")
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182
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183 (define_insn_reservation "ppc620-ssqrt" 31
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184 (and (eq_attr "type" "ssqrt")
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185 (eq_attr "cpu" "ppc620"))
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186 "fpu_6xx*31")
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187
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188 (define_insn_reservation "ppc620-dsqrt" 31
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189 (and (eq_attr "type" "dsqrt")
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190 (eq_attr "cpu" "ppc620"))
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191 "fpu_6xx*31")
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192
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193
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194 ; 2xFPU PPC630
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195 (define_insn_reservation "ppc630-fpcompare" 5
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196 (and (eq_attr "type" "fpcompare")
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197 (eq_attr "cpu" "ppc630"))
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198 "fpu1_6xx|fpu2_6xx")
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199
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200 (define_insn_reservation "ppc630-fp" 3
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201 (and (eq_attr "type" "fp,dmul")
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202 (eq_attr "cpu" "ppc630"))
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203 "fpu1_6xx|fpu2_6xx")
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204
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205 (define_insn_reservation "ppc630-sdiv" 17
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206 (and (eq_attr "type" "sdiv")
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207 (eq_attr "cpu" "ppc630"))
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208 "fpu1_6xx*17|fpu2_6xx*17")
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209
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210 (define_insn_reservation "ppc630-ddiv" 21
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211 (and (eq_attr "type" "ddiv")
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212 (eq_attr "cpu" "ppc630"))
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213 "fpu1_6xx*21|fpu2_6xx*21")
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214
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215 (define_insn_reservation "ppc630-ssqrt" 18
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216 (and (eq_attr "type" "ssqrt")
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217 (eq_attr "cpu" "ppc630"))
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218 "fpu1_6xx*18|fpu2_6xx*18")
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219
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220 (define_insn_reservation "ppc630-dsqrt" 25
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221 (and (eq_attr "type" "dsqrt")
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222 (eq_attr "cpu" "ppc630"))
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223 "fpu1_6xx*25|fpu2_6xx*25")
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224
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225 (define_insn_reservation "ppc604-mfcr" 3
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226 (and (eq_attr "type" "mfcr")
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227 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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228 "mciu_6xx")
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229
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230 (define_insn_reservation "ppc604-mtcr" 2
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231 (and (eq_attr "type" "mtcr")
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232 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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233 "iu1_6xx|iu2_6xx")
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234
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235 (define_insn_reservation "ppc604-crlogical" 2
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236 (and (eq_attr "type" "cr_logical,delayed_cr")
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237 (eq_attr "cpu" "ppc604"))
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parents:
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238 "bpu_6xx")
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239
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240 (define_insn_reservation "ppc604e-crlogical" 2
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241 (and (eq_attr "type" "cr_logical,delayed_cr")
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242 (eq_attr "cpu" "ppc604e,ppc620,ppc630"))
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parents:
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243 "cru_6xx")
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244
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245 (define_insn_reservation "ppc604-mtjmpr" 2
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246 (and (eq_attr "type" "mtjmpr")
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247 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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248 "mciu_6xx")
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249
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250 (define_insn_reservation "ppc604-mfjmpr" 3
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251 (and (eq_attr "type" "mfjmpr")
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252 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
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253 "mciu_6xx")
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254
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255 (define_insn_reservation "ppc630-mfjmpr" 2
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256 (and (eq_attr "type" "mfjmpr")
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257 (eq_attr "cpu" "ppc630"))
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258 "mciu_6xx")
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259
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260 (define_insn_reservation "ppc604-jmpreg" 1
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261 (and (eq_attr "type" "jmpreg,branch")
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262 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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263 "bpu_6xx")
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264
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265 (define_insn_reservation "ppc604-isync" 0
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266 (and (eq_attr "type" "isync")
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267 (eq_attr "cpu" "ppc604,ppc604e"))
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268 "bpu_6xx")
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269
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270 (define_insn_reservation "ppc630-isync" 6
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271 (and (eq_attr "type" "isync")
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272 (eq_attr "cpu" "ppc620,ppc630"))
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273 "bpu_6xx")
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274
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275 (define_insn_reservation "ppc604-sync" 35
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276 (and (eq_attr "type" "sync")
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277 (eq_attr "cpu" "ppc604,ppc604e"))
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278 "lsu_6xx")
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279
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280 (define_insn_reservation "ppc630-sync" 26
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281 (and (eq_attr "type" "sync")
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282 (eq_attr "cpu" "ppc620,ppc630"))
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283 "lsu_6xx")
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284