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1 ;; Pipeline description for Motorola PowerPC e300c3 core.
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2 ;; Copyright (C) 2008-2018 Free Software Foundation, Inc.
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3 ;; Contributed by Edmar Wienskoski (edmar@freescale.com)
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_automaton "ppce300c3_most,ppce300c3_long,ppce300c3_retire")
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22 (define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most")
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23
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24 ;; We don't simulate general issue queue (GIC). If we have SU insn
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25 ;; and then SU1 insn, they can not be issued on the same cycle
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26 ;; (although SU1 insn and then SU insn can be issued) because the SU
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27 ;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle
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28 ;; multipass insn scheduling will find the situation and issue the SU1
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29 ;; insn and then the SU insn.
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30 (define_cpu_unit "ppce300c3_issue_0,ppce300c3_issue_1" "ppce300c3_most")
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31
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32 ;; We could describe completion buffers slots in combination with the
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33 ;; retirement units and the order of completion but the result
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34 ;; automaton would behave in the same way because we can not describe
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35 ;; real latency time with taking in order completion into account.
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36 ;; Actually we could define the real latency time by querying reserved
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37 ;; automaton units but the current scheduler uses latency time before
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38 ;; issuing insns and making any reservations.
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39 ;;
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40 ;; So our description is aimed to achieve a insn schedule in which the
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41 ;; insns would not wait in the completion buffer.
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42 (define_cpu_unit "ppce300c3_retire_0,ppce300c3_retire_1" "ppce300c3_retire")
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43
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44 ;; Branch unit:
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45 (define_cpu_unit "ppce300c3_bu" "ppce300c3_most")
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46
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47 ;; IU:
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48 (define_cpu_unit "ppce300c3_iu0_stage0,ppce300c3_iu1_stage0" "ppce300c3_most")
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49
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50 ;; IU: This used to describe non-pipelined division.
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51 (define_cpu_unit "ppce300c3_mu_div" "ppce300c3_long")
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52
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53 ;; SRU:
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54 (define_cpu_unit "ppce300c3_sru_stage0" "ppce300c3_most")
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55
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56 ;; Here we simplified LSU unit description not describing the stages.
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57 (define_cpu_unit "ppce300c3_lsu" "ppce300c3_most")
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58
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59 ;; FPU:
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60 (define_cpu_unit "ppce300c3_fpu" "ppce300c3_most")
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61
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62 ;; The following units are used to make automata deterministic
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63 (define_cpu_unit "present_ppce300c3_decode_0" "ppce300c3_most")
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64 (define_cpu_unit "present_ppce300c3_issue_0" "ppce300c3_most")
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65 (define_cpu_unit "present_ppce300c3_retire_0" "ppce300c3_retire")
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66 (define_cpu_unit "present_ppce300c3_iu0_stage0" "ppce300c3_most")
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67
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68 ;; The following sets to make automata deterministic when option ndfa is used.
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69 (presence_set "present_ppce300c3_decode_0" "ppce300c3_decode_0")
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70 (presence_set "present_ppce300c3_issue_0" "ppce300c3_issue_0")
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71 (presence_set "present_ppce300c3_retire_0" "ppce300c3_retire_0")
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72 (presence_set "present_ppce300c3_iu0_stage0" "ppce300c3_iu0_stage0")
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73
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74 ;; Some useful abbreviations.
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75 (define_reservation "ppce300c3_decode"
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76 "ppce300c3_decode_0|ppce300c3_decode_1+present_ppce300c3_decode_0")
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77 (define_reservation "ppce300c3_issue"
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78 "ppce300c3_issue_0|ppce300c3_issue_1+present_ppce300c3_issue_0")
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79 (define_reservation "ppce300c3_retire"
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80 "ppce300c3_retire_0|ppce300c3_retire_1+present_ppce300c3_retire_0")
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81 (define_reservation "ppce300c3_iu_stage0"
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82 "ppce300c3_iu0_stage0|ppce300c3_iu1_stage0+present_ppce300c3_iu0_stage0")
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83
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84 ;; Compares can be executed either one of the IU or SRU
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85 (define_insn_reservation "ppce300c3_cmp" 1
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86 (and (ior (eq_attr "type" "cmp")
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87 (and (eq_attr "type" "add,logical,shift,exts")
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88 (eq_attr "dot" "yes")))
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89 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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90 "ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
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91 +ppce300c3_retire")
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92
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93 ;; Other one cycle IU insns
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94 (define_insn_reservation "ppce300c3_iu" 1
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95 (and (ior (eq_attr "type" "integer,insert,isel")
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96 (and (eq_attr "type" "add,logical,shift,exts")
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97 (eq_attr "dot" "no")))
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98 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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99 "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
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100
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101 ;; Branch. Actually this latency time is not used by the scheduler.
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102 (define_insn_reservation "ppce300c3_branch" 1
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103 (and (eq_attr "type" "jmpreg,branch")
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104 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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105 "ppce300c3_decode,ppce300c3_bu,ppce300c3_retire")
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106
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107 ;; Multiply is non-pipelined but can be executed in any IU
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108 (define_insn_reservation "ppce300c3_multiply" 2
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109 (and (eq_attr "type" "mul")
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110 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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111 "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \
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112 ppce300c3_iu_stage0+ppce300c3_retire")
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113
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114 ;; Divide. We use the average latency time here. We omit reserving a
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115 ;; retire unit because of the result automata will be huge.
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116 (define_insn_reservation "ppce300c3_divide" 20
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117 (and (eq_attr "type" "div")
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118 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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119 "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\
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120 ppce300c3_mu_div*19")
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121
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122 ;; CR logical
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123 (define_insn_reservation "ppce300c3_cr_logical" 1
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124 (and (eq_attr "type" "cr_logical,delayed_cr")
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125 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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126 "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
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127
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128 ;; Mfcr
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129 (define_insn_reservation "ppce300c3_mfcr" 1
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130 (and (eq_attr "type" "mfcr")
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131 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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132 "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
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133
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134 ;; Mtcrf
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135 (define_insn_reservation "ppce300c3_mtcrf" 1
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136 (and (eq_attr "type" "mtcr")
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137 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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138 "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
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139
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140 ;; Mtjmpr
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141 (define_insn_reservation "ppce300c3_mtjmpr" 1
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142 (and (eq_attr "type" "mtjmpr,mfjmpr")
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143 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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144 "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
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145
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146 ;; Float point instructions
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147 (define_insn_reservation "ppce300c3_fpcompare" 3
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148 (and (eq_attr "type" "fpcompare")
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149 (eq_attr "cpu" "ppce300c3"))
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150 "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
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151
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152 (define_insn_reservation "ppce300c3_fp" 3
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153 (and (eq_attr "type" "fp,fpsimple")
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154 (eq_attr "cpu" "ppce300c3"))
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155 "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
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156
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157 (define_insn_reservation "ppce300c3_dmul" 4
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158 (and (eq_attr "type" "dmul")
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159 (eq_attr "cpu" "ppce300c3"))
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160 "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu,nothing,ppce300c3_retire")
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161
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162 ; Divides are not pipelined
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163 (define_insn_reservation "ppce300c3_sdiv" 18
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164 (and (eq_attr "type" "sdiv")
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165 (eq_attr "cpu" "ppce300c3"))
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166 "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*17")
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167
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168 (define_insn_reservation "ppce300c3_ddiv" 33
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169 (and (eq_attr "type" "ddiv")
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170 (eq_attr "cpu" "ppce300c3"))
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171 "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*32")
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172
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173 ;; Loads
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174 (define_insn_reservation "ppce300c3_load" 2
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175 (and (eq_attr "type" "load")
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176 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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177 "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
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178
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179 (define_insn_reservation "ppce300c3_fpload" 2
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180 (and (eq_attr "type" "fpload")
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181 (eq_attr "cpu" "ppce300c3"))
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182 "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
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183
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184 ;; Stores.
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185 (define_insn_reservation "ppce300c3_store" 2
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186 (and (eq_attr "type" "store")
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187 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
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188 "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
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189
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190 (define_insn_reservation "ppce300c3_fpstore" 2
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191 (and (eq_attr "type" "fpstore")
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192 (eq_attr "cpu" "ppce300c3"))
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193 "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
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