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annotate gcc/config/powerpcspe/e6500.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children
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1 ;; Pipeline description for Freescale PowerPC e6500 core.
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84e7813d76e9 gcc-8.2
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2 ;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
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3 ;; Contributed by Edmar Wienskoski (edmar@freescale.com)
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20 ;;
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21 ;; e6500 64-bit SFX(2), CFX, LSU, FPU, BU, VSFX, VCFX, VFPU, VPERM
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22 ;; Max issue 3 insns/clock cycle (includes 1 branch)
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23
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24 (define_automaton "e6500_most,e6500_long,e6500_vec")
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25 (define_cpu_unit "e6500_decode_0,e6500_decode_1" "e6500_most")
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26
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27 ;; SFX.
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28 (define_cpu_unit "e6500_sfx_0,e6500_sfx_1" "e6500_most")
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29
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30 ;; CFX.
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31 (define_cpu_unit "e6500_cfx_stage0,e6500_cfx_stage1" "e6500_most")
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32
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33 ;; Non-pipelined division.
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34 (define_cpu_unit "e6500_cfx_div" "e6500_long")
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35
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36 ;; LSU.
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37 (define_cpu_unit "e6500_lsu" "e6500_most")
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38
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39 ;; FPU.
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40 (define_cpu_unit "e6500_fpu" "e6500_long")
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41
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42 ;; BU.
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43 (define_cpu_unit "e6500_bu" "e6500_most")
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44
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45 ;; Altivec unit
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46 (define_cpu_unit "e6500_vec,e6500_vecperm" "e6500_vec")
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47
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48 ;; The following units are used to make the automata deterministic.
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49 (define_cpu_unit "present_e6500_decode_0" "e6500_most")
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50 (define_cpu_unit "present_e6500_sfx_0" "e6500_most")
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51 (presence_set "present_e6500_decode_0" "e6500_decode_0")
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52 (presence_set "present_e6500_sfx_0" "e6500_sfx_0")
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53
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54 ;; Some useful abbreviations.
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55 (define_reservation "e6500_decode"
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56 "e6500_decode_0|e6500_decode_1+present_e6500_decode_0")
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57 (define_reservation "e6500_sfx"
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58 "e6500_sfx_0|e6500_sfx_1+present_e6500_sfx_0")
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59
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60 ;; SFX.
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61 (define_insn_reservation "e6500_sfx" 1
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62 (and (ior (eq_attr "type" "integer,insert,cntlz")
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63 (and (eq_attr "type" "add,logical,exts")
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64 (eq_attr "dot" "no"))
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65 (and (eq_attr "type" "shift")
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66 (eq_attr "dot" "no")
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67 (eq_attr "var_shift" "no")))
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68 (eq_attr "cpu" "ppce6500"))
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69 "e6500_decode,e6500_sfx")
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70
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71 (define_insn_reservation "e6500_sfx2" 2
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72 (and (ior (eq_attr "type" "cmp,trap")
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73 (and (eq_attr "type" "add,logical,exts")
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74 (eq_attr "dot" "yes"))
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75 (and (eq_attr "type" "shift")
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76 (eq_attr "dot" "yes")
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77 (eq_attr "var_shift" "no")))
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78 (eq_attr "cpu" "ppce6500"))
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79 "e6500_decode,e6500_sfx")
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80
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81 (define_insn_reservation "e6500_delayed" 2
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82 (and (eq_attr "type" "shift")
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83 (eq_attr "var_shift" "yes")
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84 (eq_attr "cpu" "ppce6500"))
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85 "e6500_decode,e6500_sfx*2")
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86
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87 (define_insn_reservation "e6500_two" 2
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88 (and (eq_attr "type" "two")
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89 (eq_attr "cpu" "ppce6500"))
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90 "e6500_decode,e6500_decode+e6500_sfx,e6500_sfx")
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91
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92 (define_insn_reservation "e6500_three" 3
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93 (and (eq_attr "type" "three")
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94 (eq_attr "cpu" "ppce6500"))
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95 "e6500_decode,(e6500_decode+e6500_sfx)*2,e6500_sfx")
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96
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97 ;; SFX - Mfcr.
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98 (define_insn_reservation "e6500_mfcr" 4
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99 (and (eq_attr "type" "mfcr")
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100 (eq_attr "cpu" "ppce6500"))
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101 "e6500_decode,e6500_sfx_0*4")
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102
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103 ;; SFX - Mtcrf.
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104 (define_insn_reservation "e6500_mtcrf" 1
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105 (and (eq_attr "type" "mtcr")
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106 (eq_attr "cpu" "ppce6500"))
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107 "e6500_decode,e6500_sfx_0")
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108
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109 ;; SFX - Mtjmpr.
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110 (define_insn_reservation "e6500_mtjmpr" 1
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111 (and (eq_attr "type" "mtjmpr,mfjmpr")
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112 (eq_attr "cpu" "ppce6500"))
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113 "e6500_decode,e6500_sfx")
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114
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115 ;; CFX - Multiply.
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116 (define_insn_reservation "e6500_multiply" 4
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117 (and (eq_attr "type" "mul")
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118 (eq_attr "dot" "no")
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119 (eq_attr "size" "32")
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120 (eq_attr "cpu" "ppce6500"))
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121 "e6500_decode,e6500_cfx_stage0,e6500_cfx_stage1")
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122
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123 (define_insn_reservation "e6500_multiply_i" 5
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124 (and (eq_attr "type" "mul")
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125 (ior (eq_attr "dot" "yes")
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126 (eq_attr "size" "8,16"))
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127 (eq_attr "cpu" "ppce6500"))
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128 "e6500_decode,e6500_cfx_stage0,\
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129 e6500_cfx_stage0+e6500_cfx_stage1,e6500_cfx_stage1")
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130
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131 ;; CFX - Divide.
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132 (define_insn_reservation "e6500_divide" 16
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133 (and (eq_attr "type" "div")
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134 (eq_attr "size" "32")
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135 (eq_attr "cpu" "ppce6500"))
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136 "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
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137 e6500_cfx_div*15")
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138
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139 (define_insn_reservation "e6500_divide_d" 26
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140 (and (eq_attr "type" "div")
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141 (eq_attr "size" "64")
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142 (eq_attr "cpu" "ppce6500"))
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143 "e6500_decode,e6500_cfx_stage0+e6500_cfx_div,\
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144 e6500_cfx_div*25")
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145
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146 ;; LSU - Loads.
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147 (define_insn_reservation "e6500_load" 3
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148 (and (eq_attr "type" "load,load_l,sync")
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149 (eq_attr "cpu" "ppce6500"))
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150 "e6500_decode,e6500_lsu")
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151
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152 (define_insn_reservation "e6500_fpload" 4
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153 (and (eq_attr "type" "fpload")
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154 (eq_attr "cpu" "ppce6500"))
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155 "e6500_decode,e6500_lsu")
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156
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157 (define_insn_reservation "e6500_vecload" 4
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158 (and (eq_attr "type" "vecload")
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159 (eq_attr "cpu" "ppce6500"))
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160 "e6500_decode,e6500_lsu")
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161
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162 ;; LSU - Stores.
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163 (define_insn_reservation "e6500_store" 3
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164 (and (eq_attr "type" "store,store_c")
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165 (eq_attr "cpu" "ppce6500"))
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166 "e6500_decode,e6500_lsu")
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167
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168 (define_insn_reservation "e6500_fpstore" 3
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169 (and (eq_attr "type" "fpstore")
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170 (eq_attr "cpu" "ppce6500"))
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171 "e6500_decode,e6500_lsu")
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172
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173 (define_insn_reservation "e6500_vecstore" 4
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174 (and (eq_attr "type" "vecstore")
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175 (eq_attr "cpu" "ppce6500"))
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176 "e6500_decode,e6500_lsu")
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177
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178 ;; FP.
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179 (define_insn_reservation "e6500_float" 7
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180 (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
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181 (eq_attr "cpu" "ppce6500"))
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182 "e6500_decode,e6500_fpu")
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183
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184 (define_insn_reservation "e6500_sdiv" 20
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185 (and (eq_attr "type" "sdiv")
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186 (eq_attr "cpu" "ppce6500"))
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187 "e6500_decode,e6500_fpu*20")
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188
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189 (define_insn_reservation "e6500_ddiv" 35
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190 (and (eq_attr "type" "ddiv")
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191 (eq_attr "cpu" "ppce6500"))
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192 "e6500_decode,e6500_fpu*35")
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193
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194 ;; BU.
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195 (define_insn_reservation "e6500_branch" 1
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196 (and (eq_attr "type" "jmpreg,branch,isync")
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197 (eq_attr "cpu" "ppce6500"))
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198 "e6500_decode,e6500_bu")
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199
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200 ;; BU - CR logical.
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201 (define_insn_reservation "e6500_cr_logical" 1
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202 (and (eq_attr "type" "cr_logical,delayed_cr")
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203 (eq_attr "cpu" "ppce6500"))
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204 "e6500_decode,e6500_bu")
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205
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206 ;; VSFX.
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207 (define_insn_reservation "e6500_vecsimple" 1
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208 (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx")
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209 (eq_attr "cpu" "ppce6500"))
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210 "e6500_decode,e6500_vec")
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211
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212 ;; VCFX.
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213 (define_insn_reservation "e6500_veccomplex" 4
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214 (and (eq_attr "type" "veccomplex")
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215 (eq_attr "cpu" "ppce6500"))
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216 "e6500_decode,e6500_vec")
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217
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218 ;; VFPU.
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219 (define_insn_reservation "e6500_vecfloat" 6
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220 (and (eq_attr "type" "vecfloat")
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221 (eq_attr "cpu" "ppce6500"))
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222 "e6500_decode,e6500_vec")
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223
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224 ;; VPERM.
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225 (define_insn_reservation "e6500_vecperm" 2
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226 (and (eq_attr "type" "vecperm")
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227 (eq_attr "cpu" "ppce6500"))
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228 "e6500_decode,e6500_vecperm")