|
111
|
1 ;; Constraint definitions for RISC-V target.
|
|
131
|
2 ;; Copyright (C) 2011-2018 Free Software Foundation, Inc.
|
|
111
|
3 ;; Contributed by Andrew Waterman (andrew@sifive.com).
|
|
|
4 ;; Based on MIPS target for GNU compiler.
|
|
|
5 ;;
|
|
|
6 ;; This file is part of GCC.
|
|
|
7 ;;
|
|
|
8 ;; GCC is free software; you can redistribute it and/or modify
|
|
|
9 ;; it under the terms of the GNU General Public License as published by
|
|
|
10 ;; the Free Software Foundation; either version 3, or (at your option)
|
|
|
11 ;; any later version.
|
|
|
12 ;;
|
|
|
13 ;; GCC is distributed in the hope that it will be useful,
|
|
|
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
16 ;; GNU General Public License for more details.
|
|
|
17 ;;
|
|
|
18 ;; You should have received a copy of the GNU General Public License
|
|
|
19 ;; along with GCC; see the file COPYING3. If not see
|
|
|
20 ;; <http://www.gnu.org/licenses/>.
|
|
|
21
|
|
|
22 ;; Register constraints
|
|
|
23
|
|
|
24 (define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
|
|
|
25 "A floating-point register (if available).")
|
|
|
26
|
|
|
27 (define_register_constraint "j" "SIBCALL_REGS"
|
|
|
28 "@internal")
|
|
|
29
|
|
|
30 ;; Avoid using register t0 for JALR's argument, because for some
|
|
|
31 ;; microarchitectures that is a return-address stack hint.
|
|
|
32 (define_register_constraint "l" "JALR_REGS"
|
|
|
33 "@internal")
|
|
|
34
|
|
|
35 ;; General constraints
|
|
|
36
|
|
|
37 (define_constraint "I"
|
|
|
38 "An I-type 12-bit signed immediate."
|
|
|
39 (and (match_code "const_int")
|
|
|
40 (match_test "SMALL_OPERAND (ival)")))
|
|
|
41
|
|
|
42 (define_constraint "J"
|
|
|
43 "Integer zero."
|
|
|
44 (and (match_code "const_int")
|
|
|
45 (match_test "ival == 0")))
|
|
|
46
|
|
|
47 (define_constraint "K"
|
|
|
48 "A 5-bit unsigned immediate for CSR access instructions."
|
|
|
49 (and (match_code "const_int")
|
|
|
50 (match_test "IN_RANGE (ival, 0, 31)")))
|
|
|
51
|
|
|
52 ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
|
|
|
53 ;; not available in RV32.
|
|
|
54 (define_constraint "G"
|
|
|
55 "@internal"
|
|
|
56 (and (match_code "const_double")
|
|
|
57 (match_test "op == CONST0_RTX (mode)")))
|
|
|
58
|
|
|
59 (define_memory_constraint "A"
|
|
|
60 "An address that is held in a general-purpose register."
|
|
|
61 (and (match_code "mem")
|
|
|
62 (match_test "GET_CODE(XEXP(op,0)) == REG")))
|
|
|
63
|
|
|
64 (define_constraint "S"
|
|
|
65 "@internal
|
|
|
66 A constant call address."
|
|
|
67 (match_operand 0 "absolute_symbolic_operand"))
|
|
|
68
|
|
|
69 (define_constraint "U"
|
|
|
70 "@internal
|
|
|
71 A PLT-indirect call address."
|
|
|
72 (match_operand 0 "plt_symbolic_operand"))
|
|
|
73
|
|
|
74 (define_constraint "T"
|
|
|
75 "@internal
|
|
|
76 A constant @code{move_operand}."
|
|
|
77 (and (match_operand 0 "move_operand")
|
|
|
78 (match_test "CONSTANT_P (op)")))
|
