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1 ;; Machine description for RISC-V atomic operations.
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2 ;; Copyright (C) 2011-2018 Free Software Foundation, Inc.
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3 ;; Contributed by Andrew Waterman (andrew@sifive.com).
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4 ;; Based on MIPS target for GNU compiler.
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5
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6 ;; This file is part of GCC.
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7
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8 ;; GCC is free software; you can redistribute it and/or modify
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9 ;; it under the terms of the GNU General Public License as published by
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10 ;; the Free Software Foundation; either version 3, or (at your option)
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11 ;; any later version.
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12
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13 ;; GCC is distributed in the hope that it will be useful,
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14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 ;; GNU General Public License for more details.
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17
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 (define_c_enum "unspec" [
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23 UNSPEC_COMPARE_AND_SWAP
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24 UNSPEC_SYNC_OLD_OP
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25 UNSPEC_SYNC_EXCHANGE
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26 UNSPEC_ATOMIC_STORE
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27 UNSPEC_MEMORY_BARRIER
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28 ])
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29
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30 (define_code_iterator any_atomic [plus ior xor and])
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31 (define_code_attr atomic_optab
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32 [(plus "add") (ior "or") (xor "xor") (and "and")])
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33
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34 ;; Memory barriers.
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35
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36 (define_expand "mem_thread_fence"
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37 [(match_operand:SI 0 "const_int_operand" "")] ;; model
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38 ""
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39 {
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40 if (INTVAL (operands[0]) != MEMMODEL_RELAXED)
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41 {
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42 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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43 MEM_VOLATILE_P (mem) = 1;
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44 emit_insn (gen_mem_thread_fence_1 (mem, operands[0]));
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45 }
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46 DONE;
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47 })
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48
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49 ;; Until the RISC-V memory model (hence its mapping from C++) is finalized,
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50 ;; conservatively emit a full FENCE.
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51 (define_insn "mem_thread_fence_1"
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52 [(set (match_operand:BLK 0 "" "")
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53 (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))
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54 (match_operand:SI 1 "const_int_operand" "")] ;; model
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55 ""
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56 "fence\tiorw,iorw")
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57
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58 ;; Atomic memory operations.
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59
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60 ;; Implement atomic stores with amoswap. Fall back to fences for atomic loads.
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61 (define_insn "atomic_store<mode>"
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62 [(set (match_operand:GPR 0 "memory_operand" "=A")
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63 (unspec_volatile:GPR
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64 [(match_operand:GPR 1 "reg_or_0_operand" "rJ")
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65 (match_operand:SI 2 "const_int_operand")] ;; model
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66 UNSPEC_ATOMIC_STORE))]
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67 "TARGET_ATOMIC"
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68 "%F2amoswap.<amo>%A2 zero,%z1,%0"
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69 [(set (attr "length") (const_int 8))])
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70
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71 (define_insn "atomic_<atomic_optab><mode>"
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72 [(set (match_operand:GPR 0 "memory_operand" "+A")
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73 (unspec_volatile:GPR
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74 [(any_atomic:GPR (match_dup 0)
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75 (match_operand:GPR 1 "reg_or_0_operand" "rJ"))
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76 (match_operand:SI 2 "const_int_operand")] ;; model
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77 UNSPEC_SYNC_OLD_OP))]
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78 "TARGET_ATOMIC"
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79 "%F2amo<insn>.<amo>%A2 zero,%z1,%0"
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80 [(set (attr "length") (const_int 8))])
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81
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82 (define_insn "atomic_fetch_<atomic_optab><mode>"
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83 [(set (match_operand:GPR 0 "register_operand" "=&r")
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84 (match_operand:GPR 1 "memory_operand" "+A"))
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85 (set (match_dup 1)
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86 (unspec_volatile:GPR
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87 [(any_atomic:GPR (match_dup 1)
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88 (match_operand:GPR 2 "reg_or_0_operand" "rJ"))
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89 (match_operand:SI 3 "const_int_operand")] ;; model
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90 UNSPEC_SYNC_OLD_OP))]
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91 "TARGET_ATOMIC"
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92 "%F3amo<insn>.<amo>%A3 %0,%z2,%1"
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93 [(set (attr "length") (const_int 8))])
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94
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95 (define_insn "atomic_exchange<mode>"
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96 [(set (match_operand:GPR 0 "register_operand" "=&r")
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97 (unspec_volatile:GPR
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98 [(match_operand:GPR 1 "memory_operand" "+A")
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99 (match_operand:SI 3 "const_int_operand")] ;; model
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100 UNSPEC_SYNC_EXCHANGE))
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101 (set (match_dup 1)
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102 (match_operand:GPR 2 "register_operand" "0"))]
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103 "TARGET_ATOMIC"
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104 "%F3amoswap.<amo>%A3 %0,%z2,%1"
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105 [(set (attr "length") (const_int 8))])
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106
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107 (define_insn "atomic_cas_value_strong<mode>"
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108 [(set (match_operand:GPR 0 "register_operand" "=&r")
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109 (match_operand:GPR 1 "memory_operand" "+A"))
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110 (set (match_dup 1)
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111 (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "rJ")
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112 (match_operand:GPR 3 "reg_or_0_operand" "rJ")
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113 (match_operand:SI 4 "const_int_operand") ;; mod_s
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114 (match_operand:SI 5 "const_int_operand")] ;; mod_f
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115 UNSPEC_COMPARE_AND_SWAP))
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116 (clobber (match_scratch:GPR 6 "=&r"))]
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117 "TARGET_ATOMIC"
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118 "%F5 1: lr.<amo>%A5 %0,%1; bne %0,%z2,1f; sc.<amo>%A4 %6,%z3,%1; bnez %6,1b; 1:"
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119 [(set (attr "length") (const_int 20))])
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120
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121 (define_expand "atomic_compare_and_swap<mode>"
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122 [(match_operand:SI 0 "register_operand" "") ;; bool output
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123 (match_operand:GPR 1 "register_operand" "") ;; val output
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124 (match_operand:GPR 2 "memory_operand" "") ;; memory
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125 (match_operand:GPR 3 "reg_or_0_operand" "") ;; expected value
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126 (match_operand:GPR 4 "reg_or_0_operand" "") ;; desired value
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127 (match_operand:SI 5 "const_int_operand" "") ;; is_weak
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128 (match_operand:SI 6 "const_int_operand" "") ;; mod_s
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129 (match_operand:SI 7 "const_int_operand" "")] ;; mod_f
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130 "TARGET_ATOMIC"
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131 {
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132 emit_insn (gen_atomic_cas_value_strong<mode> (operands[1], operands[2],
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133 operands[3], operands[4],
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134 operands[6], operands[7]));
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135
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136 rtx compare = operands[1];
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137 if (operands[3] != const0_rtx)
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138 {
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139 rtx difference = gen_rtx_MINUS (<MODE>mode, operands[1], operands[3]);
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140 compare = gen_reg_rtx (<MODE>mode);
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141 emit_insn (gen_rtx_SET (compare, difference));
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142 }
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143
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144 if (word_mode != <MODE>mode)
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145 {
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146 rtx reg = gen_reg_rtx (word_mode);
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147 emit_insn (gen_rtx_SET (reg, gen_rtx_SIGN_EXTEND (word_mode, compare)));
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148 compare = reg;
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149 }
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150
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151 emit_insn (gen_rtx_SET (operands[0], gen_rtx_EQ (SImode, compare, const0_rtx)));
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152 DONE;
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153 })
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154
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155 (define_expand "atomic_test_and_set"
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156 [(match_operand:QI 0 "register_operand" "") ;; bool output
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157 (match_operand:QI 1 "memory_operand" "+A") ;; memory
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158 (match_operand:SI 2 "const_int_operand" "")] ;; model
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159 "TARGET_ATOMIC"
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160 {
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161 /* We have no QImode atomics, so use the address LSBs to form a mask,
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162 then use an aligned SImode atomic. */
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163 rtx result = operands[0];
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164 rtx mem = operands[1];
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165 rtx model = operands[2];
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166 rtx addr = force_reg (Pmode, XEXP (mem, 0));
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167
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168 rtx aligned_addr = gen_reg_rtx (Pmode);
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169 emit_move_insn (aligned_addr, gen_rtx_AND (Pmode, addr, GEN_INT (-4)));
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170
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171 rtx aligned_mem = change_address (mem, SImode, aligned_addr);
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172 set_mem_alias_set (aligned_mem, 0);
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173
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174 rtx offset = gen_reg_rtx (SImode);
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175 emit_move_insn (offset, gen_rtx_AND (SImode, gen_lowpart (SImode, addr),
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176 GEN_INT (3)));
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177
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178 rtx tmp = gen_reg_rtx (SImode);
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179 emit_move_insn (tmp, GEN_INT (1));
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180
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181 rtx shmt = gen_reg_rtx (SImode);
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182 emit_move_insn (shmt, gen_rtx_ASHIFT (SImode, offset, GEN_INT (3)));
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183
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184 rtx word = gen_reg_rtx (SImode);
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185 emit_move_insn (word, gen_rtx_ASHIFT (SImode, tmp,
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186 gen_lowpart (QImode, shmt)));
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111
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187
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188 tmp = gen_reg_rtx (SImode);
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189 emit_insn (gen_atomic_fetch_orsi (tmp, aligned_mem, word, model));
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190
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191 emit_move_insn (gen_lowpart (SImode, result),
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192 gen_rtx_LSHIFTRT (SImode, tmp,
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131
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193 gen_lowpart (QImode, shmt)));
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194 DONE;
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195 })
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