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111
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1 /* GCC backend definitions for the Renesas RL78 processor.
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131
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2 Copyright (C) 2011-2018 Free Software Foundation, Inc.
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111
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3 Contributed by Red Hat.
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify it
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8 under the terms of the GNU General Public License as published
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9 by the Free Software Foundation; either version 3, or (at your
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10 option) any later version.
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11
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12 GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 License for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21
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22 #define RL78_MUL_NONE (rl78_mul_type == MUL_NONE)
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23 #define RL78_MUL_G13 (rl78_mul_type == MUL_G13)
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24 #define RL78_MUL_G14 (rl78_mul_type == MUL_G14)
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25
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26 #define TARGET_G10 (rl78_cpu_type == CPU_G10)
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27 #define TARGET_G13 (rl78_cpu_type == CPU_G13)
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28 #define TARGET_G14 (rl78_cpu_type == CPU_G14)
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29
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30 #define TARGET_CPU_CPP_BUILTINS() \
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31 do \
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32 { \
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33 builtin_define ("__RL78__"); \
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34 builtin_assert ("cpu=RL78"); \
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35 \
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36 if (RL78_MUL_NONE) \
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37 builtin_define ("__RL78_MUL_NONE__"); \
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38 else if (RL78_MUL_G13) \
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39 builtin_define ("__RL78_MUL_G13__"); \
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40 else if (RL78_MUL_G14) \
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41 builtin_define ("__RL78_MUL_G14__"); \
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42 \
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43 if (TARGET_G10) \
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44 builtin_define ("__RL78_G10__"); \
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45 else if (TARGET_G13) \
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46 builtin_define ("__RL78_G13__"); \
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47 else if (TARGET_G14) \
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48 builtin_define ("__RL78_G14__"); \
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49 } \
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50 while (0)
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51
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52 #undef STARTFILE_SPEC
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53 #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s} crtbegin.o%s"
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54
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55 #undef ENDFILE_SPEC
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56 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
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57
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58 #undef ASM_SPEC
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59 #define ASM_SPEC "\
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60 %{mrelax:-relax} \
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61 %{mg10:--mg10} \
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62 %{mg13:--mg13} \
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63 %{mg14:--mg14} \
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64 %{mrl78:--mg14} \
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65 %{mcpu=g10:--mg10} \
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66 %{mcpu=g13:--mg13} \
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67 %{mcpu=g14:--mg14} \
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68 %{mcpu=rl78:--mg14} \
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69 "
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70
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71 #undef LINK_SPEC
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72 #define LINK_SPEC "\
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73 %{mrelax:-relax} \
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74 %{!r:--gc-sections} \
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75 "
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76
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77 #undef LIB_SPEC
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78 #define LIB_SPEC " \
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79 --start-group \
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80 -lc \
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81 -lsim \
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82 %{fprofile-arcs|fprofile-generate|coverage:-lgcov} \
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83 --end-group \
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84 %{!T*: %{msim:%Trl78-sim.ld}%{!msim:%Trl78.ld}} \
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85 "
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86
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87
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88 #define BITS_BIG_ENDIAN 0
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89 #define BYTES_BIG_ENDIAN 0
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90 #define WORDS_BIG_ENDIAN 0
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91
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92 #ifdef IN_LIBGCC2
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93 /* This is to get correct SI and DI modes in libgcc2.c (32 and 64 bits). */
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94 #define UNITS_PER_WORD 4
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95 /* We have a problem with libgcc2. It only defines two versions of
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96 each function, one for "int" and one for "long long". Ie it assumes
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97 that "sizeof (int) == sizeof (long)". For the RL78 this is not true
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98 and we need a third set of functions. We explicitly define
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99 LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting
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100 to get the SI and DI versions from the libgcc2.c sources, and we
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101 provide our own set of HI functions, which is why this
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102 definition is surrounded by #ifndef..#endif. */
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103 #ifndef LIBGCC2_UNITS_PER_WORD
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104 #define LIBGCC2_UNITS_PER_WORD 4
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105 #endif
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106 #else
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107 /* Actual width of a word, in units (bytes). */
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108 #define UNITS_PER_WORD 1
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109 #endif
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110
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111 #define SHORT_TYPE_SIZE 16
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112 #define INT_TYPE_SIZE 16
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113 #define LONG_TYPE_SIZE 32
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114 #define LONG_LONG_TYPE_SIZE 64
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115
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116 #define FLOAT_TYPE_SIZE 32
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117 #define DOUBLE_TYPE_SIZE 32 /*64*/
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118 #define LONG_DOUBLE_TYPE_SIZE 64 /*DOUBLE_TYPE_SIZE*/
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119
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120 #define DEFAULT_SIGNED_CHAR 0
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121
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122 #define STRICT_ALIGNMENT 1
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123 #define FUNCTION_BOUNDARY 8
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124 #define BIGGEST_ALIGNMENT 16
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125 #define STACK_BOUNDARY 16
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126 #define PARM_BOUNDARY 16
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127
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128 #define STACK_GROWS_DOWNWARD 1
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129 #define FRAME_GROWS_DOWNWARD 1
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130 #define FIRST_PARM_OFFSET(FNDECL) 0
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131
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132 #define MAX_REGS_PER_ADDRESS 1
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133
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134 #define Pmode HImode
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135 #define POINTER_SIZE 16
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136 #undef SIZE_TYPE
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137 #define SIZE_TYPE "unsigned int"
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138 #undef PTRDIFF_TYPE
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139 #define PTRDIFF_TYPE "int"
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140 #undef WCHAR_TYPE
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141 #define WCHAR_TYPE "long int"
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142 #undef WCHAR_TYPE_SIZE
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143 #define WCHAR_TYPE_SIZE BITS_PER_WORD
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144 #define POINTERS_EXTEND_UNSIGNED 1
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145 #define FUNCTION_MODE HImode
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146 #define CASE_VECTOR_MODE Pmode
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147 #define WORD_REGISTER_OPERATIONS 1
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148 #define HAS_LONG_COND_BRANCH 0
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149 #define HAS_LONG_UNCOND_BRANCH 0
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150
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151 #define MOVE_MAX 2
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152
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153 #define ADDR_SPACE_NEAR 1
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154 #define ADDR_SPACE_FAR 2
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155
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156 #define HAVE_PRE_DECCREMENT 0
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157 #define HAVE_POST_INCREMENT 0
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158
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159 #define MOVE_RATIO(SPEED) ((SPEED) ? 24 : 16)
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160 #define SLOW_BYTE_ACCESS 0
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161
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162 #define STORE_FLAG_VALUE 1
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163 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
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164
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165
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166 /* The RL78 has four register banks. Normal operation uses RB0 as
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167 real registers, RB1 and RB2 as "virtual" registers (because we know
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168 they'll be there, and not used as variables), and RB3 is reserved
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169 for interrupt handlers. The virtual registers are accessed as
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170 SADDRs:
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171
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172 FFEE0-FFEE7 RB0
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173 FFEE8-FFEEF RB1
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174 FFEF0-FFEF7 RB2
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175 FFEF8-FFEFF RB3
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176 */
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177 #define REGISTER_NAMES \
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178 { \
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179 "x", "a", "c", "b", "e", "d", "l", "h", \
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180 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
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181 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
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182 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
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183 "sp", "ap", "psw", "es", "cs" \
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184 }
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185
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186 #define ADDITIONAL_REGISTER_NAMES \
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187 { \
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188 { "ax", 0 }, \
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189 { "bc", 2 }, \
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190 { "de", 4 }, \
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191 { "hl", 6 }, \
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192 { "rp0", 0 }, \
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193 { "rp1", 2 }, \
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194 { "rp2", 4 }, \
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195 { "rp3", 6 }, \
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196 { "r0", 0 }, \
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197 { "r1", 1 }, \
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198 { "r2", 2 }, \
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199 { "r3", 3 }, \
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200 { "r4", 4 }, \
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201 { "r5", 5 }, \
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202 { "r6", 6 }, \
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203 { "r7", 7 }, \
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204 }
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205
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206 enum reg_class
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207 {
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208 NO_REGS, /* No registers in set. */
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209 XREG,
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210 AREG,
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211 AXREG,
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212 CREG,
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213 BREG,
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214 BCREG,
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215 EREG,
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216 DREG,
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217 DEREG,
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218 LREG,
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219 HREG,
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220 HLREG,
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221 IDX_REGS,
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222 QI_REGS,
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223 SPREG,
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224 R8W_REGS,
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225 R10W_REGS,
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226 INT_REGS,
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227 V_REGS, /* Virtual registers. */
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228 GR_REGS, /* Integer registers. */
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229 PSWREG,
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230 ALL_REGS, /* All registers. */
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231 LIM_REG_CLASSES /* Max value + 1. */
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232 };
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233
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234 #define REG_CLASS_NAMES \
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235 { \
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236 "NO_REGS", \
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237 "XREG", \
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238 "AREG", \
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239 "AXREG", \
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240 "CREG", \
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241 "BREG", \
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242 "BCREG", \
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243 "EREG", \
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244 "DREG", \
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245 "DEREG", \
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246 "LREG", \
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247 "HREG", \
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248 "HLREG", \
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249 "IDX_REGS", \
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250 "QI_REGS", \
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251 "SPREG", \
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252 "R8W_REGS", \
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253 "R10W_REGS", \
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254 "INT_REGS", \
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255 "V_REGS", \
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256 "GR_REGS", \
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257 "PSWREG", \
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258 "ALL_REGS" \
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259 }
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260
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261 /* Note that no class may include the second register in $fp, because
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262 we treat $fp as a single HImode register. */
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263 #define REG_CLASS_CONTENTS \
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264 { \
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265 { 0x00000000, 0x00000000 }, /* No registers, */ \
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266 { 0x00000001, 0x00000000 }, \
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267 { 0x00000002, 0x00000000 }, \
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268 { 0x00000003, 0x00000000 }, \
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269 { 0x00000004, 0x00000000 }, \
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270 { 0x00000008, 0x00000000 }, \
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271 { 0x0000000c, 0x00000000 }, \
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272 { 0x00000010, 0x00000000 }, \
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273 { 0x00000020, 0x00000000 }, \
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274 { 0x00000030, 0x00000000 }, \
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275 { 0x00000040, 0x00000000 }, \
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276 { 0x00000080, 0x00000000 }, \
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277 { 0x000000c0, 0x00000000 }, \
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278 { 0x0000000c, 0x00000000 }, /* B and C - index regs. */ \
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279 { 0x000000ff, 0x00000000 }, /* all real registers. */ \
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280 { 0x00000000, 0x00000001 }, /* SP */ \
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281 { 0x00000300, 0x00000000 }, /* R8 - HImode */ \
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282 { 0x00000c00, 0x00000000 }, /* R10 - HImode */ \
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283 { 0xff000000, 0x00000000 }, /* INT - HImode */ \
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284 { 0xff7fff00, 0x00000000 }, /* Virtual registers. */ \
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285 { 0xff7fff00, 0x00000002 }, /* General registers. */ \
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286 { 0x04000000, 0x00000004 }, /* PSW. */ \
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287 { 0xff7fffff, 0x0000001f } /* All registers. */ \
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288 }
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289
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290 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
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291 #define N_REG_CLASSES (int) LIM_REG_CLASSES
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292 #define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) \
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293 + UNITS_PER_WORD - 1) \
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294 / UNITS_PER_WORD)
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295
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296 #define GENERAL_REGS GR_REGS
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297 #define BASE_REG_CLASS V_REGS
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298 #define INDEX_REG_CLASS V_REGS
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299
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300 #define FIRST_PSEUDO_REGISTER 37
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301
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302 #define REGNO_REG_CLASS(REGNO) ((REGNO) < FIRST_PSEUDO_REGISTER \
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303 ? GR_REGS : NO_REGS)
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304
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305 #define FRAME_POINTER_REGNUM 22
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306 #define STACK_POINTER_REGNUM 32
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307 #define ARG_POINTER_REGNUM 33
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308 #define CC_REGNUM 34
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309 #define FUNC_RETURN_REGNUM 8
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310 #define STATIC_CHAIN_REGNUM 14
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311
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312 /* Trampolines are implemented with a separate data stack. The memory
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313 on stack only holds the function pointer for the chosen stub.
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314 */
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315
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316 #define TRAMPOLINE_SIZE 4
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317 #define TRAMPOLINE_ALIGNMENT 16
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318
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319 #define ELIMINABLE_REGS \
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320 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
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321 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
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322 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
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323
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324 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
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325 (OFFSET) = rl78_initial_elimination_offset ((FROM), (TO))
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326
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327
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328 #define FUNCTION_ARG_REGNO_P(N) 0
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329 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8)
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330 #define DEFAULT_PCC_STRUCT_RETURN 0
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331
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332 #define FIXED_REGISTERS \
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333 { \
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334 1,1,1,1, 1,1,1,1, \
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335 0,0,0,0, 0,0,0,0, \
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336 0,0,0,0, 0,0,1,1, \
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337 1,1,1,1, 1,1,1,1, \
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338 0, 1, 0, 1, 1 \
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339 }
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340
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341 #define CALL_USED_REGISTERS \
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342 { \
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343 1,1,1,1, 1,1,1,1, \
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344 1,1,1,1, 1,1,1,1, \
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345 0,0,0,0, 0,0,1,1, \
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346 1,1,1,1, 1,1,1,1, \
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347 0, 1, 1, 1, 1 \
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348 }
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349
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350 #define LIBCALL_VALUE(MODE) \
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351 gen_rtx_REG ((MODE), \
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352 FUNC_RETURN_REGNUM)
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353
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354 /* Order of allocation of registers. */
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355
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356 #define REG_ALLOC_ORDER \
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357 { 8, 9, 10, 11, 12, 13, 14, 15, \
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358 16, 17, 18, 19, 20, 21, 22, 23, \
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359 0, 1, 6, 7, 2, 3, 4, 5, \
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360 24, 25, 26, 27, 28, 29, 30, 31, \
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361 32, 33, 34 \
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362 }
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363
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364 #define REGNO_IN_RANGE(REGNO, MIN, MAX) \
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365 (IN_RANGE ((REGNO), (MIN), (MAX)) \
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366 || (reg_renumber != NULL \
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367 && reg_renumber[(REGNO)] >= (MIN) \
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368 && reg_renumber[(REGNO)] <= (MAX)))
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369
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370 #ifdef REG_OK_STRICT
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371 #define REGNO_OK_FOR_BASE_P(regno) REGNO_IN_RANGE (regno, 16, 31)
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372 #else
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373 #define REGNO_OK_FOR_BASE_P(regno) 1
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374 #endif
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375
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376 #define REGNO_OK_FOR_INDEX_P(regno) REGNO_OK_FOR_BASE_P (regno)
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377
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378 #define REGNO_MODE_CODE_OK_FOR_BASE_P(regno, mode, address_space, outer_code, index_code) \
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379 rl78_regno_mode_code_ok_for_base_p (regno, mode, address_space, outer_code, index_code)
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380
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381 #define MODE_CODE_BASE_REG_CLASS(mode, address_space, outer_code, index_code) \
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382 rl78_mode_code_base_reg_class (mode, address_space, outer_code, index_code)
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383
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384 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
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385 ((COUNT) == 0 \
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386 ? gen_rtx_MEM (Pmode, gen_rtx_PLUS (HImode, arg_pointer_rtx, GEN_INT (-4))) \
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387 : NULL_RTX)
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388
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389 #define INCOMING_RETURN_ADDR_RTX gen_rtx_MEM (Pmode, stack_pointer_rtx)
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390
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391 #define ACCUMULATE_OUTGOING_ARGS 1
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392
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393 typedef unsigned int CUMULATIVE_ARGS;
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394
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395 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
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396 (CUM) = 0
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397
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398
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399 /* FIXME */
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400 #define NO_PROFILE_COUNTERS 1
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401 #define PROFILE_BEFORE_PROLOGUE 1
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402
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403 #define FUNCTION_PROFILER(FILE, LABELNO) \
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404 fprintf (FILE, "\tbsr\t__mcount\n");
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405
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406
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407 #define TEXT_SECTION_ASM_OP ".text"
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408 #define DATA_SECTION_ASM_OP ".data"
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409 #define BSS_SECTION_ASM_OP ".bss"
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410 #define CTORS_SECTION_ASM_OP ".section \".ctors\",\"a\""
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411 #define DTORS_SECTION_ASM_OP ".section \".dtors\",\"a\""
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412
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413 #define ASM_COMMENT_START " ;"
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414 #define ASM_APP_ON ""
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415 #define ASM_APP_OFF ""
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416 #define LOCAL_LABEL_PREFIX ".L"
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417 #undef USER_LABEL_PREFIX
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418 #define USER_LABEL_PREFIX "_"
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419
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420 #define GLOBAL_ASM_OP "\t.global\t"
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421
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422 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
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423 fprintf (FILE, "\t.long .L%d\n", VALUE)
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424
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425 /* This is how to output an element of a case-vector that is relative.
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426 Note: The local label referenced by the "3b" below is emitted by
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427 the tablejump insn. */
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428
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429 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
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430 fprintf (FILE, "\t.long .L%d - 1b\n", VALUE)
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431
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432
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433 #define ASM_OUTPUT_SYMBOL_REF(FILE, SYM) rl78_output_symbol_ref ((FILE), (SYM))
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434
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435 #define ASM_OUTPUT_LABELREF(FILE, SYM) rl78_output_labelref ((FILE), (SYM))
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436
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437 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
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438 rl78_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
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439
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440 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
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441 rl78_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
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442
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443 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
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444 do \
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445 { \
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446 if ((LOG) == 0) \
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447 break; \
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448 fprintf (STREAM, "\t.balign %d\n", 1 << (LOG)); \
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449 } \
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450 while (0)
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451
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452 /* For PIC put jump tables into the text section so that the offsets that
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453 they contain are always computed between two same-section symbols. */
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454 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
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455
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456 /* This is a version of REG_P that also returns TRUE for SUBREGs. */
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457 #define RL78_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
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458
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459 /* Like REG_P except that this macro is true for SET expressions. */
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460 #define SET_P(rtl) (GET_CODE (rtl) == SET)
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461
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462 #undef PREFERRED_DEBUGGING_TYPE
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463 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
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464
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465 #undef DWARF2_ADDR_SIZE
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466 #define DWARF2_ADDR_SIZE 4
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467
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468 #define DWARF2_ASM_LINE_DEBUG_INFO 1
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469
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470 #define EXIT_IGNORE_STACK 0
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471 #define INCOMING_FRAME_SP_OFFSET 4
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472
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473
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474 #define BRANCH_COST(SPEED,PREDICT) 1
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475 #define REGISTER_MOVE_COST(MODE,FROM,TO) 2
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476
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477 #define EH_RETURN_DATA_REGNO(N) (N < 2 ? (8+(N)*2) : INVALID_REGNUM)
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478 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (HImode, 20)
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479
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480 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) DW_EH_PE_udata4
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481
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482 /* NOTE: defined but zero means dwarf2 debugging, but sjlj EH. */
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483 #define DWARF2_UNWIND_INFO 0
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484
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485 #define REGISTER_TARGET_PRAGMAS() rl78_register_pragmas()
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