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1 ;; Scheduling description for IBM PowerPC 440 processor.
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2 ;; Copyright (C) 2003-2018 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; PPC440 Embedded PowerPC controller
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21 ;; dual issue
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22 ;; i_pipe - complex integer / compare / branch
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23 ;; j_pipe - simple integer arithmetic
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24 ;; l_pipe - load-store
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25 ;; f_pipe - floating point arithmetic
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26
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27 (define_automaton "ppc440_core,ppc440_apu")
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28 (define_cpu_unit "ppc440_i_pipe,ppc440_j_pipe,ppc440_l_pipe" "ppc440_core")
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29 (define_cpu_unit "ppc440_f_pipe" "ppc440_apu")
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30 (define_cpu_unit "ppc440_issue_0,ppc440_issue_1" "ppc440_core")
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31
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32 (define_reservation "ppc440_issue" "ppc440_issue_0|ppc440_issue_1")
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33
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34
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35 (define_insn_reservation "ppc440-load" 3
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111
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36 (and (eq_attr "type" "load,load_l,store_c,sync")
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37 (eq_attr "cpu" "ppc440"))
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38 "ppc440_issue,ppc440_l_pipe")
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39
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40 (define_insn_reservation "ppc440-store" 3
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111
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41 (and (eq_attr "type" "store")
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42 (eq_attr "cpu" "ppc440"))
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43 "ppc440_issue,ppc440_l_pipe")
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44
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45 (define_insn_reservation "ppc440-fpload" 4
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111
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46 (and (eq_attr "type" "fpload")
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47 (eq_attr "cpu" "ppc440"))
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48 "ppc440_issue,ppc440_l_pipe")
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49
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50 (define_insn_reservation "ppc440-fpstore" 3
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111
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51 (and (eq_attr "type" "fpstore")
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52 (eq_attr "cpu" "ppc440"))
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53 "ppc440_issue,ppc440_l_pipe")
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54
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55 (define_insn_reservation "ppc440-integer" 1
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111
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56 (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
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57 (and (eq_attr "type" "add,logical,shift,exts")
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58 (eq_attr "dot" "no")))
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59 (eq_attr "cpu" "ppc440"))
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60 "ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
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61
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62 (define_insn_reservation "ppc440-two" 1
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63 (and (eq_attr "type" "two")
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64 (eq_attr "cpu" "ppc440"))
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65 "ppc440_issue_0+ppc440_issue_1,\
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66 ppc440_i_pipe|ppc440_j_pipe,ppc440_i_pipe|ppc440_j_pipe")
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67
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68 (define_insn_reservation "ppc440-three" 1
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69 (and (eq_attr "type" "three")
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70 (eq_attr "cpu" "ppc440"))
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71 "ppc440_issue_0+ppc440_issue_1,ppc440_i_pipe|ppc440_j_pipe,\
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72 ppc440_i_pipe|ppc440_j_pipe,ppc440_i_pipe|ppc440_j_pipe")
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73
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74 (define_insn_reservation "ppc440-imul" 3
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111
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75 (and (eq_attr "type" "mul")
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76 (eq_attr "size" "32")
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77 (eq_attr "cpu" "ppc440"))
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78 "ppc440_issue,ppc440_i_pipe")
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79
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80 (define_insn_reservation "ppc440-imul2" 2
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111
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81 (and (ior (eq_attr "type" "halfmul")
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82 (and (eq_attr "type" "mul")
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83 (eq_attr "size" "8,16")))
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84 (eq_attr "cpu" "ppc440"))
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85 "ppc440_issue,ppc440_i_pipe")
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86
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87 (define_insn_reservation "ppc440-idiv" 34
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111
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88 (and (eq_attr "type" "div")
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89 (eq_attr "cpu" "ppc440"))
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90 "ppc440_issue,ppc440_i_pipe*33")
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91
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92 (define_insn_reservation "ppc440-branch" 1
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93 (and (eq_attr "type" "branch,jmpreg,isync")
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94 (eq_attr "cpu" "ppc440"))
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95 "ppc440_issue,ppc440_i_pipe")
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96
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97 (define_insn_reservation "ppc440-compare" 2
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131
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98 (and (ior (eq_attr "type" "cmp,cr_logical,mfcr")
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111
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99 (and (eq_attr "type" "add,logical,shift,exts")
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100 (eq_attr "dot" "yes")))
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101 (eq_attr "cpu" "ppc440"))
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102 "ppc440_issue,ppc440_i_pipe")
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103
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104 (define_insn_reservation "ppc440-fpcompare" 3 ; 2
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105 (and (eq_attr "type" "fpcompare")
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106 (eq_attr "cpu" "ppc440"))
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107 "ppc440_issue,ppc440_f_pipe+ppc440_i_pipe")
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108
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109 (define_insn_reservation "ppc440-fp" 5
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111
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110 (and (eq_attr "type" "fp,fpsimple,dmul")
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111 (eq_attr "cpu" "ppc440"))
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112 "ppc440_issue,ppc440_f_pipe")
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113
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114 (define_insn_reservation "ppc440-sdiv" 19
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115 (and (eq_attr "type" "sdiv")
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116 (eq_attr "cpu" "ppc440"))
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117 "ppc440_issue,ppc440_f_pipe*15")
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118
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119 (define_insn_reservation "ppc440-ddiv" 33
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120 (and (eq_attr "type" "ddiv")
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121 (eq_attr "cpu" "ppc440"))
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122 "ppc440_issue,ppc440_f_pipe*29")
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123
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124 (define_insn_reservation "ppc440-mtcr" 3
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125 (and (eq_attr "type" "mtcr")
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126 (eq_attr "cpu" "ppc440"))
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127 "ppc440_issue,ppc440_i_pipe")
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128
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129 (define_insn_reservation "ppc440-mtjmpr" 4
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130 (and (eq_attr "type" "mtjmpr")
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131 (eq_attr "cpu" "ppc440"))
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132 "ppc440_issue,ppc440_i_pipe")
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133
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134 (define_insn_reservation "ppc440-mfjmpr" 2
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135 (and (eq_attr "type" "mfjmpr")
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136 (eq_attr "cpu" "ppc440"))
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137 "ppc440_issue,ppc440_i_pipe")
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138
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