0
|
1 ;; Pipeline description for Motorola PowerPC e500mc core.
|
131
|
2 ;; Copyright (C) 2008-2018 Free Software Foundation, Inc.
|
0
|
3 ;; Contributed by Edmar Wienskoski (edmar@freescale.com)
|
|
4 ;;
|
|
5 ;; This file is part of GCC.
|
|
6 ;;
|
|
7 ;; GCC is free software; you can redistribute it and/or modify it
|
|
8 ;; under the terms of the GNU General Public License as published
|
|
9 ;; by the Free Software Foundation; either version 3, or (at your
|
|
10 ;; option) any later version.
|
|
11 ;;
|
|
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
|
|
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
|
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
|
15 ;; License for more details.
|
|
16 ;;
|
|
17 ;; You should have received a copy of the GNU General Public License
|
|
18 ;; along with GCC; see the file COPYING3. If not see
|
|
19 ;; <http://www.gnu.org/licenses/>.
|
|
20 ;;
|
|
21 ;; e500mc 32-bit SU(2), LSU, FPU, BPU
|
|
22 ;; Max issue 3 insns/clock cycle (includes 1 branch)
|
|
23 ;; FP is half clocked, timings of other instructions are as in the e500v2.
|
|
24
|
|
25 (define_automaton "e500mc_most,e500mc_long,e500mc_retire")
|
|
26 (define_cpu_unit "e500mc_decode_0,e500mc_decode_1" "e500mc_most")
|
|
27 (define_cpu_unit "e500mc_issue_0,e500mc_issue_1" "e500mc_most")
|
|
28 (define_cpu_unit "e500mc_retire_0,e500mc_retire_1" "e500mc_retire")
|
|
29
|
|
30 ;; SU.
|
|
31 (define_cpu_unit "e500mc_su0_stage0,e500mc_su1_stage0" "e500mc_most")
|
|
32
|
|
33 ;; MU.
|
|
34 (define_cpu_unit "e500mc_mu_stage0,e500mc_mu_stage1" "e500mc_most")
|
|
35 (define_cpu_unit "e500mc_mu_stage2,e500mc_mu_stage3" "e500mc_most")
|
|
36
|
|
37 ;; Non-pipelined division.
|
|
38 (define_cpu_unit "e500mc_mu_div" "e500mc_long")
|
|
39
|
|
40 ;; LSU.
|
|
41 (define_cpu_unit "e500mc_lsu" "e500mc_most")
|
|
42
|
|
43 ;; FPU.
|
|
44 (define_cpu_unit "e500mc_fpu" "e500mc_most")
|
|
45
|
|
46 ;; Branch unit.
|
|
47 (define_cpu_unit "e500mc_bu" "e500mc_most")
|
|
48
|
|
49 ;; The following units are used to make the automata deterministic.
|
|
50 (define_cpu_unit "present_e500mc_decode_0" "e500mc_most")
|
|
51 (define_cpu_unit "present_e500mc_issue_0" "e500mc_most")
|
|
52 (define_cpu_unit "present_e500mc_retire_0" "e500mc_retire")
|
|
53 (define_cpu_unit "present_e500mc_su0_stage0" "e500mc_most")
|
|
54
|
|
55 ;; The following sets to make automata deterministic when option ndfa is used.
|
|
56 (presence_set "present_e500mc_decode_0" "e500mc_decode_0")
|
|
57 (presence_set "present_e500mc_issue_0" "e500mc_issue_0")
|
|
58 (presence_set "present_e500mc_retire_0" "e500mc_retire_0")
|
|
59 (presence_set "present_e500mc_su0_stage0" "e500mc_su0_stage0")
|
|
60
|
|
61 ;; Some useful abbreviations.
|
|
62 (define_reservation "e500mc_decode"
|
|
63 "e500mc_decode_0|e500mc_decode_1+present_e500mc_decode_0")
|
|
64 (define_reservation "e500mc_issue"
|
|
65 "e500mc_issue_0|e500mc_issue_1+present_e500mc_issue_0")
|
|
66 (define_reservation "e500mc_retire"
|
|
67 "e500mc_retire_0|e500mc_retire_1+present_e500mc_retire_0")
|
|
68 (define_reservation "e500mc_su_stage0"
|
|
69 "e500mc_su0_stage0|e500mc_su1_stage0+present_e500mc_su0_stage0")
|
|
70
|
|
71 ;; Simple SU insns.
|
|
72 (define_insn_reservation "e500mc_su" 1
|
111
|
73 (and (eq_attr "type" "integer,add,logical,insert,cmp,\
|
|
74 shift,trap,cntlz,exts,isel")
|
0
|
75 (eq_attr "cpu" "ppce500mc"))
|
|
76 "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
|
|
77
|
|
78 (define_insn_reservation "e500mc_two" 1
|
|
79 (and (eq_attr "type" "two")
|
|
80 (eq_attr "cpu" "ppce500mc"))
|
|
81 "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\
|
|
82 e500mc_issue+e500mc_su_stage0+e500mc_retire")
|
|
83
|
|
84 (define_insn_reservation "e500mc_three" 1
|
|
85 (and (eq_attr "type" "three")
|
|
86 (eq_attr "cpu" "ppce500mc"))
|
|
87 "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\
|
|
88 e500mc_issue+e500mc_su_stage0+e500mc_retire,\
|
|
89 e500mc_issue+e500mc_su_stage0+e500mc_retire")
|
|
90
|
|
91 ;; Multiply.
|
|
92 (define_insn_reservation "e500mc_multiply" 4
|
111
|
93 (and (eq_attr "type" "mul")
|
0
|
94 (eq_attr "cpu" "ppce500mc"))
|
|
95 "e500mc_decode,e500mc_issue+e500mc_mu_stage0,e500mc_mu_stage1,\
|
|
96 e500mc_mu_stage2,e500mc_mu_stage3+e500mc_retire")
|
|
97
|
|
98 ;; Divide. We use the average latency time here.
|
|
99 (define_insn_reservation "e500mc_divide" 14
|
111
|
100 (and (eq_attr "type" "div")
|
0
|
101 (eq_attr "cpu" "ppce500mc"))
|
|
102 "e500mc_decode,e500mc_issue+e500mc_mu_stage0+e500mc_mu_div,\
|
|
103 e500mc_mu_div*13")
|
|
104
|
|
105 ;; Branch.
|
|
106 (define_insn_reservation "e500mc_branch" 1
|
|
107 (and (eq_attr "type" "jmpreg,branch,isync")
|
|
108 (eq_attr "cpu" "ppce500mc"))
|
|
109 "e500mc_decode,e500mc_bu,e500mc_retire")
|
|
110
|
|
111 ;; CR logical.
|
|
112 (define_insn_reservation "e500mc_cr_logical" 1
|
131
|
113 (and (eq_attr "type" "cr_logical")
|
0
|
114 (eq_attr "cpu" "ppce500mc"))
|
|
115 "e500mc_decode,e500mc_bu,e500mc_retire")
|
|
116
|
|
117 ;; Mfcr.
|
|
118 (define_insn_reservation "e500mc_mfcr" 1
|
|
119 (and (eq_attr "type" "mfcr")
|
|
120 (eq_attr "cpu" "ppce500mc"))
|
|
121 "e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire")
|
|
122
|
|
123 ;; Mtcrf.
|
|
124 (define_insn_reservation "e500mc_mtcrf" 1
|
|
125 (and (eq_attr "type" "mtcr")
|
|
126 (eq_attr "cpu" "ppce500mc"))
|
|
127 "e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire")
|
|
128
|
|
129 ;; Mtjmpr.
|
|
130 (define_insn_reservation "e500mc_mtjmpr" 1
|
|
131 (and (eq_attr "type" "mtjmpr,mfjmpr")
|
|
132 (eq_attr "cpu" "ppce500mc"))
|
|
133 "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
|
|
134
|
|
135 ;; Loads.
|
|
136 (define_insn_reservation "e500mc_load" 3
|
111
|
137 (and (eq_attr "type" "load,load_l,sync")
|
0
|
138 (eq_attr "cpu" "ppce500mc"))
|
|
139 "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
|
|
140
|
|
141 (define_insn_reservation "e500mc_fpload" 4
|
111
|
142 (and (eq_attr "type" "fpload")
|
0
|
143 (eq_attr "cpu" "ppce500mc"))
|
|
144 "e500mc_decode,e500mc_issue+e500mc_lsu,nothing*2,e500mc_retire")
|
|
145
|
|
146 ;; Stores.
|
|
147 (define_insn_reservation "e500mc_store" 3
|
111
|
148 (and (eq_attr "type" "store,store_c")
|
0
|
149 (eq_attr "cpu" "ppce500mc"))
|
|
150 "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
|
|
151
|
|
152 (define_insn_reservation "e500mc_fpstore" 3
|
111
|
153 (and (eq_attr "type" "fpstore")
|
0
|
154 (eq_attr "cpu" "ppce500mc"))
|
|
155 "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
|
|
156
|
|
157 ;; The following ignores the retire unit to avoid a large automata.
|
|
158
|
|
159 ;; Simple FP.
|
|
160 (define_insn_reservation "e500mc_simple_float" 8
|
|
161 (and (eq_attr "type" "fpsimple")
|
|
162 (eq_attr "cpu" "ppce500mc"))
|
|
163 "e500mc_decode,e500mc_issue+e500mc_fpu")
|
|
164 ; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire")
|
|
165
|
|
166 ;; FP.
|
|
167 (define_insn_reservation "e500mc_float" 8
|
|
168 (and (eq_attr "type" "fp")
|
|
169 (eq_attr "cpu" "ppce500mc"))
|
|
170 "e500mc_decode,e500mc_issue+e500mc_fpu")
|
|
171 ; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire")
|
|
172
|
|
173 (define_insn_reservation "e500mc_fpcompare" 8
|
|
174 (and (eq_attr "type" "fpcompare")
|
|
175 (eq_attr "cpu" "ppce500mc"))
|
|
176 "e500mc_decode,e500mc_issue+e500mc_fpu")
|
|
177
|
|
178 (define_insn_reservation "e500mc_dmul" 10
|
|
179 (and (eq_attr "type" "dmul")
|
|
180 (eq_attr "cpu" "ppce500mc"))
|
|
181 "e500mc_decode,e500mc_issue+e500mc_fpu")
|
|
182
|
|
183 ;; FP divides are not pipelined.
|
|
184 (define_insn_reservation "e500mc_sdiv" 36
|
|
185 (and (eq_attr "type" "sdiv")
|
|
186 (eq_attr "cpu" "ppce500mc"))
|
|
187 "e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*35")
|
|
188
|
|
189 (define_insn_reservation "e500mc_ddiv" 66
|
|
190 (and (eq_attr "type" "ddiv")
|
|
191 (eq_attr "cpu" "ppce500mc"))
|
|
192 "e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*65")
|