Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/rs6000/rs6000.h @ 131:84e7813d76e9
gcc-8.2
| author | mir3636 |
|---|---|
| date | Thu, 25 Oct 2018 07:37:49 +0900 |
| parents | 04ced10e8804 |
| children | 1830386684a0 |
| rev | line source |
|---|---|
| 0 | 1 /* Definitions of target machine for GNU compiler, for IBM RS/6000. |
| 131 | 2 Copyright (C) 1992-2018 Free Software Foundation, Inc. |
| 0 | 3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
| 4 | |
| 5 This file is part of GCC. | |
| 6 | |
| 7 GCC is free software; you can redistribute it and/or modify it | |
| 8 under the terms of the GNU General Public License as published | |
| 9 by the Free Software Foundation; either version 3, or (at your | |
| 10 option) any later version. | |
| 11 | |
| 12 GCC is distributed in the hope that it will be useful, but WITHOUT | |
| 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 15 License for more details. | |
| 16 | |
| 17 Under Section 7 of GPL version 3, you are granted additional | |
| 18 permissions described in the GCC Runtime Library Exception, version | |
| 19 3.1, as published by the Free Software Foundation. | |
| 20 | |
| 21 You should have received a copy of the GNU General Public License and | |
| 22 a copy of the GCC Runtime Library Exception along with this program; | |
| 23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
| 24 <http://www.gnu.org/licenses/>. */ | |
| 25 | |
| 26 /* Note that some other tm.h files include this one and then override | |
| 27 many of the definitions. */ | |
| 28 | |
|
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29 #ifndef RS6000_OPTS_H |
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30 #include "config/rs6000/rs6000-opts.h" |
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31 #endif |
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32 |
| 131 | 33 /* 128-bit floating point precision values. */ |
| 34 #ifndef RS6000_MODES_H | |
| 35 #include "config/rs6000/rs6000-modes.h" | |
| 36 #endif | |
| 37 | |
| 0 | 38 /* Definitions for the object file format. These are set at |
| 39 compile-time. */ | |
| 40 | |
| 41 #define OBJECT_XCOFF 1 | |
| 42 #define OBJECT_ELF 2 | |
| 43 #define OBJECT_PEF 3 | |
| 44 #define OBJECT_MACHO 4 | |
| 45 | |
| 46 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) | |
| 47 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) | |
| 48 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) | |
| 49 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) | |
| 50 | |
| 51 #ifndef TARGET_AIX | |
| 52 #define TARGET_AIX 0 | |
| 53 #endif | |
| 54 | |
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55 #ifndef TARGET_AIX_OS |
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56 #define TARGET_AIX_OS 0 |
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57 #endif |
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58 |
| 0 | 59 /* Control whether function entry points use a "dot" symbol when |
| 60 ABI_AIX. */ | |
| 61 #define DOT_SYMBOLS 1 | |
| 62 | |
| 63 /* Default string to use for cpu if not specified. */ | |
| 64 #ifndef TARGET_CPU_DEFAULT | |
| 65 #define TARGET_CPU_DEFAULT ((char *)0) | |
| 66 #endif | |
| 67 | |
| 68 /* If configured for PPC405, support PPC405CR Erratum77. */ | |
| 69 #ifdef CONFIG_PPC405CR | |
| 70 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) | |
| 71 #else | |
| 72 #define PPC405_ERRATUM77 0 | |
| 73 #endif | |
| 74 | |
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75 /* Common ASM definitions used by ASM_SPEC among the various targets for |
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76 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to |
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77 provide the default assembler options if the user uses -mcpu=native, so if |
| 131 | 78 you make changes here, make them also there. PR63177: Do not pass -mpower8 |
| 79 to the assembler if -mpower9-vector was also used. */ | |
| 0 | 80 #define ASM_CPU_SPEC \ |
| 81 "%{!mcpu*: \ | |
| 82 %{mpowerpc64*: -mppc64} \ | |
| 111 | 83 %{!mpowerpc64*: %(asm_default)}} \ |
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84 %{mcpu=native: %(asm_cpu_native)} \ |
| 0 | 85 %{mcpu=cell: -mcell} \ |
| 86 %{mcpu=power3: -mppc64} \ | |
| 87 %{mcpu=power4: -mpower4} \ | |
| 131 | 88 %{mcpu=power5: -mpower5} \ |
| 89 %{mcpu=power5+: -mpower5} \ | |
| 90 %{mcpu=power6: -mpower6 -maltivec} \ | |
| 91 %{mcpu=power6x: -mpower6 -maltivec} \ | |
| 92 %{mcpu=power7: -mpower7} \ | |
| 93 %{mcpu=power8: %{!mpower9-vector: -mpower8}} \ | |
| 94 %{mcpu=power9: -mpower9} \ | |
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95 %{mcpu=a2: -ma2} \ |
| 0 | 96 %{mcpu=powerpc: -mppc} \ |
| 131 | 97 %{mcpu=powerpc64le: -mpower8} \ |
| 0 | 98 %{mcpu=rs64a: -mppc64} \ |
| 99 %{mcpu=401: -mppc} \ | |
| 100 %{mcpu=403: -m403} \ | |
| 101 %{mcpu=405: -m405} \ | |
| 102 %{mcpu=405fp: -m405} \ | |
| 103 %{mcpu=440: -m440} \ | |
| 104 %{mcpu=440fp: -m440} \ | |
| 105 %{mcpu=464: -m440} \ | |
| 106 %{mcpu=464fp: -m440} \ | |
| 131 | 107 %{mcpu=476: -m476} \ |
| 108 %{mcpu=476fp: -m476} \ | |
| 0 | 109 %{mcpu=505: -mppc} \ |
| 110 %{mcpu=601: -m601} \ | |
| 111 %{mcpu=602: -mppc} \ | |
| 112 %{mcpu=603: -mppc} \ | |
| 113 %{mcpu=603e: -mppc} \ | |
| 114 %{mcpu=ec603e: -mppc} \ | |
| 115 %{mcpu=604: -mppc} \ | |
| 116 %{mcpu=604e: -mppc} \ | |
| 117 %{mcpu=620: -mppc64} \ | |
| 118 %{mcpu=630: -mppc64} \ | |
| 119 %{mcpu=740: -mppc} \ | |
| 120 %{mcpu=750: -mppc} \ | |
| 121 %{mcpu=G3: -mppc} \ | |
| 122 %{mcpu=7400: -mppc -maltivec} \ | |
| 123 %{mcpu=7450: -mppc -maltivec} \ | |
| 124 %{mcpu=G4: -mppc -maltivec} \ | |
| 125 %{mcpu=801: -mppc} \ | |
| 126 %{mcpu=821: -mppc} \ | |
| 127 %{mcpu=823: -mppc} \ | |
| 128 %{mcpu=860: -mppc} \ | |
| 129 %{mcpu=970: -mpower4 -maltivec} \ | |
| 130 %{mcpu=G5: -mpower4 -maltivec} \ | |
| 131 %{mcpu=8540: -me500} \ | |
| 132 %{mcpu=8548: -me500} \ | |
| 133 %{mcpu=e300c2: -me300} \ | |
| 134 %{mcpu=e300c3: -me300} \ | |
| 135 %{mcpu=e500mc: -me500mc} \ | |
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136 %{mcpu=e500mc64: -me500mc64} \ |
| 111 | 137 %{mcpu=e5500: -me5500} \ |
| 138 %{mcpu=e6500: -me6500} \ | |
| 0 | 139 %{maltivec: -maltivec} \ |
| 131 | 140 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: -mpower7}} \ |
| 141 %{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: -mpower8}} \ | |
| 142 %{mpower9-vector: %{!mcpu*|mcpu=power8: -mpower9}} \ | |
| 0 | 143 -many" |
| 144 | |
| 145 #define CPP_DEFAULT_SPEC "" | |
| 146 | |
| 147 #define ASM_DEFAULT_SPEC "" | |
| 148 | |
| 149 /* This macro defines names of additional specifications to put in the specs | |
| 150 that can be used in various specifications like CC1_SPEC. Its definition | |
| 151 is an initializer with a subgrouping for each command option. | |
| 152 | |
| 153 Each subgrouping contains a string constant, that defines the | |
| 154 specification name, and a string constant that used by the GCC driver | |
| 155 program. | |
| 156 | |
| 157 Do not define this macro if it does not need to do anything. */ | |
| 158 | |
| 159 #define SUBTARGET_EXTRA_SPECS | |
| 160 | |
| 161 #define EXTRA_SPECS \ | |
| 162 { "cpp_default", CPP_DEFAULT_SPEC }, \ | |
| 163 { "asm_cpu", ASM_CPU_SPEC }, \ | |
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164 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ |
| 0 | 165 { "asm_default", ASM_DEFAULT_SPEC }, \ |
| 166 { "cc1_cpu", CC1_CPU_SPEC }, \ | |
| 167 SUBTARGET_EXTRA_SPECS | |
| 168 | |
| 169 /* -mcpu=native handling only makes sense with compiler running on | |
| 170 an PowerPC chip. If changing this condition, also change | |
| 171 the condition in driver-rs6000.c. */ | |
| 172 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) | |
| 173 /* In driver-rs6000.c. */ | |
| 174 extern const char *host_detect_local_cpu (int argc, const char **argv); | |
| 175 #define EXTRA_SPEC_FUNCTIONS \ | |
| 176 { "local_cpu_detect", host_detect_local_cpu }, | |
| 177 #define HAVE_LOCAL_CPU_DETECT | |
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178 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" |
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179 |
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180 #else |
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181 #define ASM_CPU_NATIVE_SPEC "%(asm_default)" |
| 0 | 182 #endif |
| 183 | |
| 184 #ifndef CC1_CPU_SPEC | |
| 185 #ifdef HAVE_LOCAL_CPU_DETECT | |
| 186 #define CC1_CPU_SPEC \ | |
| 187 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ | |
| 188 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
| 189 #else | |
| 190 #define CC1_CPU_SPEC "" | |
| 191 #endif | |
| 192 #endif | |
| 193 | |
| 194 /* Architecture type. */ | |
| 195 | |
| 196 /* Define TARGET_MFCRF if the target assembler does not support the | |
| 197 optional field operand for mfcr. */ | |
| 198 | |
| 199 #ifndef HAVE_AS_MFCRF | |
| 200 #undef TARGET_MFCRF | |
| 201 #define TARGET_MFCRF 0 | |
| 202 #endif | |
| 203 | |
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204 /* Define TARGET_TLS_MARKERS if the target assembler does not support |
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205 arg markers for __tls_get_addr calls. */ |
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206 #ifndef HAVE_AS_TLS_MARKERS |
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207 #undef TARGET_TLS_MARKERS |
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208 #define TARGET_TLS_MARKERS 0 |
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209 #else |
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210 #define TARGET_TLS_MARKERS tls_markers |
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211 #endif |
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212 |
| 0 | 213 #ifndef TARGET_SECURE_PLT |
| 214 #define TARGET_SECURE_PLT 0 | |
| 215 #endif | |
| 216 | |
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217 #ifndef TARGET_CMODEL |
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218 #define TARGET_CMODEL CMODEL_SMALL |
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219 #endif |
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220 |
| 0 | 221 #define TARGET_32BIT (! TARGET_64BIT) |
| 222 | |
| 223 #ifndef HAVE_AS_TLS | |
| 224 #define HAVE_AS_TLS 0 | |
| 225 #endif | |
| 226 | |
| 111 | 227 #ifndef TARGET_LINK_STACK |
| 228 #define TARGET_LINK_STACK 0 | |
| 229 #endif | |
| 230 | |
| 231 #ifndef SET_TARGET_LINK_STACK | |
| 232 #define SET_TARGET_LINK_STACK(X) do { } while (0) | |
| 233 #endif | |
| 234 | |
| 235 #ifndef TARGET_FLOAT128_ENABLE_TYPE | |
| 236 #define TARGET_FLOAT128_ENABLE_TYPE 0 | |
| 237 #endif | |
| 238 | |
| 0 | 239 /* Return 1 for a symbol ref for a thread-local storage symbol. */ |
| 240 #define RS6000_SYMBOL_REF_TLS_P(RTX) \ | |
| 241 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) | |
| 242 | |
| 243 #ifdef IN_LIBGCC2 | |
| 244 /* For libgcc2 we make sure this is a compile time constant */ | |
| 245 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) | |
| 246 #undef TARGET_POWERPC64 | |
| 247 #define TARGET_POWERPC64 1 | |
| 248 #else | |
| 249 #undef TARGET_POWERPC64 | |
| 250 #define TARGET_POWERPC64 0 | |
| 251 #endif | |
| 252 #else | |
| 253 /* The option machinery will define this. */ | |
| 254 #endif | |
| 255 | |
| 131 | 256 #define TARGET_DEFAULT (MASK_MULTIPLE) |
| 0 | 257 |
| 258 /* Define generic processor types based upon current deployment. */ | |
| 259 #define PROCESSOR_COMMON PROCESSOR_PPC601 | |
| 260 #define PROCESSOR_POWERPC PROCESSOR_PPC604 | |
| 261 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A | |
| 262 | |
| 263 /* Define the default processor. This is overridden by other tm.h files. */ | |
| 111 | 264 #define PROCESSOR_DEFAULT PROCESSOR_PPC603 |
| 0 | 265 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A |
| 266 | |
| 111 | 267 /* Specify the dialect of assembler to use. Only new mnemonics are supported |
| 268 starting with GCC 4.8, i.e. just one dialect, but for backwards | |
| 269 compatibility with older inline asm ASSEMBLER_DIALECT needs to be | |
| 270 defined. */ | |
| 271 #define ASSEMBLER_DIALECT 1 | |
| 0 | 272 |
| 273 /* Debug support */ | |
|
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274 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */ |
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275 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */ |
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276 #define MASK_DEBUG_REG 0x04 /* debug register handling */ |
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277 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ |
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278 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */ |
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279 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ |
| 111 | 280 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ |
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281 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ |
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282 | MASK_DEBUG_ARG \ |
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283 | MASK_DEBUG_REG \ |
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284 | MASK_DEBUG_ADDR \ |
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285 | MASK_DEBUG_COST \ |
| 111 | 286 | MASK_DEBUG_TARGET \ |
| 287 | MASK_DEBUG_BUILTIN) | |
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288 |
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289 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) |
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290 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) |
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291 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) |
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292 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) |
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293 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) |
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294 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) |
| 111 | 295 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) |
| 296 | |
| 297 /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM | |
| 298 long double format that uses a pair of doubles, or IEEE 128-bit floating | |
| 299 point. KFmode was added as a way to represent IEEE 128-bit floating point, | |
| 300 even if the default for long double is the IBM long double format. | |
| 301 Similarly IFmode is the IBM long double format even if the default is IEEE | |
| 302 128-bit. Don't allow IFmode if -msoft-float. */ | |
| 303 #define FLOAT128_IEEE_P(MODE) \ | |
| 131 | 304 ((TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ |
| 305 && ((MODE) == TFmode || (MODE) == TCmode)) \ | |
| 111 | 306 || ((MODE) == KFmode) || ((MODE) == KCmode)) |
| 307 | |
| 308 #define FLOAT128_IBM_P(MODE) \ | |
| 131 | 309 ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ |
| 310 && ((MODE) == TFmode || (MODE) == TCmode)) \ | |
| 111 | 311 || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode))) |
| 312 | |
| 313 /* Helper macros to say whether a 128-bit floating point type can go in a | |
| 314 single vector register, or whether it needs paired scalar values. */ | |
| 315 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)) | |
| 316 | |
| 317 #define FLOAT128_2REG_P(MODE) \ | |
| 318 (FLOAT128_IBM_P (MODE) \ | |
| 319 || ((MODE) == TDmode) \ | |
| 320 || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))) | |
| 321 | |
| 322 /* Return true for floating point that does not use a vector register. */ | |
| 323 #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \ | |
| 324 (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE)) | |
| 325 | |
| 326 /* Describe the vector unit used for arithmetic operations. */ | |
|
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327 extern enum rs6000_vector rs6000_vector_unit[]; |
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328 |
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329 #define VECTOR_UNIT_NONE_P(MODE) \ |
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330 (rs6000_vector_unit[(MODE)] == VECTOR_NONE) |
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331 |
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332 #define VECTOR_UNIT_VSX_P(MODE) \ |
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333 (rs6000_vector_unit[(MODE)] == VECTOR_VSX) |
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334 |
| 111 | 335 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \ |
| 336 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR) | |
| 337 | |
|
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338 #define VECTOR_UNIT_ALTIVEC_P(MODE) \ |
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339 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) |
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340 |
| 111 | 341 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \ |
| 342 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ | |
| 343 (int)VECTOR_VSX, \ | |
| 344 (int)VECTOR_P8_VECTOR)) | |
| 345 | |
| 346 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either | |
| 347 altivec (VMX) or VSX vector instructions. P8 vector support is upwards | |
| 348 compatible, so allow it as well, rather than changing all of the uses of the | |
| 349 macro. */ | |
|
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350 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ |
| 111 | 351 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ |
| 352 (int)VECTOR_ALTIVEC, \ | |
| 353 (int)VECTOR_P8_VECTOR)) | |
|
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354 |
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355 /* Describe whether to use VSX loads or Altivec loads. For now, just use the |
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356 same unit as the vector unit we are using, but we may want to migrate to |
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357 using VSX style loads even for types handled by altivec. */ |
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358 extern enum rs6000_vector rs6000_vector_mem[]; |
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359 |
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360 #define VECTOR_MEM_NONE_P(MODE) \ |
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361 (rs6000_vector_mem[(MODE)] == VECTOR_NONE) |
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362 |
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363 #define VECTOR_MEM_VSX_P(MODE) \ |
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364 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) |
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365 |
| 111 | 366 #define VECTOR_MEM_P8_VECTOR_P(MODE) \ |
| 367 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) | |
| 368 | |
|
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369 #define VECTOR_MEM_ALTIVEC_P(MODE) \ |
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370 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) |
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371 |
| 111 | 372 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \ |
| 373 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ | |
| 374 (int)VECTOR_VSX, \ | |
| 375 (int)VECTOR_P8_VECTOR)) | |
| 376 | |
|
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377 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ |
| 111 | 378 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ |
| 379 (int)VECTOR_ALTIVEC, \ | |
| 380 (int)VECTOR_P8_VECTOR)) | |
|
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381 |
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382 /* Return the alignment of a given vector type, which is set based on the |
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383 vector unit use. VSX for instance can load 32 or 64 bit aligned words |
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384 without problems, while Altivec requires 128-bit aligned vectors. */ |
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385 extern int rs6000_vector_align[]; |
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386 |
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387 #define VECTOR_ALIGN(MODE) \ |
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388 ((rs6000_vector_align[(MODE)] != 0) \ |
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389 ? rs6000_vector_align[(MODE)] \ |
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390 : (int)GET_MODE_BITSIZE ((MODE))) |
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391 |
| 111 | 392 /* Element number of the 64-bit value in a 128-bit vector that can be accessed |
| 393 with scalar instructions. */ | |
| 394 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1) | |
| 395 | |
| 396 /* Element number of the 64-bit value in a 128-bit vector that can be accessed | |
| 397 with the ISA 3.0 MFVSRLD instructions. */ | |
| 398 #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0) | |
| 399 | |
| 0 | 400 /* Alignment options for fields in structures for sub-targets following |
| 401 AIX-like ABI. | |
| 402 ALIGN_POWER word-aligns FP doubles (default AIX ABI). | |
| 403 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). | |
| 404 | |
| 405 Override the macro definitions when compiling libobjc to avoid undefined | |
| 406 reference to rs6000_alignment_flags due to library's use of GCC alignment | |
| 407 macros which use the macros below. */ | |
| 408 | |
| 409 #ifndef IN_TARGET_LIBS | |
| 410 #define MASK_ALIGN_POWER 0x00000000 | |
| 411 #define MASK_ALIGN_NATURAL 0x00000001 | |
| 412 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) | |
| 413 #else | |
| 414 #define TARGET_ALIGN_NATURAL 0 | |
| 415 #endif | |
| 416 | |
| 131 | 417 /* We use values 126..128 to pick the appropriate long double type (IFmode, |
| 418 KFmode, TFmode). */ | |
| 419 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64) | |
| 0 | 420 #define TARGET_IEEEQUAD rs6000_ieeequad |
| 421 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi | |
|
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422 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) |
| 0 | 423 |
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424 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. |
| 131 | 425 Enable 32-bit fcfid's on any of the switches for newer ISA machines. */ |
| 111 | 426 #define TARGET_FCFID (TARGET_POWERPC64 \ |
| 427 || TARGET_PPC_GPOPT /* 970/power4 */ \ | |
| 428 || TARGET_POPCNTB /* ISA 2.02 */ \ | |
| 429 || TARGET_CMPB /* ISA 2.05 */ \ | |
| 131 | 430 || TARGET_POPCNTD) /* ISA 2.06 */ |
|
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431 |
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432 #define TARGET_FCTIDZ TARGET_FCFID |
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433 #define TARGET_STFIWX TARGET_PPC_GFXOPT |
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434 #define TARGET_LFIWAX TARGET_CMPB |
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435 #define TARGET_LFIWZX TARGET_POPCNTD |
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436 #define TARGET_FCFIDS TARGET_POPCNTD |
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437 #define TARGET_FCFIDU TARGET_POPCNTD |
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438 #define TARGET_FCFIDUS TARGET_POPCNTD |
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439 #define TARGET_FCTIDUZ TARGET_POPCNTD |
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440 #define TARGET_FCTIWUZ TARGET_POPCNTD |
| 111 | 441 #define TARGET_CTZ TARGET_MODULO |
| 442 #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64) | |
| 443 #define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64) | |
| 444 | |
| 445 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) | |
| 446 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) | |
| 447 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64) | |
| 448 #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ | |
| 449 && TARGET_POWERPC64) | |
| 450 #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ | |
| 451 && TARGET_POWERPC64) | |
| 452 | |
| 453 /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */ | |
| 454 #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT | |
| 455 #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT) | |
| 456 | |
| 457 /* This wants to be set for p8 and newer. On p7, overlapping unaligned | |
| 458 loads are slow. */ | |
| 459 #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX | |
| 460 | |
| 461 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present | |
| 462 in power7, so conditionalize them on p8 features. TImode syncs need quad | |
| 463 memory support. */ | |
| 464 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \ | |
| 465 || TARGET_QUAD_MEMORY_ATOMIC \ | |
| 466 || TARGET_DIRECT_MOVE) | |
| 467 | |
| 468 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC | |
| 469 | |
| 470 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need | |
| 471 to allocate the SDmode stack slot to get the value into the proper location | |
| 472 in the register. */ | |
| 473 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP) | |
| 474 | |
| 475 /* ISA 3.0 has new min/max functions that don't need fast math that are being | |
| 476 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct | |
| 477 answers if the arguments are not in the normal range. */ | |
| 131 | 478 #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ |
| 479 && (TARGET_P9_MINMAX || !flag_trapping_math)) | |
| 111 | 480 |
| 481 /* In switching from using target_flags to using rs6000_isa_flags, the options | |
| 482 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map | |
| 483 OPTION_MASK_<xxx> back into MASK_<xxx>. */ | |
| 484 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC | |
| 485 #define MASK_CMPB OPTION_MASK_CMPB | |
| 486 #define MASK_CRYPTO OPTION_MASK_CRYPTO | |
| 487 #define MASK_DFP OPTION_MASK_DFP | |
| 488 #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE | |
| 489 #define MASK_DLMZB OPTION_MASK_DLMZB | |
| 490 #define MASK_EABI OPTION_MASK_EABI | |
| 491 #define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD | |
| 492 #define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW | |
| 493 #define MASK_FPRND OPTION_MASK_FPRND | |
| 494 #define MASK_P8_FUSION OPTION_MASK_P8_FUSION | |
| 495 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT | |
| 496 #define MASK_HTM OPTION_MASK_HTM | |
| 497 #define MASK_ISEL OPTION_MASK_ISEL | |
| 498 #define MASK_MFCRF OPTION_MASK_MFCRF | |
| 499 #define MASK_MFPGPR OPTION_MASK_MFPGPR | |
| 500 #define MASK_MULHW OPTION_MASK_MULHW | |
| 501 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE | |
| 502 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE | |
| 503 #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR | |
| 504 #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR | |
| 505 #define MASK_P9_MISC OPTION_MASK_P9_MISC | |
| 506 #define MASK_POPCNTB OPTION_MASK_POPCNTB | |
| 507 #define MASK_POPCNTD OPTION_MASK_POPCNTD | |
| 508 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT | |
| 509 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT | |
| 510 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION | |
| 511 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT | |
| 512 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN | |
| 513 #define MASK_UPDATE OPTION_MASK_UPDATE | |
| 514 #define MASK_VSX OPTION_MASK_VSX | |
| 515 | |
| 516 #ifndef IN_LIBGCC2 | |
| 517 #define MASK_POWERPC64 OPTION_MASK_POWERPC64 | |
| 518 #endif | |
| 519 | |
| 520 #ifdef TARGET_64BIT | |
| 521 #define MASK_64BIT OPTION_MASK_64BIT | |
| 522 #endif | |
| 523 | |
| 524 #ifdef TARGET_LITTLE_ENDIAN | |
| 525 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN | |
| 526 #endif | |
| 527 | |
| 528 #ifdef TARGET_REGNAMES | |
| 529 #define MASK_REGNAMES OPTION_MASK_REGNAMES | |
| 530 #endif | |
| 531 | |
| 532 #ifdef TARGET_PROTOTYPE | |
| 533 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE | |
| 534 #endif | |
| 535 | |
| 536 #ifdef TARGET_MODULO | |
| 537 #define RS6000_BTM_MODULO OPTION_MASK_MODULO | |
| 538 #endif | |
| 539 | |
| 540 | |
| 541 /* For power systems, we want to enable Altivec and VSX builtins even if the | |
| 542 user did not use -maltivec or -mvsx to allow the builtins to be used inside | |
| 543 of #pragma GCC target or the target attribute to change the code level for a | |
| 131 | 544 given system. */ |
| 111 | 545 |
| 131 | 546 #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \ |
| 547 || TARGET_PPC_GPOPT /* 970/power4 */ \ | |
| 548 || TARGET_POPCNTB /* ISA 2.02 */ \ | |
| 549 || TARGET_CMPB /* ISA 2.05 */ \ | |
| 550 || TARGET_POPCNTD /* ISA 2.06 */ \ | |
| 551 || TARGET_ALTIVEC \ | |
| 552 || TARGET_VSX \ | |
| 553 || TARGET_HARD_FLOAT) | |
| 111 | 554 |
| 555 /* E500 cores only support plain "sync", not lwsync. */ | |
| 556 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ | |
| 557 || rs6000_cpu == PROCESSOR_PPC8548) | |
| 558 | |
| 559 | |
| 131 | 560 /* Which machine supports the various reciprocal estimate instructions. */ |
| 561 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT) | |
| 111 | 562 |
| 131 | 563 #define TARGET_FRE (TARGET_HARD_FLOAT \ |
|
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564 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) |
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565 |
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566 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ |
| 131 | 567 && TARGET_PPC_GFXOPT) |
|
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568 |
| 131 | 569 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \ |
| 570 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) | |
| 111 | 571 |
| 572 /* Macro to say whether we can do optimizations where we need to do parts of | |
| 573 the calculation in 64-bit GPRs and then is transfered to the vector | |
| 131 | 574 registers. */ |
| 111 | 575 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \ |
| 576 && TARGET_P8_VECTOR \ | |
| 131 | 577 && TARGET_POWERPC64) |
| 111 | 578 |
|
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579 /* Whether the various reciprocal divide/square root estimate instructions |
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580 exist, and whether we should automatically generate code for the instruction |
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581 by default. */ |
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582 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ |
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583 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */ |
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584 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */ |
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585 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */ |
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586 |
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587 extern unsigned char rs6000_recip_bits[]; |
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588 |
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589 #define RS6000_RECIP_HAVE_RE_P(MODE) \ |
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590 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE) |
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591 |
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592 #define RS6000_RECIP_AUTO_RE_P(MODE) \ |
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593 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE) |
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594 |
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595 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \ |
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596 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE) |
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597 |
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598 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ |
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599 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) |
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600 |
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601 /* The default CPU for TARGET_OPTION_OVERRIDE. */ |
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602 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT |
| 0 | 603 |
| 604 /* Target pragma. */ | |
| 605 #define REGISTER_TARGET_PRAGMAS() do { \ | |
| 606 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ | |
|
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607 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ |
| 0 | 608 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ |
| 111 | 609 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \ |
| 0 | 610 } while (0) |
| 611 | |
| 612 /* Target #defines. */ | |
| 613 #define TARGET_CPU_CPP_BUILTINS() \ | |
| 614 rs6000_cpu_cpp_builtins (pfile) | |
| 615 | |
| 616 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order | |
| 617 we're compiling for. Some configurations may need to override it. */ | |
| 618 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ | |
| 619 do \ | |
| 620 { \ | |
| 621 if (BYTES_BIG_ENDIAN) \ | |
| 622 { \ | |
| 623 builtin_define ("__BIG_ENDIAN__"); \ | |
| 624 builtin_define ("_BIG_ENDIAN"); \ | |
| 625 builtin_assert ("machine=bigendian"); \ | |
| 626 } \ | |
| 627 else \ | |
| 628 { \ | |
| 629 builtin_define ("__LITTLE_ENDIAN__"); \ | |
| 630 builtin_define ("_LITTLE_ENDIAN"); \ | |
| 631 builtin_assert ("machine=littleendian"); \ | |
| 632 } \ | |
| 633 } \ | |
| 634 while (0) | |
| 635 | |
| 636 /* Target machine storage layout. */ | |
| 637 | |
| 638 /* Define this macro if it is advisable to hold scalars in registers | |
| 639 in a wider mode than that declared by the program. In such cases, | |
| 640 the value is constrained to be within the bounds of the declared | |
| 641 type, but kept valid in the wider mode. The signedness of the | |
| 642 extension may differ from that of the type. */ | |
| 643 | |
| 644 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ | |
| 645 if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
| 111 | 646 && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \ |
| 0 | 647 (MODE) = TARGET_32BIT ? SImode : DImode; |
| 648 | |
| 649 /* Define this if most significant bit is lowest numbered | |
| 650 in instructions that operate on numbered bit-fields. */ | |
| 651 /* That is true on RS/6000. */ | |
| 652 #define BITS_BIG_ENDIAN 1 | |
| 653 | |
| 654 /* Define this if most significant byte of a word is the lowest numbered. */ | |
| 655 /* That is true on RS/6000. */ | |
| 656 #define BYTES_BIG_ENDIAN 1 | |
| 657 | |
| 658 /* Define this if most significant word of a multiword number is lowest | |
| 659 numbered. | |
| 660 | |
| 661 For RS/6000 we can decide arbitrarily since there are no machine | |
| 662 instructions for them. Might as well be consistent with bits and bytes. */ | |
| 663 #define WORDS_BIG_ENDIAN 1 | |
| 664 | |
| 111 | 665 /* This says that for the IBM long double the larger magnitude double |
| 666 comes first. It's really a two element double array, and arrays | |
| 667 don't index differently between little- and big-endian. */ | |
| 668 #define LONG_DOUBLE_LARGE_FIRST 1 | |
| 669 | |
| 0 | 670 #define MAX_BITS_PER_WORD 64 |
| 671 | |
| 672 /* Width of a word, in units (bytes). */ | |
| 673 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) | |
| 674 #ifdef IN_LIBGCC2 | |
| 675 #define MIN_UNITS_PER_WORD UNITS_PER_WORD | |
| 676 #else | |
| 677 #define MIN_UNITS_PER_WORD 4 | |
| 678 #endif | |
| 679 #define UNITS_PER_FP_WORD 8 | |
| 680 #define UNITS_PER_ALTIVEC_WORD 16 | |
|
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681 #define UNITS_PER_VSX_WORD 16 |
| 0 | 682 |
| 683 /* Type used for ptrdiff_t, as a string used in a declaration. */ | |
| 684 #define PTRDIFF_TYPE "int" | |
| 685 | |
| 686 /* Type used for size_t, as a string used in a declaration. */ | |
| 687 #define SIZE_TYPE "long unsigned int" | |
| 688 | |
| 689 /* Type used for wchar_t, as a string used in a declaration. */ | |
| 690 #define WCHAR_TYPE "short unsigned int" | |
| 691 | |
| 692 /* Width of wchar_t in bits. */ | |
| 693 #define WCHAR_TYPE_SIZE 16 | |
| 694 | |
| 695 /* A C expression for the size in bits of the type `short' on the | |
| 696 target machine. If you don't define this, the default is half a | |
| 697 word. (If this would be less than one storage unit, it is | |
| 698 rounded up to one unit.) */ | |
| 699 #define SHORT_TYPE_SIZE 16 | |
| 700 | |
| 701 /* A C expression for the size in bits of the type `int' on the | |
| 702 target machine. If you don't define this, the default is one | |
| 703 word. */ | |
| 704 #define INT_TYPE_SIZE 32 | |
| 705 | |
| 706 /* A C expression for the size in bits of the type `long' on the | |
| 707 target machine. If you don't define this, the default is one | |
| 708 word. */ | |
| 709 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) | |
| 710 | |
| 711 /* A C expression for the size in bits of the type `long long' on the | |
| 712 target machine. If you don't define this, the default is two | |
| 713 words. */ | |
| 714 #define LONG_LONG_TYPE_SIZE 64 | |
| 715 | |
| 716 /* A C expression for the size in bits of the type `float' on the | |
| 717 target machine. If you don't define this, the default is one | |
| 718 word. */ | |
| 719 #define FLOAT_TYPE_SIZE 32 | |
| 720 | |
| 721 /* A C expression for the size in bits of the type `double' on the | |
| 722 target machine. If you don't define this, the default is two | |
| 723 words. */ | |
| 724 #define DOUBLE_TYPE_SIZE 64 | |
| 725 | |
| 131 | 726 /* A C expression for the size in bits of the type `long double' on the target |
| 727 machine. If you don't define this, the default is two words. */ | |
| 0 | 728 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size |
| 729 | |
| 730 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ | |
| 731 #define WIDEST_HARDWARE_FP_SIZE 64 | |
| 732 | |
| 733 /* Width in bits of a pointer. | |
| 734 See also the macro `Pmode' defined below. */ | |
|
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735 extern unsigned rs6000_pointer_size; |
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736 #define POINTER_SIZE rs6000_pointer_size |
| 0 | 737 |
| 738 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
| 739 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) | |
| 740 | |
| 741 /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
|
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742 #define STACK_BOUNDARY \ |
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743 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ |
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744 ? 64 : 128) |
| 0 | 745 |
| 746 /* Allocation boundary (in *bits*) for the code of a function. */ | |
| 747 #define FUNCTION_BOUNDARY 32 | |
| 748 | |
| 749 /* No data type wants to be aligned rounder than this. */ | |
| 750 #define BIGGEST_ALIGNMENT 128 | |
| 751 | |
| 752 /* Alignment of field after `int : 0' in a structure. */ | |
| 753 #define EMPTY_FIELD_BOUNDARY 32 | |
| 754 | |
| 755 /* Every structure's size must be a multiple of this. */ | |
| 756 #define STRUCTURE_SIZE_BOUNDARY 8 | |
| 757 | |
| 758 /* A bit-field declared as `int' forces `int' alignment for the struct. */ | |
| 759 #define PCC_BITFIELD_TYPE_MATTERS 1 | |
| 760 | |
| 111 | 761 enum data_align { align_abi, align_opt, align_both }; |
| 762 | |
| 763 /* A C expression to compute the alignment for a variables in the | |
| 764 local store. TYPE is the data type, and ALIGN is the alignment | |
| 765 that the object would ordinarily have. */ | |
| 766 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
| 767 rs6000_data_alignment (TYPE, ALIGN, align_both) | |
| 768 | |
| 769 /* Make arrays of chars word-aligned for the same reasons. */ | |
| 770 #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
| 771 rs6000_data_alignment (TYPE, ALIGN, align_opt) | |
| 772 | |
| 773 /* Align vectors to 128 bits. */ | |
| 774 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ | |
| 775 rs6000_data_alignment (TYPE, ALIGN, align_abi) | |
| 0 | 776 |
| 777 /* Nonzero if move instructions will actually fail to work | |
| 778 when given unaligned data. */ | |
| 779 #define STRICT_ALIGNMENT 0 | |
| 780 | |
| 781 /* Standard register usage. */ | |
| 782 | |
| 783 /* Number of actual hardware registers. | |
| 784 The hardware registers are assigned numbers for the compiler | |
| 785 from 0 to just below FIRST_PSEUDO_REGISTER. | |
| 786 All registers that the compiler knows about must be given numbers, | |
| 787 even those that are not normally considered general registers. | |
| 788 | |
| 789 RS/6000 has 32 fixed-point registers, 32 floating-point registers, | |
| 111 | 790 a count register, a link register, and 8 condition register fields, |
| 791 which we view here as separate registers. AltiVec adds 32 vector | |
| 792 registers and a VRsave register. | |
| 0 | 793 |
| 794 In addition, the difference between the frame and argument pointers is | |
| 795 a function of the number of registers saved, so we need to have a | |
| 796 register for AP that will later be eliminated in favor of SP or FP. | |
| 797 This is a normal register, but it is fixed. | |
| 798 | |
| 799 We also create a pseudo register for float/int conversions, that will | |
| 800 really represent the memory location used. It is represented here as | |
| 801 a register, in order to work around problems in allocating stack storage | |
| 802 in inline functions. | |
| 803 | |
| 804 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame | |
| 111 | 805 pointer, which is eventually eliminated in favor of SP or FP. |
| 806 | |
| 807 The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */ | |
| 808 | |
| 809 #define FIRST_PSEUDO_REGISTER 115 | |
| 0 | 810 |
| 811 /* This must be included for pre gcc 3.0 glibc compatibility. */ | |
| 812 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 | |
| 813 | |
| 111 | 814 /* The sfp register and 3 HTM registers |
| 815 aren't included in DWARF_FRAME_REGISTERS. */ | |
| 816 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4) | |
| 0 | 817 |
| 818 /* Use standard DWARF numbering for DWARF debugging information. */ | |
| 111 | 819 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0) |
| 0 | 820 |
| 821 /* Use gcc hard register numbering for eh_frame. */ | |
| 822 #define DWARF_FRAME_REGNUM(REGNO) (REGNO) | |
| 823 | |
| 824 /* Map register numbers held in the call frame info that gcc has | |
| 825 collected using DWARF_FRAME_REGNUM to those that should be output in | |
| 111 | 826 .debug_frame and .eh_frame. */ |
| 827 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ | |
| 828 rs6000_dbx_register_number ((REGNO), (FOR_EH)? 2 : 1) | |
| 0 | 829 |
| 830 /* 1 for registers that have pervasive standard uses | |
| 831 and are not available for the register allocator. | |
| 832 | |
| 833 On RS/6000, r1 is used for the stack. On Darwin, r2 is available | |
| 834 as a local register; for all other OS's r2 is the TOC pointer. | |
| 835 | |
| 836 On System V implementations, r13 is fixed and not available for use. */ | |
| 837 | |
| 838 #define FIXED_REGISTERS \ | |
| 839 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ | |
| 840 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 841 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 842 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 111 | 843 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ |
| 0 | 844 /* AltiVec registers. */ \ |
| 845 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 846 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 847 1, 1 \ | |
| 111 | 848 , 1, 1, 1, 1 \ |
| 0 | 849 } |
| 850 | |
| 851 /* 1 for registers not available across function calls. | |
| 852 These must include the FIXED_REGISTERS and also any | |
| 853 registers that can be used without being saved. | |
| 854 The latter must include the registers where values are returned | |
| 855 and the register where structure-value addresses are passed. | |
| 856 Aside from that, you can include as many other registers as you like. */ | |
| 857 | |
| 858 #define CALL_USED_REGISTERS \ | |
| 859 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ | |
| 860 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 861 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
| 862 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 863 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ | |
| 864 /* AltiVec registers. */ \ | |
| 865 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 866 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 867 1, 1 \ | |
| 111 | 868 , 1, 1, 1, 1 \ |
| 0 | 869 } |
| 870 | |
| 871 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that | |
| 872 the entire set of `FIXED_REGISTERS' be included. | |
| 873 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). | |
| 874 This macro is optional. If not specified, it defaults to the value | |
| 875 of `CALL_USED_REGISTERS'. */ | |
| 876 | |
| 877 #define CALL_REALLY_USED_REGISTERS \ | |
| 878 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ | |
| 879 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 880 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
| 881 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 111 | 882 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ |
| 0 | 883 /* AltiVec registers. */ \ |
| 884 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 885 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 886 0, 0 \ | |
| 111 | 887 , 0, 0, 0, 0 \ |
| 0 | 888 } |
| 889 | |
| 890 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) | |
| 891 | |
| 892 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) | |
| 111 | 893 #define FIRST_SAVED_FP_REGNO (14+32) |
| 894 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13) | |
| 0 | 895 |
| 896 /* List the order in which to allocate registers. Each register must be | |
| 897 listed once, even those in FIXED_REGISTERS. | |
| 898 | |
| 899 We allocate in the following order: | |
| 900 fp0 (not saved or used for anything) | |
| 901 fp13 - fp2 (not saved; incoming fp arg registers) | |
| 902 fp1 (not saved; return value) | |
| 903 fp31 - fp14 (saved; order given to save least number) | |
| 111 | 904 cr7, cr5 (not saved or special) |
| 905 cr6 (not saved, but used for vector operations) | |
| 0 | 906 cr1 (not saved, but used for FP operations) |
| 907 cr0 (not saved, but used for arithmetic operations) | |
| 908 cr4, cr3, cr2 (saved) | |
| 111 | 909 r9 (not saved; best for TImode) |
| 910 r10, r8-r4 (not saved; highest first for less conflict with params) | |
| 911 r3 (not saved; return value register) | |
| 912 r11 (not saved; later alloc to help shrink-wrap) | |
| 0 | 913 r0 (not saved; cannot be base reg) |
| 914 r31 - r13 (saved; order given to save least number) | |
| 915 r12 (not saved; if used for DImode or DFmode would use r13) | |
| 916 ctr (not saved; when we have the choice ctr is better) | |
| 917 lr (saved) | |
| 111 | 918 r1, r2, ap, ca (fixed) |
| 0 | 919 v0 - v1 (not saved or used for anything) |
| 920 v13 - v3 (not saved; incoming vector arg registers) | |
| 921 v2 (not saved; incoming vector arg reg; return value) | |
| 922 v19 - v14 (not saved or used for anything) | |
| 923 v31 - v20 (saved; order given to save least number) | |
| 924 vrsave, vscr (fixed) | |
| 925 sfp (fixed) | |
| 111 | 926 tfhar (fixed) |
| 927 tfiar (fixed) | |
| 928 texasr (fixed) | |
| 0 | 929 */ |
| 930 | |
| 931 #if FIXED_R2 == 1 | |
| 932 #define MAYBE_R2_AVAILABLE | |
| 933 #define MAYBE_R2_FIXED 2, | |
| 934 #else | |
| 935 #define MAYBE_R2_AVAILABLE 2, | |
| 936 #define MAYBE_R2_FIXED | |
| 937 #endif | |
| 938 | |
| 111 | 939 #if FIXED_R13 == 1 |
| 940 #define EARLY_R12 12, | |
| 941 #define LATE_R12 | |
| 942 #else | |
| 943 #define EARLY_R12 | |
| 944 #define LATE_R12 12, | |
| 945 #endif | |
| 946 | |
| 0 | 947 #define REG_ALLOC_ORDER \ |
| 948 {32, \ | |
| 111 | 949 /* move fr13 (ie 45) later, so if we need TFmode, it does */ \ |
| 950 /* not use fr14 which is a saved register. */ \ | |
| 951 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \ | |
| 0 | 952 33, \ |
| 953 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ | |
| 954 50, 49, 48, 47, 46, \ | |
| 131 | 955 68, 75, 73, 74, 69, 72, 71, 70, \ |
| 111 | 956 MAYBE_R2_AVAILABLE \ |
| 957 9, 10, 8, 7, 6, 5, 4, \ | |
| 958 3, EARLY_R12 11, 0, \ | |
| 0 | 959 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ |
| 111 | 960 18, 17, 16, 15, 14, 13, LATE_R12 \ |
| 961 66, 65, \ | |
| 962 1, MAYBE_R2_FIXED 67, 76, \ | |
| 0 | 963 /* AltiVec registers. */ \ |
| 964 77, 78, \ | |
| 965 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ | |
| 966 79, \ | |
| 967 96, 95, 94, 93, 92, 91, \ | |
| 968 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ | |
| 969 109, 110, \ | |
| 111 | 970 111, 112, 113, 114 \ |
| 0 | 971 } |
| 972 | |
| 973 /* True if register is floating-point. */ | |
| 974 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
| 975 | |
| 976 /* True if register is a condition register. */ | |
| 977 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) | |
| 978 | |
| 979 /* True if register is a condition register, but not cr0. */ | |
| 980 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) | |
| 981 | |
| 982 /* True if register is an integer register. */ | |
| 983 #define INT_REGNO_P(N) \ | |
| 984 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) | |
| 985 | |
|
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986 /* True if register is the CA register. */ |
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987 #define CA_REGNO_P(N) ((N) == CA_REGNO) |
| 0 | 988 |
| 989 /* True if register is an AltiVec register. */ | |
| 990 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) | |
| 991 | |
|
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992 /* True if register is a VSX register. */ |
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993 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) |
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994 |
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995 /* Alternate name for any vector register supporting floating point, no matter |
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996 which instruction set(s) are available. */ |
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997 #define VFLOAT_REGNO_P(N) \ |
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998 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) |
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999 |
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1000 /* Alternate name for any vector register supporting integer, no matter which |
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1001 instruction set(s) are available. */ |
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1002 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) |
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1003 |
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1004 /* Alternate name for any vector register supporting logical operations, no |
| 111 | 1005 matter which instruction set(s) are available. Allow GPRs as well as the |
| 1006 vector registers. */ | |
| 1007 #define VLOGICAL_REGNO_P(N) \ | |
| 1008 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \ | |
| 1009 || (TARGET_VSX && FP_REGNO_P (N))) \ | |
|
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1010 |
|
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1011 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate |
| 111 | 1012 enough space to account for vectors in FP regs. However, TFmode/TDmode |
| 1013 should not use VSX instructions to do a caller save. */ | |
| 1014 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ | |
| 1015 ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \ | |
| 1016 ? (MODE) \ | |
| 1017 : TARGET_VSX \ | |
| 1018 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ | |
| 1019 && FP_REGNO_P (REGNO) \ | |
| 1020 ? V2DFmode \ | |
| 1021 : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \ | |
| 1022 ? DFmode \ | |
| 1023 : (MODE) == TDmode && FP_REGNO_P (REGNO) \ | |
| 1024 ? DImode \ | |
|
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1025 : choose_hard_reg_mode ((REGNO), (NREGS), false)) |
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1026 |
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1027 #define VSX_VECTOR_MODE(MODE) \ |
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1028 ((MODE) == V4SFmode \ |
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1029 || (MODE) == V2DFmode) \ |
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1030 |
| 111 | 1031 /* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not |
| 1032 really a vector, but we want to treat it as a vector for moves, and | |
| 1033 such. */ | |
| 1034 | |
| 1035 #define ALTIVEC_VECTOR_MODE(MODE) \ | |
| 1036 ((MODE) == V16QImode \ | |
| 1037 || (MODE) == V8HImode \ | |
| 1038 || (MODE) == V4SFmode \ | |
| 1039 || (MODE) == V4SImode \ | |
| 1040 || FLOAT128_VECTOR_P (MODE)) | |
| 1041 | |
| 1042 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ | |
| 1043 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ | |
| 1044 || (MODE) == V2DImode || (MODE) == V1TImode) | |
| 0 | 1045 |
| 1046 /* Post-reload, we can't use any new AltiVec registers, as we already | |
| 1047 emitted the vrsave mask. */ | |
| 1048 | |
| 1049 #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
| 1050 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) | |
| 1051 | |
| 1052 /* Specify the cost of a branch insn; roughly the number of extra insns that | |
| 1053 should be added to avoid a branch. | |
| 1054 | |
| 1055 Set this to 3 on the RS/6000 since that is roughly the average cost of an | |
| 1056 unscheduled conditional branch. */ | |
| 1057 | |
| 1058 #define BRANCH_COST(speed_p, predictable_p) 3 | |
| 1059 | |
| 1060 /* Override BRANCH_COST heuristic which empirically produces worse | |
| 1061 performance for removing short circuiting from the logical ops. */ | |
| 1062 | |
| 1063 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 | |
| 1064 | |
| 1065 /* Specify the registers used for certain standard purposes. | |
| 1066 The values of these macros are register numbers. */ | |
| 1067 | |
| 1068 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ | |
| 1069 /* #define PC_REGNUM */ | |
| 1070 | |
| 1071 /* Register to use for pushing function arguments. */ | |
| 1072 #define STACK_POINTER_REGNUM 1 | |
| 1073 | |
| 1074 /* Base register for access to local variables of the function. */ | |
| 1075 #define HARD_FRAME_POINTER_REGNUM 31 | |
| 1076 | |
| 1077 /* Base register for access to local variables of the function. */ | |
| 111 | 1078 #define FRAME_POINTER_REGNUM 111 |
| 0 | 1079 |
| 1080 /* Base register for access to arguments of the function. */ | |
| 1081 #define ARG_POINTER_REGNUM 67 | |
| 1082 | |
| 1083 /* Place to put static chain when calling a function that requires it. */ | |
| 1084 #define STATIC_CHAIN_REGNUM 11 | |
| 1085 | |
| 111 | 1086 /* Base register for access to thread local storage variables. */ |
| 1087 #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2) | |
| 1088 | |
| 0 | 1089 |
| 1090 /* Define the classes of registers for register constraints in the | |
| 1091 machine description. Also define ranges of constants. | |
| 1092 | |
| 1093 One of the classes must always be named ALL_REGS and include all hard regs. | |
| 1094 If there is more than one class, another class must be named NO_REGS | |
| 1095 and contain no registers. | |
| 1096 | |
| 1097 The name GENERAL_REGS must be the name of a class (or an alias for | |
| 1098 another name such as ALL_REGS). This is the class of registers | |
| 1099 that is allowed by "g" or "r" in a register constraint. | |
| 1100 Also, registers outside this class are allocated only when | |
| 1101 instructions express preferences for them. | |
| 1102 | |
| 1103 The classes must be numbered in nondecreasing order; that is, | |
| 1104 a larger-numbered class must never be contained completely | |
| 1105 in a smaller-numbered class. | |
| 1106 | |
| 1107 For any two classes, it is very desirable that there be another | |
| 1108 class that represents their union. */ | |
| 1109 | |
|
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1110 /* The RS/6000 has three types of registers, fixed-point, floating-point, and |
| 111 | 1111 condition registers, plus three special registers, CTR, and the link |
|
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1112 register. AltiVec adds a vector register class. VSX registers overlap the |
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1113 FPR registers and the Altivec registers. |
| 0 | 1114 |
| 1115 However, r0 is special in that it cannot be used as a base register. | |
| 1116 So make a class for registers valid as base registers. | |
| 1117 | |
| 1118 Also, cr0 is the only condition code register that can be used in | |
| 1119 arithmetic insns, so make a separate class for it. */ | |
| 1120 | |
| 1121 enum reg_class | |
| 1122 { | |
| 1123 NO_REGS, | |
| 1124 BASE_REGS, | |
| 1125 GENERAL_REGS, | |
| 1126 FLOAT_REGS, | |
| 1127 ALTIVEC_REGS, | |
|
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1128 VSX_REGS, |
| 0 | 1129 VRSAVE_REGS, |
| 1130 VSCR_REGS, | |
| 111 | 1131 SPR_REGS, |
| 0 | 1132 NON_SPECIAL_REGS, |
| 1133 LINK_REGS, | |
| 1134 CTR_REGS, | |
| 1135 LINK_OR_CTR_REGS, | |
| 1136 SPECIAL_REGS, | |
| 1137 SPEC_OR_GEN_REGS, | |
| 1138 CR0_REGS, | |
| 1139 CR_REGS, | |
| 1140 NON_FLOAT_REGS, | |
|
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1141 CA_REGS, |
| 0 | 1142 ALL_REGS, |
| 1143 LIM_REG_CLASSES | |
| 1144 }; | |
| 1145 | |
| 1146 #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
| 1147 | |
| 1148 /* Give names of register classes as strings for dump file. */ | |
| 1149 | |
| 1150 #define REG_CLASS_NAMES \ | |
| 1151 { \ | |
| 1152 "NO_REGS", \ | |
| 1153 "BASE_REGS", \ | |
| 1154 "GENERAL_REGS", \ | |
| 1155 "FLOAT_REGS", \ | |
| 1156 "ALTIVEC_REGS", \ | |
|
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1157 "VSX_REGS", \ |
| 0 | 1158 "VRSAVE_REGS", \ |
| 1159 "VSCR_REGS", \ | |
| 111 | 1160 "SPR_REGS", \ |
| 0 | 1161 "NON_SPECIAL_REGS", \ |
| 1162 "LINK_REGS", \ | |
| 1163 "CTR_REGS", \ | |
| 1164 "LINK_OR_CTR_REGS", \ | |
| 1165 "SPECIAL_REGS", \ | |
| 1166 "SPEC_OR_GEN_REGS", \ | |
| 1167 "CR0_REGS", \ | |
| 1168 "CR_REGS", \ | |
| 1169 "NON_FLOAT_REGS", \ | |
|
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1170 "CA_REGS", \ |
| 0 | 1171 "ALL_REGS" \ |
| 1172 } | |
| 1173 | |
| 1174 /* Define which registers fit in which classes. | |
| 1175 This is an initializer for a vector of HARD_REG_SET | |
| 1176 of length N_REG_CLASSES. */ | |
| 1177 | |
| 111 | 1178 #define REG_CLASS_CONTENTS \ |
| 1179 { \ | |
| 1180 /* NO_REGS. */ \ | |
| 1181 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ | |
| 1182 /* BASE_REGS. */ \ | |
| 1183 { 0xfffffffe, 0x00000000, 0x00000008, 0x00008000 }, \ | |
| 1184 /* GENERAL_REGS. */ \ | |
| 1185 { 0xffffffff, 0x00000000, 0x00000008, 0x00008000 }, \ | |
| 1186 /* FLOAT_REGS. */ \ | |
| 1187 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \ | |
| 1188 /* ALTIVEC_REGS. */ \ | |
| 1189 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, \ | |
| 1190 /* VSX_REGS. */ \ | |
| 1191 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, \ | |
| 1192 /* VRSAVE_REGS. */ \ | |
| 1193 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \ | |
| 1194 /* VSCR_REGS. */ \ | |
| 1195 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, \ | |
| 1196 /* SPR_REGS. */ \ | |
| 1197 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, \ | |
| 1198 /* NON_SPECIAL_REGS. */ \ | |
| 1199 { 0xffffffff, 0xffffffff, 0x00000008, 0x00008000 }, \ | |
| 1200 /* LINK_REGS. */ \ | |
| 1201 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, \ | |
| 1202 /* CTR_REGS. */ \ | |
| 1203 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, \ | |
| 1204 /* LINK_OR_CTR_REGS. */ \ | |
| 1205 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, \ | |
| 1206 /* SPECIAL_REGS. */ \ | |
| 1207 { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, \ | |
| 1208 /* SPEC_OR_GEN_REGS. */ \ | |
| 1209 { 0xffffffff, 0x00000000, 0x0000000e, 0x0000a000 }, \ | |
| 1210 /* CR0_REGS. */ \ | |
| 1211 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, \ | |
| 1212 /* CR_REGS. */ \ | |
| 1213 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, \ | |
| 1214 /* NON_FLOAT_REGS. */ \ | |
| 1215 { 0xffffffff, 0x00000000, 0x00000ffe, 0x00008000 }, \ | |
| 1216 /* CA_REGS. */ \ | |
| 1217 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, \ | |
| 1218 /* ALL_REGS. */ \ | |
| 1219 { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0001ffff } \ | |
| 0 | 1220 } |
| 1221 | |
| 1222 /* The same information, inverted: | |
| 1223 Return the class number of the smallest class containing | |
| 1224 reg number REGNO. This could be a conditional expression | |
| 1225 or could index an array. */ | |
| 1226 | |
|
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1227 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; |
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1228 |
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1229 #define REGNO_REG_CLASS(REGNO) \ |
| 111 | 1230 (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\ |
|
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1231 rs6000_regno_regclass[(REGNO)]) |
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1232 |
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1233 /* Register classes for various constraints that are based on the target |
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1234 switches. */ |
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1235 enum r6000_reg_class_enum { |
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1236 RS6000_CONSTRAINT_d, /* fpr registers for double values */ |
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1237 RS6000_CONSTRAINT_f, /* fpr registers for single values */ |
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1238 RS6000_CONSTRAINT_v, /* Altivec registers */ |
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1239 RS6000_CONSTRAINT_wa, /* Any VSX register */ |
| 111 | 1240 RS6000_CONSTRAINT_wb, /* Altivec register if ISA 3.0 vector. */ |
|
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1241 RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ |
| 111 | 1242 RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */ |
|
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1243 RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ |
| 111 | 1244 RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ |
| 1245 RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */ | |
| 1246 RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ | |
| 1247 RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */ | |
| 1248 RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */ | |
| 1249 RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ | |
| 1250 RS6000_CONSTRAINT_wm, /* VSX register for direct move */ | |
| 1251 RS6000_CONSTRAINT_wo, /* VSX register for power9 vector. */ | |
| 1252 RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */ | |
| 1253 RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */ | |
| 1254 RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ | |
|
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1255 RS6000_CONSTRAINT_ws, /* VSX register for DF */ |
| 111 | 1256 RS6000_CONSTRAINT_wt, /* VSX register for TImode */ |
| 1257 RS6000_CONSTRAINT_wu, /* Altivec register for float load/stores. */ | |
| 1258 RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */ | |
| 1259 RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */ | |
| 1260 RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ | |
| 1261 RS6000_CONSTRAINT_wy, /* VSX register for SF */ | |
| 1262 RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */ | |
| 1263 RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */ | |
| 1264 RS6000_CONSTRAINT_wH, /* Altivec register for 32-bit integers. */ | |
| 1265 RS6000_CONSTRAINT_wI, /* VSX register for 32-bit integers. */ | |
| 1266 RS6000_CONSTRAINT_wJ, /* VSX register for 8/16-bit integers. */ | |
| 1267 RS6000_CONSTRAINT_wK, /* Altivec register for 16/32-bit integers. */ | |
|
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1268 RS6000_CONSTRAINT_MAX |
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1269 }; |
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1270 |
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1271 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; |
| 0 | 1272 |
| 1273 /* The class value for index registers, and the one for base regs. */ | |
| 1274 #define INDEX_REG_CLASS GENERAL_REGS | |
| 1275 #define BASE_REG_CLASS BASE_REGS | |
| 1276 | |
|
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1277 /* Return whether a given register class can hold VSX objects. */ |
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1278 #define VSX_REG_CLASS_P(CLASS) \ |
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1279 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) |
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1280 |
| 111 | 1281 /* Return whether a given register class targets general purpose registers. */ |
| 1282 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS) | |
| 1283 | |
| 0 | 1284 /* Given an rtx X being reloaded into a reg required to be |
| 1285 in class CLASS, return the class of reg to actually use. | |
| 1286 In general this is just CLASS; but on some machines | |
| 1287 in some cases it is preferable to use a more restrictive class. | |
| 1288 | |
| 1289 On the RS/6000, we have to return NO_REGS when we want to reload a | |
| 1290 floating-point CONST_DOUBLE to force it to be copied to memory. | |
| 1291 | |
| 1292 We also don't want to reload integer values into floating-point | |
| 1293 registers if we can at all help it. In fact, this can | |
| 1294 cause reload to die, if it tries to generate a reload of CTR | |
| 1295 into a FP register and discovers it doesn't have the memory location | |
| 1296 required. | |
| 1297 | |
| 1298 ??? Would it be a good idea to have reload do the converse, that is | |
| 1299 try to reload floating modes into FP registers if possible? | |
| 1300 */ | |
| 1301 | |
| 1302 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ | |
|
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1303 rs6000_preferred_reload_class_ptr (X, CLASS) |
| 0 | 1304 |
| 1305 /* Return the register class of a scratch register needed to copy IN into | |
| 1306 or out of a register in CLASS in MODE. If it can be done directly, | |
| 1307 NO_REGS is returned. */ | |
| 1308 | |
| 1309 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ | |
|
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1310 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) |
| 0 | 1311 |
| 1312 /* Return the maximum number of consecutive registers | |
| 1313 needed to represent mode MODE in a register of class CLASS. | |
| 1314 | |
|
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1315 On RS/6000, this is the size of MODE in words, except in the FP regs, where |
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1316 a single reg is enough for two words, unless we have VSX, where the FP |
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1317 registers can hold 128 bits. */ |
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1318 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] |
| 0 | 1319 |
| 1320 /* Stack layout; function entry, exit and calling. */ | |
| 1321 | |
| 1322 /* Define this if pushing a word on the stack | |
| 1323 makes the stack pointer a smaller address. */ | |
| 111 | 1324 #define STACK_GROWS_DOWNWARD 1 |
| 0 | 1325 |
| 1326 /* Offsets recorded in opcodes are a multiple of this alignment factor. */ | |
| 1327 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) | |
| 1328 | |
| 1329 /* Define this to nonzero if the nominal address of the stack frame | |
| 1330 is at the high-address end of the local variables; | |
| 1331 that is, each additional local variable allocated | |
| 1332 goes at a more negative offset in the frame. | |
| 1333 | |
| 1334 On the RS/6000, we grow upwards, from the area after the outgoing | |
| 1335 arguments. */ | |
| 111 | 1336 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \ |
| 1337 || (flag_sanitize & SANITIZE_ADDRESS) != 0) | |
| 0 | 1338 |
| 1339 /* Size of the fixed area on the stack */ | |
| 1340 #define RS6000_SAVE_AREA \ | |
| 111 | 1341 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \ |
| 0 | 1342 << (TARGET_64BIT ? 1 : 0)) |
| 1343 | |
| 111 | 1344 /* Stack offset for toc save slot. */ |
| 1345 #define RS6000_TOC_SAVE_SLOT \ | |
| 1346 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0)) | |
| 0 | 1347 |
| 1348 /* Align an address */ | |
| 111 | 1349 #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a)) |
| 0 | 1350 |
| 1351 /* Offset within stack frame to start allocating local variables at. | |
| 1352 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
| 1353 first local allocated. Otherwise, it is the offset to the BEGINNING | |
| 1354 of the first local allocated. | |
| 1355 | |
| 1356 On the RS/6000, the frame pointer is the same as the stack pointer, | |
| 1357 except for dynamic allocations. So we start after the fixed area and | |
| 111 | 1358 outgoing parameter area. |
| 1359 | |
| 1360 If the function uses dynamic stack space (CALLS_ALLOCA is set), that | |
| 1361 space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the | |
| 1362 sizes of the fixed area and the parameter area must be a multiple of | |
| 1363 STACK_BOUNDARY. */ | |
| 1364 | |
| 1365 #define RS6000_STARTING_FRAME_OFFSET \ | |
| 1366 (cfun->calls_alloca \ | |
| 1367 ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \ | |
| 1368 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \ | |
|
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1369 : (RS6000_ALIGN (crtl->outgoing_args_size, \ |
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1370 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ |
| 0 | 1371 + RS6000_SAVE_AREA)) |
| 1372 | |
| 1373 /* Offset from the stack pointer register to an item dynamically | |
| 1374 allocated on the stack, e.g., by `alloca'. | |
| 1375 | |
| 1376 The default value for this macro is `STACK_POINTER_OFFSET' plus the | |
| 1377 length of the outgoing arguments. The default is correct for most | |
| 111 | 1378 machines. See `function.c' for details. |
| 1379 | |
| 1380 This value must be a multiple of STACK_BOUNDARY (hard coded in | |
| 1381 `emit-rtl.c'). */ | |
| 0 | 1382 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ |
| 131 | 1383 RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \ |
| 1384 + STACK_POINTER_OFFSET, \ | |
| 111 | 1385 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) |
| 0 | 1386 |
| 1387 /* If we generate an insn to push BYTES bytes, | |
| 1388 this says how many the stack pointer really advances by. | |
| 1389 On RS/6000, don't define this because there are no push insns. */ | |
| 1390 /* #define PUSH_ROUNDING(BYTES) */ | |
| 1391 | |
| 1392 /* Offset of first parameter from the argument pointer register value. | |
| 1393 On the RS/6000, we define the argument pointer to the start of the fixed | |
| 1394 area. */ | |
| 1395 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA | |
| 1396 | |
| 1397 /* Offset from the argument pointer register value to the top of | |
| 1398 stack. This is different from FIRST_PARM_OFFSET because of the | |
| 1399 register save area. */ | |
| 1400 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 | |
| 1401 | |
| 1402 /* Define this if stack space is still allocated for a parameter passed | |
| 1403 in a register. The value is the number of bytes allocated to this | |
| 1404 area. */ | |
| 111 | 1405 #define REG_PARM_STACK_SPACE(FNDECL) \ |
| 1406 rs6000_reg_parm_stack_space ((FNDECL), false) | |
| 1407 | |
| 1408 /* Define this macro if space guaranteed when compiling a function body | |
| 1409 is different to space required when making a call, a situation that | |
| 1410 can arise with K&R style function definitions. */ | |
| 1411 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \ | |
| 1412 rs6000_reg_parm_stack_space ((FNDECL), true) | |
| 0 | 1413 |
| 1414 /* Define this if the above stack space is to be considered part of the | |
| 1415 space allocated by the caller. */ | |
| 1416 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 | |
| 1417 | |
| 1418 /* This is the difference between the logical top of stack and the actual sp. | |
| 1419 | |
| 1420 For the RS/6000, sp points past the fixed area. */ | |
| 1421 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA | |
| 1422 | |
| 1423 /* Define this if the maximum size of all the outgoing args is to be | |
| 1424 accumulated and pushed during the prologue. The amount can be | |
| 1425 found in the variable crtl->outgoing_args_size. */ | |
| 1426 #define ACCUMULATE_OUTGOING_ARGS 1 | |
| 1427 | |
| 1428 /* Define how to find the value returned by a library function | |
| 1429 assuming the value has mode MODE. */ | |
| 1430 | |
| 1431 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) | |
| 1432 | |
| 1433 /* DRAFT_V4_STRUCT_RET defaults off. */ | |
| 1434 #define DRAFT_V4_STRUCT_RET 0 | |
| 1435 | |
| 1436 /* Let TARGET_RETURN_IN_MEMORY control what happens. */ | |
| 1437 #define DEFAULT_PCC_STRUCT_RETURN 0 | |
| 1438 | |
| 1439 /* Mode of stack savearea. | |
| 1440 FUNCTION is VOIDmode because calling convention maintains SP. | |
| 1441 BLOCK needs Pmode for SP. | |
| 1442 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ | |
| 1443 #define STACK_SAVEAREA_MODE(LEVEL) \ | |
| 1444 (LEVEL == SAVE_FUNCTION ? VOIDmode \ | |
| 111 | 1445 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode) |
| 0 | 1446 |
| 1447 /* Minimum and maximum general purpose registers used to hold arguments. */ | |
| 1448 #define GP_ARG_MIN_REG 3 | |
| 1449 #define GP_ARG_MAX_REG 10 | |
| 1450 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) | |
| 1451 | |
| 1452 /* Minimum and maximum floating point registers used to hold arguments. */ | |
| 1453 #define FP_ARG_MIN_REG 33 | |
| 1454 #define FP_ARG_AIX_MAX_REG 45 | |
| 1455 #define FP_ARG_V4_MAX_REG 40 | |
| 111 | 1456 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \ |
| 1457 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG) | |
| 0 | 1458 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) |
| 1459 | |
| 1460 /* Minimum and maximum AltiVec registers used to hold arguments. */ | |
| 1461 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) | |
| 1462 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) | |
| 1463 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) | |
| 1464 | |
| 111 | 1465 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */ |
| 1466 #define AGGR_ARG_NUM_REG 8 | |
| 1467 | |
| 0 | 1468 /* Return registers */ |
| 1469 #define GP_ARG_RETURN GP_ARG_MIN_REG | |
| 1470 #define FP_ARG_RETURN FP_ARG_MIN_REG | |
| 1471 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) | |
| 111 | 1472 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \ |
| 1473 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) | |
| 1474 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \ | |
| 1475 ? (ALTIVEC_ARG_RETURN \ | |
| 1476 + (TARGET_FLOAT128_TYPE ? 1 : 0)) \ | |
| 1477 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) | |
| 0 | 1478 |
| 1479 /* Flags for the call/call_value rtl operations set up by function_arg */ | |
| 1480 #define CALL_NORMAL 0x00000000 /* no special processing */ | |
| 1481 /* Bits in 0x00000001 are unused. */ | |
| 1482 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ | |
| 1483 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ | |
| 1484 #define CALL_LONG 0x00000008 /* always call indirect */ | |
| 1485 #define CALL_LIBCALL 0x00000010 /* libcall */ | |
| 1486 | |
| 1487 /* We don't have prologue and epilogue functions to save/restore | |
| 1488 everything for most ABIs. */ | |
| 1489 #define WORLD_SAVE_P(INFO) 0 | |
| 1490 | |
| 1491 /* 1 if N is a possible register number for a function value | |
| 1492 as seen by the caller. | |
| 1493 | |
| 1494 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ | |
| 1495 #define FUNCTION_VALUE_REGNO_P(N) \ | |
| 1496 ((N) == GP_ARG_RETURN \ | |
| 111 | 1497 || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \ |
| 1498 && TARGET_HARD_FLOAT) \ | |
| 1499 || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \ | |
| 1500 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) | |
| 0 | 1501 |
| 1502 /* 1 if N is a possible register number for function argument passing. | |
| 1503 On RS/6000, these are r3-r10 and fp1-fp13. | |
| 1504 On AltiVec, v2 - v13 are used for passing vectors. */ | |
| 1505 #define FUNCTION_ARG_REGNO_P(N) \ | |
| 111 | 1506 (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \ |
| 1507 || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \ | |
| 0 | 1508 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ |
| 111 | 1509 || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \ |
| 1510 && TARGET_HARD_FLOAT)) | |
| 0 | 1511 |
| 1512 /* Define a data type for recording info about an argument list | |
| 1513 during the scan of that argument list. This data type should | |
| 1514 hold all necessary information about the function itself | |
| 1515 and about the args processed so far, enough to enable macros | |
| 1516 such as FUNCTION_ARG to determine where the next arg should go. | |
| 1517 | |
| 1518 On the RS/6000, this is a structure. The first element is the number of | |
| 1519 total argument words, the second is used to store the next | |
| 1520 floating-point register number, and the third says how many more args we | |
| 1521 have prototype types for. | |
| 1522 | |
| 1523 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is | |
| 1524 the next available GP register, `fregno' is the next available FP | |
| 1525 register, and `words' is the number of words used on the stack. | |
| 1526 | |
| 1527 The varargs/stdarg support requires that this structure's size | |
| 1528 be a multiple of sizeof(int). */ | |
| 1529 | |
| 1530 typedef struct rs6000_args | |
| 1531 { | |
| 1532 int words; /* # words used for passing GP registers */ | |
| 1533 int fregno; /* next available FP register */ | |
| 1534 int vregno; /* next available AltiVec register */ | |
| 1535 int nargs_prototype; /* # args left in the current prototype */ | |
| 1536 int prototype; /* Whether a prototype was defined */ | |
| 1537 int stdarg; /* Whether function is a stdarg function. */ | |
| 1538 int call_cookie; /* Do special things for this call */ | |
| 1539 int sysv_gregno; /* next available GP register */ | |
| 1540 int intoffset; /* running offset in struct (darwin64) */ | |
| 1541 int use_stack; /* any part of struct on stack (darwin64) */ | |
|
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1542 int floats_in_gpr; /* count of SFmode floats taking up |
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1543 GPR space (darwin64) */ |
| 0 | 1544 int named; /* false for varargs params */ |
|
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1545 int escapes; /* if function visible outside tu */ |
| 111 | 1546 int libcall; /* If this is a compiler generated call. */ |
| 0 | 1547 } CUMULATIVE_ARGS; |
| 1548 | |
| 1549 /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
| 1550 for a call to a function whose data type is FNTYPE. | |
| 1551 For a library call, FNTYPE is 0. */ | |
| 1552 | |
|
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1553 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
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1554 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \ |
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1555 N_NAMED_ARGS, FNDECL, VOIDmode) |
| 0 | 1556 |
| 1557 /* Similar, but when scanning the definition of a procedure. We always | |
| 1558 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ | |
| 1559 | |
| 1560 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ | |
|
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1561 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \ |
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1562 1000, current_function_decl, VOIDmode) |
| 0 | 1563 |
| 1564 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ | |
| 1565 | |
| 1566 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ | |
|
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1567 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \ |
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1568 0, NULL_TREE, MODE) |
| 0 | 1569 |
| 1570 #define PAD_VARARGS_DOWN \ | |
| 111 | 1571 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD) |
| 0 | 1572 |
| 1573 /* Output assembler code to FILE to increment profiler label # LABELNO | |
| 1574 for profiling a function entry. */ | |
| 1575 | |
| 1576 #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
| 1577 output_function_profiler ((FILE), (LABELNO)); | |
| 1578 | |
| 1579 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
| 1580 the stack pointer does not matter. No definition is equivalent to | |
| 1581 always zero. | |
| 1582 | |
| 1583 On the RS/6000, this is nonzero because we can restore the stack from | |
| 1584 its backpointer, which we maintain. */ | |
| 1585 #define EXIT_IGNORE_STACK 1 | |
| 1586 | |
| 1587 /* Define this macro as a C expression that is nonzero for registers | |
| 1588 that are used by the epilogue or the return' pattern. The stack | |
| 1589 and frame pointer registers are already be assumed to be used as | |
| 1590 needed. */ | |
| 1591 | |
| 1592 #define EPILOGUE_USES(REGNO) \ | |
| 1593 ((reload_completed && (REGNO) == LR_REGNO) \ | |
| 1594 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ | |
|
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1595 || (crtl->calls_eh_return \ |
| 0 | 1596 && TARGET_AIX \ |
| 1597 && (REGNO) == 2)) | |
| 1598 | |
| 1599 | |
| 1600 /* Length in units of the trampoline for entering a nested function. */ | |
| 1601 | |
| 1602 #define TRAMPOLINE_SIZE rs6000_trampoline_size () | |
| 1603 | |
| 1604 /* Definitions for __builtin_return_address and __builtin_frame_address. | |
| 111 | 1605 __builtin_return_address (0) should give link register (LR_REGNO), enable |
| 0 | 1606 this. */ |
| 1607 /* This should be uncommented, so that the link register is used, but | |
| 1608 currently this would result in unmatched insns and spilling fixed | |
| 1609 registers so we'll leave it for another day. When these problems are | |
| 1610 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. | |
| 1611 (mrs) */ | |
| 1612 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ | |
| 1613 | |
| 1614 /* Number of bytes into the frame return addresses can be found. See | |
| 1615 rs6000_stack_info in rs6000.c for more information on how the different | |
| 1616 abi's store the return address. */ | |
| 111 | 1617 #define RETURN_ADDRESS_OFFSET \ |
| 1618 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0)) | |
| 0 | 1619 |
| 1620 /* The current return address is in link register (65). The return address | |
| 1621 of anything farther back is accessed normally at an offset of 8 from the | |
| 1622 frame pointer. */ | |
| 1623 #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
| 1624 (rs6000_return_addr (COUNT, FRAME)) | |
| 1625 | |
| 1626 | |
| 1627 /* Definitions for register eliminations. | |
| 1628 | |
| 1629 We have two registers that can be eliminated on the RS/6000. First, the | |
| 1630 frame pointer register can often be eliminated in favor of the stack | |
| 1631 pointer register. Secondly, the argument pointer register can always be | |
| 1632 eliminated; it is replaced with either the stack or frame pointer. | |
| 1633 | |
| 1634 In addition, we use the elimination mechanism to see if r30 is needed | |
| 1635 Initially we assume that it isn't. If it is, we spill it. This is done | |
| 1636 by making it an eliminable register. We replace it with itself so that | |
| 1637 if it isn't needed, then existing uses won't be modified. */ | |
| 1638 | |
| 1639 /* This is an array of structures. Each structure initializes one pair | |
| 1640 of eliminable registers. The "from" register number is given first, | |
| 1641 followed by "to". Eliminations of the same "from" register are listed | |
| 1642 in order of preference. */ | |
| 1643 #define ELIMINABLE_REGS \ | |
| 1644 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 1645 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 1646 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
| 1647 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 1648 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
| 1649 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } | |
| 1650 | |
| 1651 /* Define the offset between two registers, one to be eliminated, and the other | |
| 1652 its replacement, at the start of a routine. */ | |
| 1653 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
| 1654 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) | |
| 1655 | |
| 1656 /* Addressing modes, and classification of registers for them. */ | |
| 1657 | |
| 1658 #define HAVE_PRE_DECREMENT 1 | |
| 1659 #define HAVE_PRE_INCREMENT 1 | |
| 1660 #define HAVE_PRE_MODIFY_DISP 1 | |
| 1661 #define HAVE_PRE_MODIFY_REG 1 | |
| 1662 | |
| 1663 /* Macros to check register numbers against specific register classes. */ | |
| 1664 | |
| 1665 /* These assume that REGNO is a hard or pseudo reg number. | |
| 1666 They give nonzero only if REGNO is a hard reg of the suitable class | |
| 1667 or a pseudo reg currently allocated to a suitable hard reg. | |
| 1668 Since they use reg_renumber, they are safe only once reg_renumber | |
| 111 | 1669 has been allocated, which happens in reginfo.c during register |
| 1670 allocation. */ | |
| 0 | 1671 |
| 1672 #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
| 1673 ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
| 1674 ? (REGNO) <= 31 || (REGNO) == 67 \ | |
| 1675 || (REGNO) == FRAME_POINTER_REGNUM \ | |
| 1676 : (reg_renumber[REGNO] >= 0 \ | |
| 1677 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ | |
| 1678 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) | |
| 1679 | |
| 1680 #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
| 1681 ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
| 1682 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ | |
| 1683 || (REGNO) == FRAME_POINTER_REGNUM \ | |
| 1684 : (reg_renumber[REGNO] > 0 \ | |
| 1685 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ | |
| 1686 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) | |
|
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1687 |
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1688 /* Nonzero if X is a hard reg that can be used as an index |
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1689 or if it is a pseudo reg in the non-strict case. */ |
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1690 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ |
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1691 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ |
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1692 || REGNO_OK_FOR_INDEX_P (REGNO (X))) |
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1693 |
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1694 /* Nonzero if X is a hard reg that can be used as a base reg |
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1695 or if it is a pseudo reg in the non-strict case. */ |
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1696 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ |
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1697 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ |
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1698 || REGNO_OK_FOR_BASE_P (REGNO (X))) |
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1699 |
| 0 | 1700 |
| 1701 /* Maximum number of registers that can appear in a valid memory address. */ | |
| 1702 | |
| 1703 #define MAX_REGS_PER_ADDRESS 2 | |
| 1704 | |
| 1705 /* Recognize any constant value that is a valid address. */ | |
| 1706 | |
| 1707 #define CONSTANT_ADDRESS_P(X) \ | |
| 1708 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
| 1709 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ | |
| 1710 || GET_CODE (X) == HIGH) | |
| 1711 | |
| 1712 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) | |
| 1713 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ | |
| 1714 && EASY_VECTOR_15((n) >> 1) \ | |
| 1715 && ((n) & 1) == 0) | |
| 1716 | |
|
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1717 #define EASY_VECTOR_MSB(n,mode) \ |
| 111 | 1718 ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \ |
|
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1719 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) |
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1720 |
| 0 | 1721 |
| 1722 /* Try a machine-dependent way of reloading an illegitimate address | |
| 1723 operand. If we find one, push the reload and jump to WIN. This | |
| 1724 macro is used in only one place: `find_reloads_address' in reload.c. | |
| 1725 | |
| 1726 Implemented on rs6000 by rs6000_legitimize_reload_address. | |
| 1727 Note that (X) is evaluated twice; this is safe in current usage. */ | |
| 1728 | |
| 1729 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ | |
| 1730 do { \ | |
| 1731 int win; \ | |
|
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1732 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \ |
| 0 | 1733 (int)(TYPE), (IND_LEVELS), &win); \ |
| 1734 if ( win ) \ | |
| 1735 goto WIN; \ | |
| 1736 } while (0) | |
| 1737 | |
| 1738 #define FIND_BASE_TERM rs6000_find_base_term | |
| 1739 | |
| 1740 /* The register number of the register used to address a table of | |
| 1741 static data addresses in memory. In some cases this register is | |
| 1742 defined by a processor's "application binary interface" (ABI). | |
| 1743 When this macro is defined, RTL is generated for this register | |
| 1744 once, as with the stack pointer and frame pointer registers. If | |
| 1745 this macro is not defined, it is up to the machine-dependent files | |
| 1746 to allocate such a register (if necessary). */ | |
| 1747 | |
| 1748 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 | |
| 111 | 1749 #define PIC_OFFSET_TABLE_REGNUM \ |
| 1750 (TARGET_TOC ? TOC_REGISTER \ | |
| 1751 : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \ | |
| 1752 : INVALID_REGNUM) | |
| 0 | 1753 |
| 1754 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) | |
| 1755 | |
| 1756 /* Define this macro if the register defined by | |
| 1757 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define | |
| 1758 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ | |
| 1759 | |
| 1760 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ | |
| 1761 | |
| 1762 /* A C expression that is nonzero if X is a legitimate immediate | |
| 1763 operand on the target machine when generating position independent | |
| 1764 code. You can assume that X satisfies `CONSTANT_P', so you need | |
| 1765 not check this. You can also assume FLAG_PIC is true, so you need | |
| 1766 not check it either. You need not define this macro if all | |
| 1767 constants (including `SYMBOL_REF') can be immediate operands when | |
| 1768 generating position independent code. */ | |
| 1769 | |
| 1770 /* #define LEGITIMATE_PIC_OPERAND_P (X) */ | |
| 1771 | |
| 1772 /* Specify the machine mode that this machine uses | |
| 1773 for the index in the tablejump instruction. */ | |
| 1774 #define CASE_VECTOR_MODE SImode | |
| 1775 | |
| 1776 /* Define as C expression which evaluates to nonzero if the tablejump | |
| 1777 instruction expects the table to contain offsets from the address of the | |
| 1778 table. | |
| 1779 Do not define this if the table should contain absolute addresses. */ | |
| 1780 #define CASE_VECTOR_PC_RELATIVE 1 | |
| 1781 | |
| 1782 /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
| 1783 #define DEFAULT_SIGNED_CHAR 0 | |
| 1784 | |
| 1785 /* An integer expression for the size in bits of the largest integer machine | |
| 1786 mode that should actually be used. */ | |
| 1787 | |
| 1788 /* Allow pairs of registers to be used, which is the intent of the default. */ | |
| 1789 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) | |
| 1790 | |
| 1791 /* Max number of bytes we can move from memory to memory | |
| 1792 in one reasonably fast instruction. */ | |
| 1793 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) | |
| 1794 #define MAX_MOVE_MAX 8 | |
| 1795 | |
| 1796 /* Nonzero if access to memory by bytes is no faster than for words. | |
| 1797 Also nonzero if doing byte operations (specifically shifts) in registers | |
| 1798 is undesirable. */ | |
| 1799 #define SLOW_BYTE_ACCESS 1 | |
| 1800 | |
| 1801 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
| 1802 will either zero-extend or sign-extend. The value of this macro should | |
| 1803 be the code that says which one of the two operations is implicitly | |
| 1804 done, UNKNOWN if none. */ | |
| 1805 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
| 1806 | |
| 1807 /* Define if loading short immediate values into registers sign extends. */ | |
| 111 | 1808 #define SHORT_IMMEDIATES_SIGN_EXTEND 1 |
| 0 | 1809 |
| 1810 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ | |
| 1811 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
| 111 | 1812 ((VALUE) = GET_MODE_BITSIZE (MODE), 2) |
| 1813 | |
| 1814 /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of | |
| 1815 zero. The hardware instructions added in Power9 and the sequences using | |
| 1816 popcount return 32 or 64. */ | |
| 1817 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
| 1818 (TARGET_CTZ || TARGET_POPCNTD \ | |
| 1819 ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \ | |
| 1820 : ((VALUE) = -1, 2)) | |
| 0 | 1821 |
| 1822 /* Specify the machine mode that pointers have. | |
| 1823 After generation of rtl, the compiler makes no further distinction | |
| 1824 between pointers and any other objects of this machine mode. */ | |
| 111 | 1825 extern scalar_int_mode rs6000_pmode; |
| 1826 #define Pmode rs6000_pmode | |
| 0 | 1827 |
| 1828 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ | |
| 1829 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) | |
| 1830 | |
| 1831 /* Mode of a function address in a call instruction (for indexing purposes). | |
| 1832 Doesn't matter on RS/6000. */ | |
| 1833 #define FUNCTION_MODE SImode | |
| 1834 | |
| 1835 /* Define this if addresses of constant functions | |
| 1836 shouldn't be put through pseudo regs where they can be cse'd. | |
| 1837 Desirable on machines where ordinary constants are expensive | |
| 1838 but a CALL with constant address is cheap. */ | |
| 111 | 1839 #define NO_FUNCTION_CSE 1 |
| 0 | 1840 |
| 1841 /* Define this to be nonzero if shift instructions ignore all but the low-order | |
| 1842 few bits. | |
| 1843 | |
| 1844 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED | |
| 1845 have been dropped from the PowerPC architecture. */ | |
| 111 | 1846 #define SHIFT_COUNT_TRUNCATED 0 |
| 0 | 1847 |
| 1848 /* Adjust the length of an INSN. LENGTH is the currently-computed length and | |
| 1849 should be adjusted to reflect any required changes. This macro is used when | |
| 1850 there is some systematic length adjustment required that would be difficult | |
| 1851 to express in the length attribute. */ | |
| 1852 | |
| 1853 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */ | |
| 1854 | |
| 1855 /* Given a comparison code (EQ, NE, etc.) and the first operand of a | |
| 1856 COMPARE, return the mode to be used for the comparison. For | |
| 1857 floating-point, CCFPmode should be used. CCUNSmode should be used | |
| 1858 for unsigned comparisons. CCEQmode should be used when we are | |
| 1859 doing an inequality comparison on the result of a | |
| 1860 comparison. CCmode should be used in all other cases. */ | |
| 1861 | |
| 1862 #define SELECT_CC_MODE(OP,X,Y) \ | |
| 1863 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ | |
| 1864 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ | |
| 1865 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ | |
| 1866 ? CCEQmode : CCmode)) | |
| 1867 | |
| 1868 /* Can the condition code MODE be safely reversed? This is safe in | |
| 1869 all cases on this port, because at present it doesn't use the | |
| 1870 trapping FP comparisons (fcmpo). */ | |
| 1871 #define REVERSIBLE_CC_MODE(MODE) 1 | |
| 1872 | |
| 1873 /* Given a condition code and a mode, return the inverse condition. */ | |
| 1874 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) | |
| 1875 | |
| 1876 | |
| 111 | 1877 /* Target cpu costs. */ |
| 1878 | |
| 1879 struct processor_costs { | |
| 1880 const int mulsi; /* cost of SImode multiplication. */ | |
| 1881 const int mulsi_const; /* cost of SImode multiplication by constant. */ | |
| 1882 const int mulsi_const9; /* cost of SImode mult by short constant. */ | |
| 1883 const int muldi; /* cost of DImode multiplication. */ | |
| 1884 const int divsi; /* cost of SImode division. */ | |
| 1885 const int divdi; /* cost of DImode division. */ | |
| 1886 const int fp; /* cost of simple SFmode and DFmode insns. */ | |
| 1887 const int dmul; /* cost of DFmode multiplication (and fmadd). */ | |
| 1888 const int sdiv; /* cost of SFmode division (fdivs). */ | |
| 1889 const int ddiv; /* cost of DFmode division (fdiv). */ | |
| 1890 const int cache_line_size; /* cache line size in bytes. */ | |
| 1891 const int l1_cache_size; /* size of l1 cache, in kilobytes. */ | |
| 1892 const int l2_cache_size; /* size of l2 cache, in kilobytes. */ | |
| 1893 const int simultaneous_prefetches; /* number of parallel prefetch | |
| 1894 operations. */ | |
| 1895 const int sfdf_convert; /* cost of SF->DF conversion. */ | |
| 1896 }; | |
| 1897 | |
| 1898 extern const struct processor_costs *rs6000_cost; | |
| 1899 | |
| 0 | 1900 /* Control the assembler format that we output. */ |
| 1901 | |
| 1902 /* A C string constant describing how to begin a comment in the target | |
| 1903 assembler language. The compiler assumes that the comment will end at | |
| 1904 the end of the line. */ | |
| 1905 #define ASM_COMMENT_START " #" | |
| 1906 | |
| 1907 /* Flag to say the TOC is initialized */ | |
| 1908 extern int toc_initialized; | |
| 1909 | |
| 1910 /* Macro to output a special constant pool entry. Go to WIN if we output | |
| 1911 it. Otherwise, it is written the usual way. | |
| 1912 | |
| 1913 On the RS/6000, toc entries are handled this way. */ | |
| 1914 | |
| 1915 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ | |
| 1916 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ | |
| 1917 { \ | |
| 1918 output_toc (FILE, X, LABELNO, MODE); \ | |
| 1919 goto WIN; \ | |
| 1920 } \ | |
| 1921 } | |
| 1922 | |
| 1923 #ifdef HAVE_GAS_WEAK | |
| 1924 #define RS6000_WEAK 1 | |
| 1925 #else | |
| 1926 #define RS6000_WEAK 0 | |
| 1927 #endif | |
| 1928 | |
| 1929 #if RS6000_WEAK | |
| 1930 /* Used in lieu of ASM_WEAKEN_LABEL. */ | |
| 111 | 1931 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ |
| 1932 rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL)) | |
| 0 | 1933 #endif |
| 1934 | |
| 1935 #if HAVE_GAS_WEAKREF | |
| 1936 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ | |
| 1937 do \ | |
| 1938 { \ | |
| 1939 fputs ("\t.weakref\t", (FILE)); \ | |
| 1940 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
| 1941 fputs (", ", (FILE)); \ | |
| 1942 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
| 1943 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ | |
| 1944 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ | |
| 1945 { \ | |
| 1946 fputs ("\n\t.weakref\t.", (FILE)); \ | |
| 1947 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
| 1948 fputs (", .", (FILE)); \ | |
| 1949 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
| 1950 } \ | |
| 1951 fputc ('\n', (FILE)); \ | |
| 1952 } while (0) | |
| 1953 #endif | |
| 1954 | |
| 1955 /* This implements the `alias' attribute. */ | |
| 1956 #undef ASM_OUTPUT_DEF_FROM_DECLS | |
| 1957 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ | |
| 1958 do \ | |
| 1959 { \ | |
| 1960 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ | |
| 1961 const char *name = IDENTIFIER_POINTER (TARGET); \ | |
| 1962 if (TREE_CODE (DECL) == FUNCTION_DECL \ | |
| 1963 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ | |
| 1964 { \ | |
| 1965 if (TREE_PUBLIC (DECL)) \ | |
| 1966 { \ | |
| 1967 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ | |
| 1968 { \ | |
| 1969 fputs ("\t.globl\t.", FILE); \ | |
| 1970 RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
| 1971 putc ('\n', FILE); \ | |
| 1972 } \ | |
| 1973 } \ | |
| 1974 else if (TARGET_XCOFF) \ | |
| 1975 { \ | |
| 111 | 1976 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ |
| 1977 { \ | |
| 1978 fputs ("\t.lglobl\t.", FILE); \ | |
| 1979 RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
| 1980 putc ('\n', FILE); \ | |
| 1981 fputs ("\t.lglobl\t", FILE); \ | |
| 1982 RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
| 1983 putc ('\n', FILE); \ | |
| 1984 } \ | |
| 0 | 1985 } \ |
| 1986 fputs ("\t.set\t.", FILE); \ | |
| 1987 RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
| 1988 fputs (",.", FILE); \ | |
| 1989 RS6000_OUTPUT_BASENAME (FILE, name); \ | |
| 1990 fputc ('\n', FILE); \ | |
| 1991 } \ | |
| 1992 ASM_OUTPUT_DEF (FILE, alias, name); \ | |
| 1993 } \ | |
| 1994 while (0) | |
| 1995 | |
| 1996 #define TARGET_ASM_FILE_START rs6000_file_start | |
| 1997 | |
| 1998 /* Output to assembler file text saying following lines | |
| 1999 may contain character constants, extra white space, comments, etc. */ | |
| 2000 | |
| 2001 #define ASM_APP_ON "" | |
| 2002 | |
| 2003 /* Output to assembler file text saying following lines | |
| 2004 no longer contain unusual constructs. */ | |
| 2005 | |
| 2006 #define ASM_APP_OFF "" | |
| 2007 | |
| 2008 /* How to refer to registers in assembler output. | |
| 2009 This sequence is indexed by compiler's hard-register-number (see above). */ | |
| 2010 | |
| 2011 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ | |
| 2012 | |
| 2013 #define REGISTER_NAMES \ | |
| 2014 { \ | |
| 2015 &rs6000_reg_names[ 0][0], /* r0 */ \ | |
| 2016 &rs6000_reg_names[ 1][0], /* r1 */ \ | |
| 2017 &rs6000_reg_names[ 2][0], /* r2 */ \ | |
| 2018 &rs6000_reg_names[ 3][0], /* r3 */ \ | |
| 2019 &rs6000_reg_names[ 4][0], /* r4 */ \ | |
| 2020 &rs6000_reg_names[ 5][0], /* r5 */ \ | |
| 2021 &rs6000_reg_names[ 6][0], /* r6 */ \ | |
| 2022 &rs6000_reg_names[ 7][0], /* r7 */ \ | |
| 2023 &rs6000_reg_names[ 8][0], /* r8 */ \ | |
| 2024 &rs6000_reg_names[ 9][0], /* r9 */ \ | |
| 2025 &rs6000_reg_names[10][0], /* r10 */ \ | |
| 2026 &rs6000_reg_names[11][0], /* r11 */ \ | |
| 2027 &rs6000_reg_names[12][0], /* r12 */ \ | |
| 2028 &rs6000_reg_names[13][0], /* r13 */ \ | |
| 2029 &rs6000_reg_names[14][0], /* r14 */ \ | |
| 2030 &rs6000_reg_names[15][0], /* r15 */ \ | |
| 2031 &rs6000_reg_names[16][0], /* r16 */ \ | |
| 2032 &rs6000_reg_names[17][0], /* r17 */ \ | |
| 2033 &rs6000_reg_names[18][0], /* r18 */ \ | |
| 2034 &rs6000_reg_names[19][0], /* r19 */ \ | |
| 2035 &rs6000_reg_names[20][0], /* r20 */ \ | |
| 2036 &rs6000_reg_names[21][0], /* r21 */ \ | |
| 2037 &rs6000_reg_names[22][0], /* r22 */ \ | |
| 2038 &rs6000_reg_names[23][0], /* r23 */ \ | |
| 2039 &rs6000_reg_names[24][0], /* r24 */ \ | |
| 2040 &rs6000_reg_names[25][0], /* r25 */ \ | |
| 2041 &rs6000_reg_names[26][0], /* r26 */ \ | |
| 2042 &rs6000_reg_names[27][0], /* r27 */ \ | |
| 2043 &rs6000_reg_names[28][0], /* r28 */ \ | |
| 2044 &rs6000_reg_names[29][0], /* r29 */ \ | |
| 2045 &rs6000_reg_names[30][0], /* r30 */ \ | |
| 2046 &rs6000_reg_names[31][0], /* r31 */ \ | |
| 2047 \ | |
| 2048 &rs6000_reg_names[32][0], /* fr0 */ \ | |
| 2049 &rs6000_reg_names[33][0], /* fr1 */ \ | |
| 2050 &rs6000_reg_names[34][0], /* fr2 */ \ | |
| 2051 &rs6000_reg_names[35][0], /* fr3 */ \ | |
| 2052 &rs6000_reg_names[36][0], /* fr4 */ \ | |
| 2053 &rs6000_reg_names[37][0], /* fr5 */ \ | |
| 2054 &rs6000_reg_names[38][0], /* fr6 */ \ | |
| 2055 &rs6000_reg_names[39][0], /* fr7 */ \ | |
| 2056 &rs6000_reg_names[40][0], /* fr8 */ \ | |
| 2057 &rs6000_reg_names[41][0], /* fr9 */ \ | |
| 2058 &rs6000_reg_names[42][0], /* fr10 */ \ | |
| 2059 &rs6000_reg_names[43][0], /* fr11 */ \ | |
| 2060 &rs6000_reg_names[44][0], /* fr12 */ \ | |
| 2061 &rs6000_reg_names[45][0], /* fr13 */ \ | |
| 2062 &rs6000_reg_names[46][0], /* fr14 */ \ | |
| 2063 &rs6000_reg_names[47][0], /* fr15 */ \ | |
| 2064 &rs6000_reg_names[48][0], /* fr16 */ \ | |
| 2065 &rs6000_reg_names[49][0], /* fr17 */ \ | |
| 2066 &rs6000_reg_names[50][0], /* fr18 */ \ | |
| 2067 &rs6000_reg_names[51][0], /* fr19 */ \ | |
| 2068 &rs6000_reg_names[52][0], /* fr20 */ \ | |
| 2069 &rs6000_reg_names[53][0], /* fr21 */ \ | |
| 2070 &rs6000_reg_names[54][0], /* fr22 */ \ | |
| 2071 &rs6000_reg_names[55][0], /* fr23 */ \ | |
| 2072 &rs6000_reg_names[56][0], /* fr24 */ \ | |
| 2073 &rs6000_reg_names[57][0], /* fr25 */ \ | |
| 2074 &rs6000_reg_names[58][0], /* fr26 */ \ | |
| 2075 &rs6000_reg_names[59][0], /* fr27 */ \ | |
| 2076 &rs6000_reg_names[60][0], /* fr28 */ \ | |
| 2077 &rs6000_reg_names[61][0], /* fr29 */ \ | |
| 2078 &rs6000_reg_names[62][0], /* fr30 */ \ | |
| 2079 &rs6000_reg_names[63][0], /* fr31 */ \ | |
| 2080 \ | |
| 111 | 2081 &rs6000_reg_names[64][0], /* was mq */ \ |
| 0 | 2082 &rs6000_reg_names[65][0], /* lr */ \ |
| 2083 &rs6000_reg_names[66][0], /* ctr */ \ | |
| 2084 &rs6000_reg_names[67][0], /* ap */ \ | |
| 2085 \ | |
| 2086 &rs6000_reg_names[68][0], /* cr0 */ \ | |
| 2087 &rs6000_reg_names[69][0], /* cr1 */ \ | |
| 2088 &rs6000_reg_names[70][0], /* cr2 */ \ | |
| 2089 &rs6000_reg_names[71][0], /* cr3 */ \ | |
| 2090 &rs6000_reg_names[72][0], /* cr4 */ \ | |
| 2091 &rs6000_reg_names[73][0], /* cr5 */ \ | |
| 2092 &rs6000_reg_names[74][0], /* cr6 */ \ | |
| 2093 &rs6000_reg_names[75][0], /* cr7 */ \ | |
| 2094 \ | |
|
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2095 &rs6000_reg_names[76][0], /* ca */ \ |
| 0 | 2096 \ |
| 2097 &rs6000_reg_names[77][0], /* v0 */ \ | |
| 2098 &rs6000_reg_names[78][0], /* v1 */ \ | |
| 2099 &rs6000_reg_names[79][0], /* v2 */ \ | |
| 2100 &rs6000_reg_names[80][0], /* v3 */ \ | |
| 2101 &rs6000_reg_names[81][0], /* v4 */ \ | |
| 2102 &rs6000_reg_names[82][0], /* v5 */ \ | |
| 2103 &rs6000_reg_names[83][0], /* v6 */ \ | |
| 2104 &rs6000_reg_names[84][0], /* v7 */ \ | |
| 2105 &rs6000_reg_names[85][0], /* v8 */ \ | |
| 2106 &rs6000_reg_names[86][0], /* v9 */ \ | |
| 2107 &rs6000_reg_names[87][0], /* v10 */ \ | |
| 2108 &rs6000_reg_names[88][0], /* v11 */ \ | |
| 2109 &rs6000_reg_names[89][0], /* v12 */ \ | |
| 2110 &rs6000_reg_names[90][0], /* v13 */ \ | |
| 2111 &rs6000_reg_names[91][0], /* v14 */ \ | |
| 2112 &rs6000_reg_names[92][0], /* v15 */ \ | |
| 2113 &rs6000_reg_names[93][0], /* v16 */ \ | |
| 2114 &rs6000_reg_names[94][0], /* v17 */ \ | |
| 2115 &rs6000_reg_names[95][0], /* v18 */ \ | |
| 2116 &rs6000_reg_names[96][0], /* v19 */ \ | |
| 2117 &rs6000_reg_names[97][0], /* v20 */ \ | |
| 2118 &rs6000_reg_names[98][0], /* v21 */ \ | |
| 2119 &rs6000_reg_names[99][0], /* v22 */ \ | |
| 2120 &rs6000_reg_names[100][0], /* v23 */ \ | |
| 2121 &rs6000_reg_names[101][0], /* v24 */ \ | |
| 2122 &rs6000_reg_names[102][0], /* v25 */ \ | |
| 2123 &rs6000_reg_names[103][0], /* v26 */ \ | |
| 2124 &rs6000_reg_names[104][0], /* v27 */ \ | |
| 2125 &rs6000_reg_names[105][0], /* v28 */ \ | |
| 2126 &rs6000_reg_names[106][0], /* v29 */ \ | |
| 2127 &rs6000_reg_names[107][0], /* v30 */ \ | |
| 2128 &rs6000_reg_names[108][0], /* v31 */ \ | |
| 2129 &rs6000_reg_names[109][0], /* vrsave */ \ | |
| 2130 &rs6000_reg_names[110][0], /* vscr */ \ | |
| 111 | 2131 &rs6000_reg_names[111][0], /* sfp */ \ |
| 2132 &rs6000_reg_names[112][0], /* tfhar */ \ | |
| 2133 &rs6000_reg_names[113][0], /* tfiar */ \ | |
| 2134 &rs6000_reg_names[114][0], /* texasr */ \ | |
| 0 | 2135 } |
| 2136 | |
| 2137 /* Table of additional register names to use in user input. */ | |
| 2138 | |
| 2139 #define ADDITIONAL_REGISTER_NAMES \ | |
| 2140 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ | |
| 2141 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ | |
| 2142 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ | |
| 2143 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ | |
| 2144 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ | |
| 2145 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ | |
| 2146 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ | |
| 2147 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ | |
| 2148 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ | |
| 2149 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ | |
| 2150 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ | |
| 2151 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ | |
| 2152 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ | |
| 2153 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ | |
| 2154 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ | |
| 2155 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ | |
| 2156 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ | |
| 2157 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ | |
| 2158 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ | |
| 2159 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ | |
| 2160 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ | |
| 2161 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ | |
| 2162 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ | |
| 2163 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ | |
| 2164 {"vrsave", 109}, {"vscr", 110}, \ | |
| 111 | 2165 /* no additional names for: lr, ctr, ap */ \ |
| 0 | 2166 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ |
| 2167 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ | |
|
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2168 {"cc", 68}, {"sp", 1}, {"toc", 2}, \ |
|
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2169 /* CA is only part of XER, but we do not model the other parts (yet). */ \ |
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2170 {"xer", 76}, \ |
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2171 /* VSX registers overlaid on top of FR, Altivec registers */ \ |
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2172 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ |
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2173 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ |
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2174 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ |
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2175 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ |
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2176 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ |
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2177 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ |
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2178 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ |
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2179 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ |
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2180 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \ |
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2181 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \ |
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2182 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \ |
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2183 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \ |
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2184 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \ |
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2185 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \ |
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2186 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ |
| 111 | 2187 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \ |
| 2188 /* Transactional Memory Facility (HTM) Registers. */ \ | |
| 2189 {"tfhar", 112}, {"tfiar", 113}, {"texasr", 114}, \ | |
| 2190 } | |
| 0 | 2191 |
| 2192 /* This is how to output an element of a case-vector that is relative. */ | |
| 2193 | |
| 2194 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
| 2195 do { char buf[100]; \ | |
| 2196 fputs ("\t.long ", FILE); \ | |
| 2197 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ | |
| 2198 assemble_name (FILE, buf); \ | |
| 2199 putc ('-', FILE); \ | |
| 2200 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ | |
| 2201 assemble_name (FILE, buf); \ | |
| 2202 putc ('\n', FILE); \ | |
| 2203 } while (0) | |
| 2204 | |
| 2205 /* This is how to output an assembler line | |
| 2206 that says to advance the location counter | |
| 2207 to a multiple of 2**LOG bytes. */ | |
| 2208 | |
| 2209 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
| 2210 if ((LOG) != 0) \ | |
| 2211 fprintf (FILE, "\t.align %d\n", (LOG)) | |
| 2212 | |
|
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|
2213 /* How to align the given loop. */ |
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2214 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL) |
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2215 |
| 111 | 2216 /* Alignment guaranteed by __builtin_malloc. */ |
| 2217 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT. | |
| 2218 However, specifying the stronger guarantee currently leads to | |
| 2219 a regression in SPEC CPU2006 437.leslie3d. The stronger | |
| 2220 guarantee should be implemented here once that's fixed. */ | |
| 2221 #define MALLOC_ABI_ALIGNMENT (64) | |
| 2222 | |
| 0 | 2223 /* Pick up the return address upon entry to a procedure. Used for |
| 2224 dwarf2 unwind information. This also enables the table driven | |
| 2225 mechanism. */ | |
| 2226 | |
| 2227 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) | |
| 2228 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) | |
| 2229 | |
| 2230 /* Describe how we implement __builtin_eh_return. */ | |
| 2231 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) | |
| 2232 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) | |
| 2233 | |
| 2234 /* Print operand X (an rtx) in assembler syntax to file FILE. | |
| 2235 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
| 2236 For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
| 2237 | |
| 2238 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
| 2239 | |
| 2240 /* Define which CODE values are valid. */ | |
| 2241 | |
| 111 | 2242 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&') |
| 0 | 2243 |
| 2244 /* Print a memory address as an operand to reference that memory location. */ | |
| 2245 | |
| 2246 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
| 2247 | |
| 111 | 2248 /* For switching between functions with different target attributes. */ |
| 2249 #define SWITCHABLE_TARGET 1 | |
| 2250 | |
| 0 | 2251 /* uncomment for disabling the corresponding default options */ |
| 2252 /* #define MACHINE_no_sched_interblock */ | |
| 2253 /* #define MACHINE_no_sched_speculative */ | |
| 2254 /* #define MACHINE_no_sched_speculative_load */ | |
| 2255 | |
| 2256 /* General flags. */ | |
| 2257 extern int frame_pointer_needed; | |
| 2258 | |
| 111 | 2259 /* Classification of the builtin functions as to which switches enable the |
| 2260 builtin, and what attributes it should have. We used to use the target | |
| 2261 flags macros, but we've run out of bits, so we now map the options into new | |
| 2262 settings used here. */ | |
| 2263 | |
| 2264 /* Builtin attributes. */ | |
| 2265 #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */ | |
| 2266 #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */ | |
| 2267 #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */ | |
| 2268 #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */ | |
| 2269 #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */ | |
| 2270 #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */ | |
| 2271 #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */ | |
| 2272 #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */ | |
| 2273 | |
| 2274 #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */ | |
| 2275 #define RS6000_BTC_CONST 0x00000100 /* Neither uses, nor | |
| 2276 modifies global state. */ | |
| 2277 #define RS6000_BTC_PURE 0x00000200 /* reads global | |
| 2278 state/mem and does | |
| 2279 not modify global state. */ | |
| 2280 #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */ | |
| 2281 #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */ | |
| 2282 | |
| 2283 /* Miscellaneous information. */ | |
| 2284 #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */ | |
| 2285 #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */ | |
| 2286 #define RS6000_BTC_CR 0x04000000 /* function references a CR. */ | |
| 2287 #define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */ | |
| 2288 #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */ | |
|
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2289 |
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2290 /* Convenience macros to document the instruction type. */ |
| 111 | 2291 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ |
| 2292 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ | |
| 2293 | |
| 2294 /* Builtin targets. For now, we reuse the masks for those options that are in | |
| 131 | 2295 target flags, and pick a random bit for ldbl128, which isn't in |
| 2296 target_flags. */ | |
| 111 | 2297 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ |
| 2298 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ | |
| 2299 #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */ | |
| 2300 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ | |
| 2301 #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ | |
| 2302 #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ | |
| 2303 #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ | |
| 2304 #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ | |
| 2305 #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ | |
| 2306 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ | |
| 2307 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ | |
| 2308 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ | |
| 2309 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ | |
| 2310 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ | |
| 2311 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ | |
| 2312 #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ | |
| 2313 #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ | |
| 2314 #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ | |
| 2315 #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ | |
| 131 | 2316 #define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */ |
| 111 | 2317 #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */ |
| 2318 #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */ | |
| 2319 | |
| 2320 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ | |
| 2321 | RS6000_BTM_VSX \ | |
| 2322 | RS6000_BTM_P8_VECTOR \ | |
| 2323 | RS6000_BTM_P9_VECTOR \ | |
| 2324 | RS6000_BTM_P9_MISC \ | |
| 2325 | RS6000_BTM_MODULO \ | |
| 2326 | RS6000_BTM_CRYPTO \ | |
| 2327 | RS6000_BTM_FRE \ | |
| 2328 | RS6000_BTM_FRES \ | |
| 2329 | RS6000_BTM_FRSQRTE \ | |
| 2330 | RS6000_BTM_FRSQRTES \ | |
| 2331 | RS6000_BTM_HTM \ | |
| 2332 | RS6000_BTM_POPCNTD \ | |
| 2333 | RS6000_BTM_CELL \ | |
| 2334 | RS6000_BTM_DFP \ | |
| 2335 | RS6000_BTM_HARD_FLOAT \ | |
| 2336 | RS6000_BTM_LDBL128 \ | |
| 131 | 2337 | RS6000_BTM_POWERPC64 \ |
| 111 | 2338 | RS6000_BTM_FLOAT128 \ |
| 2339 | RS6000_BTM_FLOAT128_HW) | |
| 2340 | |
| 2341 /* Define builtin enum index. */ | |
| 2342 | |
| 2343 #undef RS6000_BUILTIN_0 | |
| 2344 #undef RS6000_BUILTIN_1 | |
| 2345 #undef RS6000_BUILTIN_2 | |
| 2346 #undef RS6000_BUILTIN_3 | |
| 2347 #undef RS6000_BUILTIN_A | |
| 2348 #undef RS6000_BUILTIN_D | |
| 2349 #undef RS6000_BUILTIN_H | |
| 2350 #undef RS6000_BUILTIN_P | |
| 2351 #undef RS6000_BUILTIN_X | |
| 2352 | |
| 2353 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2354 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2355 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2356 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2357 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2358 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2359 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2360 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2361 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
|
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2362 |
| 0 | 2363 enum rs6000_builtins |
| 2364 { | |
|
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2365 #include "rs6000-builtin.def" |
| 0 | 2366 |
| 2367 RS6000_BUILTIN_COUNT | |
| 2368 }; | |
| 2369 | |
| 111 | 2370 #undef RS6000_BUILTIN_0 |
| 2371 #undef RS6000_BUILTIN_1 | |
| 2372 #undef RS6000_BUILTIN_2 | |
| 2373 #undef RS6000_BUILTIN_3 | |
| 2374 #undef RS6000_BUILTIN_A | |
| 2375 #undef RS6000_BUILTIN_D | |
| 2376 #undef RS6000_BUILTIN_H | |
| 2377 #undef RS6000_BUILTIN_P | |
| 2378 #undef RS6000_BUILTIN_X | |
|
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2379 |
| 0 | 2380 enum rs6000_builtin_type_index |
| 2381 { | |
| 2382 RS6000_BTI_NOT_OPAQUE, | |
| 2383 RS6000_BTI_opaque_V4SI, | |
| 131 | 2384 RS6000_BTI_V16QI, /* __vector signed char */ |
| 111 | 2385 RS6000_BTI_V1TI, |
|
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2386 RS6000_BTI_V2DI, |
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2387 RS6000_BTI_V2DF, |
| 0 | 2388 RS6000_BTI_V4HI, |
| 2389 RS6000_BTI_V4SI, | |
| 2390 RS6000_BTI_V4SF, | |
| 2391 RS6000_BTI_V8HI, | |
| 131 | 2392 RS6000_BTI_unsigned_V16QI, /* __vector unsigned char */ |
| 111 | 2393 RS6000_BTI_unsigned_V1TI, |
| 0 | 2394 RS6000_BTI_unsigned_V8HI, |
| 2395 RS6000_BTI_unsigned_V4SI, | |
|
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2396 RS6000_BTI_unsigned_V2DI, |
| 0 | 2397 RS6000_BTI_bool_char, /* __bool char */ |
| 2398 RS6000_BTI_bool_short, /* __bool short */ | |
| 2399 RS6000_BTI_bool_int, /* __bool int */ | |
| 131 | 2400 RS6000_BTI_bool_long_long, /* __bool long long */ |
| 2401 RS6000_BTI_pixel, /* __pixel (16 bits arranged as 4 | |
| 2402 channels of 1, 5, 5, and 5 bits | |
| 2403 respectively as packed with the | |
| 2404 vpkpx insn. __pixel is only | |
| 2405 meaningful as a vector type. | |
| 2406 There is no corresponding scalar | |
| 2407 __pixel data type.) */ | |
| 0 | 2408 RS6000_BTI_bool_V16QI, /* __vector __bool char */ |
| 2409 RS6000_BTI_bool_V8HI, /* __vector __bool short */ | |
| 2410 RS6000_BTI_bool_V4SI, /* __vector __bool int */ | |
|
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2411 RS6000_BTI_bool_V2DI, /* __vector __bool long */ |
| 0 | 2412 RS6000_BTI_pixel_V8HI, /* __vector __pixel */ |
| 2413 RS6000_BTI_long, /* long_integer_type_node */ | |
| 2414 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ | |
|
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2415 RS6000_BTI_long_long, /* long_long_integer_type_node */ |
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2416 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ |
| 131 | 2417 RS6000_BTI_INTQI, /* (signed) intQI_type_node */ |
| 0 | 2418 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ |
| 2419 RS6000_BTI_INTHI, /* intHI_type_node */ | |
| 2420 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ | |
| 131 | 2421 RS6000_BTI_INTSI, /* intSI_type_node (signed) */ |
| 0 | 2422 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ |
|
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2423 RS6000_BTI_INTDI, /* intDI_type_node */ |
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2424 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ |
| 111 | 2425 RS6000_BTI_INTTI, /* intTI_type_node */ |
| 2426 RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */ | |
| 0 | 2427 RS6000_BTI_float, /* float_type_node */ |
|
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2428 RS6000_BTI_double, /* double_type_node */ |
| 111 | 2429 RS6000_BTI_long_double, /* long_double_type_node */ |
| 2430 RS6000_BTI_dfloat64, /* dfloat64_type_node */ | |
| 2431 RS6000_BTI_dfloat128, /* dfloat128_type_node */ | |
| 0 | 2432 RS6000_BTI_void, /* void_type_node */ |
| 111 | 2433 RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */ |
| 2434 RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */ | |
| 2435 RS6000_BTI_const_str, /* pointer to const char * */ | |
| 0 | 2436 RS6000_BTI_MAX |
| 2437 }; | |
| 2438 | |
| 2439 | |
| 2440 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) | |
| 2441 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) | |
| 111 | 2442 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI]) |
|
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2443 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) |
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2444 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) |
| 0 | 2445 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) |
| 2446 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) | |
| 2447 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) | |
| 2448 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) | |
| 2449 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) | |
| 111 | 2450 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI]) |
| 0 | 2451 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) |
| 2452 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) | |
|
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2453 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) |
| 0 | 2454 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) |
| 2455 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) | |
| 2456 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) | |
| 131 | 2457 #define bool_long_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long_long]) |
| 0 | 2458 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) |
| 2459 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) | |
| 2460 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) | |
| 2461 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) | |
|
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2462 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) |
| 0 | 2463 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) |
| 2464 | |
|
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2465 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) |
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f6334be47118
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parents:
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2466 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) |
| 0 | 2467 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) |
| 2468 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) | |
| 2469 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) | |
| 2470 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) | |
| 2471 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) | |
| 2472 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) | |
| 2473 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) | |
| 2474 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) | |
|
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2475 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) |
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2476 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) |
| 111 | 2477 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI]) |
| 2478 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI]) | |
| 0 | 2479 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) |
|
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2480 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) |
| 111 | 2481 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double]) |
| 2482 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64]) | |
| 2483 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128]) | |
| 0 | 2484 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) |
| 111 | 2485 #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float]) |
| 2486 #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float]) | |
| 2487 #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str]) | |
| 0 | 2488 |
| 2489 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; | |
| 2490 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; | |
| 2491 | |
| 111 | 2492 #define TARGET_SUPPORTS_WIDE_INT 1 |
| 2493 | |
| 2494 #if (GCC_VERSION >= 3000) | |
| 2495 #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128 | |
| 2496 #endif |