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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
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1 ;; Pipeline description for the AppliedMicro Titan core.
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2 ;; Copyright (C) 2010-2018 Free Software Foundation, Inc.
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3 ;; Contributed by Theobroma Systems Design und Consulting GmbH
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; AppliedMicro Titan core complex
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22
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23 (define_automaton "titan_core,titan_fpu,titan_fxu,titan_bpu,titan_lsu")
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24 (define_cpu_unit "titan_issue_0,titan_issue_1" "titan_core")
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25
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26 ;; Some useful abbreviations.
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27 (define_reservation "titan_issue" "titan_issue_0|titan_issue_1")
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28
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29 ;; === FXU scheduling ===
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30
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31 (define_cpu_unit "titan_fxu_sh,titan_fxu_wb" "titan_fxu")
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32
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33 ;; The 1-cycle adder executes add, addi, subf, neg, compare and trap
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34 ;; instructions. It provides its own, dedicated result-bus, so we
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35 ;; don't need the titan_fxu_wb reservation to complete.
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36 (define_insn_reservation "titan_fxu_adder" 1
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37 (and (ior (eq_attr "type" "cmp,trap")
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38 (and (eq_attr "type" "add,logical")
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39 (eq_attr "dot" "yes")))
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40 (eq_attr "cpu" "titan"))
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41 "titan_issue,titan_fxu_sh")
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42
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43 (define_insn_reservation "titan_imul" 5
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44 (and (eq_attr "type" "mul")
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45 (eq_attr "cpu" "titan"))
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46 "titan_issue,titan_fxu_sh,nothing*5,titan_fxu_wb")
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47
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48 (define_insn_reservation "titan_mulhw" 4
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49 (and (eq_attr "type" "halfmul")
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50 (eq_attr "cpu" "titan"))
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51 "titan_issue,titan_fxu_sh,nothing*4,titan_fxu_wb")
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52
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53 (define_bypass 2 "titan_mulhw" "titan_mulhw")
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54
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55 (define_insn_reservation "titan_fxu_shift_and_rotate" 2
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56 (and (eq_attr "type" "insert,shift,cntlz")
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57 (eq_attr "cpu" "titan"))
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58 "titan_issue,titan_fxu_sh,nothing*2,titan_fxu_wb")
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59
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60 ;; We model the divider for the worst-case (i.e. a full 32-bit
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61 ;; divide). To model the bypass for byte-wise completion, a
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62 ;; define_bypass with a guard-function could be used... however, this
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63 ;; would be an optimization of doubtful value, as a large number of
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64 ;; divides will operate on 32-bit variables.
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65
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66 ;; To avoid an unmanagably large automata (generating the automata
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67 ;; would require well over 2GB in memory), we don't model the shared
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68 ;; result bus on this one. The divider-pipeline is thus modeled
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69 ;; through its latency and initial disptach bottlenecks (i.e. issue
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70 ;; slots and fxu scheduler availability)
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71 (define_insn_reservation "titan_fxu_div" 34
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72 (and (eq_attr "type" "div")
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73 (eq_attr "cpu" "titan"))
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74 "titan_issue,titan_fxu_sh")
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75
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76 (define_insn_reservation "titan_fxu_alu" 1
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77 (and (ior (eq_attr "type" "integer,exts")
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78 (and (eq_attr "type" "add,logical")
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79 (eq_attr "dot" "no")))
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80 (eq_attr "cpu" "titan"))
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81 "titan_issue,titan_fxu_sh,nothing,titan_fxu_wb")
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82
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83 ;; === BPU scheduling ===
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84
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85 (define_cpu_unit "titan_bpu_sh" "titan_bpu")
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86
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87 (define_insn_reservation "titan_bpu" 2
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88 (and (eq_attr "type" "branch,jmpreg,cr_logical")
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89 (eq_attr "cpu" "titan"))
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90 "titan_issue,titan_bpu_sh")
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91
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92 ;; === LSU scheduling ===
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93
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94 (define_cpu_unit "titan_lsu_sh" "titan_lsu")
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95
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96 ;; Loads.
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97 (define_insn_reservation "titan_lsu_load" 3
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98 (and (eq_attr "type" "load,load_l,sync")
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99 (eq_attr "cpu" "titan"))
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100 "titan_issue,titan_lsu_sh")
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101
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102 (define_insn_reservation "titan_lsu_fpload" 12
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103 (and (eq_attr "type" "fpload")
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104 (eq_attr "cpu" "titan"))
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105 "titan_issue,titan_lsu_sh")
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106
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107 ;; Note that the isync is not clearly placed within any execution
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108 ;; unit. We've made the assumption that it will be running out of the
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109 ;; LSU, as msync is also executed within the LSU.
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110 (define_insn_reservation "titan_lsu_sync" 20
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111 (and (eq_attr "type" "sync")
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112 (eq_attr "cpu" "titan"))
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113 "titan_issue,titan_lsu_sh*20")
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114
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115 ;; Stores.
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116 (define_insn_reservation "titan_lsu_store" 12
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117 (and (eq_attr "type" "store,store_c")
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118 (eq_attr "cpu" "titan"))
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119 "titan_issue,titan_lsu_sh")
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120
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121 (define_insn_reservation "titan_lsu_fpstore" 12
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122 (and (eq_attr "type" "fpstore")
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123 (eq_attr "cpu" "titan"))
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124 "titan_issue,titan_lsu_sh")
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125
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126 ;; === FPU scheduling ===
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127
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128 ;; In order to keep the automaton for the Titan FPU efficient and
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129 ;; maintainable, we've kept in as concise as possible and created a
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130 ;; mapping for the main "choke points" only instead of modelling the
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131 ;; overall flow of instructions through the FP-pipeline(s).
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132
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133 ;; The key elements modelled are:
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134 ;; * each FP-instruction takes up one of the two issue slots
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135 ;; * the FPU runs at half the core frequency
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136 ;; * divides are not pipelined (but execute in a separate unit)
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137 ;; * the FPU has a shared result bus for all its units
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138
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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139 (define_cpu_unit "titan_fp0,titan_fpdiv,titan_fpwb" "titan_fpu")
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140
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141 (define_insn_reservation "titan_fp_div_double" 72
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142 (and (eq_attr "type" "ddiv")
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143 (eq_attr "cpu" "titan"))
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144 "titan_issue,titan_fpdiv*72,titan_fpwb")
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145
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146 (define_insn_reservation "titan_fp_div_single" 46
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147 (and (eq_attr "type" "sdiv")
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148 (eq_attr "cpu" "titan"))
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149 "titan_issue,titan_fpdiv*46,titan_fpwb")
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150
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151 ;; Make sure the "titan_fp" rule stays last, as it's a catch all for
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152 ;; double-precision and unclassified (e.g. fsel) FP-instructions
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153 (define_insn_reservation "titan_fp" 10
111
kono
parents: 68
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154 (and (eq_attr "type" "fpcompare,fp,fpsimple,dmul")
68
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155 (eq_attr "cpu" "titan"))
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156 "titan_issue,titan_fp0*2,nothing*8,titan_fpwb")
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157
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158 ;; Please note, that the non-pipelined FP-instructions "mcrfs",
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159 ;; "mtfsb0[.]", "mtfsb1[.]", "mtfsf[.]", "mtfsfi[.]" are not
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160 ;; accessible from regular language constructs (i.e. they are not used
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161 ;; by the code generator, except for special purpose sequences defined
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162 ;; in rs6000.md), no special provisions are made for these.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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163