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131
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1 /* Copyright (C) 2002-2018 Free Software Foundation, Inc.
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111
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2
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3 This file is part of GCC.
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4
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5 GCC is free software; you can redistribute it and/or modify
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6 it under the terms of the GNU General Public License as published by
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7 the Free Software Foundation; either version 3, or (at your option)
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8 any later version.
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9
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10 GCC is distributed in the hope that it will be useful,
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11 but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 GNU General Public License for more details.
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14
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15 Under Section 7 of GPL version 3, you are granted additional
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16 permissions described in the GCC Runtime Library Exception, version
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17 3.1, as published by the Free Software Foundation.
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18
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19 You should have received a copy of the GNU General Public License and
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20 a copy of the GCC Runtime Library Exception along with this program;
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21 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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22 <http://www.gnu.org/licenses/>. */
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23
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24 /* Implemented from the specification included in the Intel C++ Compiler
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25 User Guide and Reference, version 9.0. */
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26
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27 #ifndef NO_WARN_X86_INTRINSICS
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28 /* This header is distributed to simplify porting x86_64 code that
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29 makes explicit use of Intel intrinsics to powerpc64le.
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30 It is the user's responsibility to determine if the results are
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31 acceptable and make additional changes as necessary.
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32 Note that much code that uses Intel intrinsics can be rewritten in
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33 standard C or GNU C extensions, which are more portable and better
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34 optimized across multiple targets.
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35
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36 In the specific case of X86 SSE (__m128) intrinsics, the PowerPC
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37 VMX/VSX ISA is a good match for vector float SIMD operations.
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38 However scalar float operations in vector (XMM) registers require
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39 the POWER8 VSX ISA (2.07) level. Also there are important
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40 differences for data format and placement of float scalars in the
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41 vector register. For PowerISA Scalar floats in FPRs (left most
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42 64-bits of the low 32 VSRs) is in double format, while X86_64 SSE
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43 uses the right most 32-bits of the XMM. These differences require
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44 extra steps on POWER to match the SSE scalar float semantics.
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45
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46 Most SSE scalar float intrinsic operations can be performed more
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47 efficiently as C language float scalar operations or optimized to
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48 use vector SIMD operations. We recommend this for new applications.
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49
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50 Another difference is the format and details of the X86_64 MXSCR vs
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51 the PowerISA FPSCR / VSCR registers. We recommend applications
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52 replace direct access to the MXSCR with the more portable <fenv.h>
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53 Posix APIs. */
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131
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54 #error "Please read comment above. Use -DNO_WARN_X86_INTRINSICS to disable this error."
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111
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55 #endif
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56
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57 #ifndef _XMMINTRIN_H_INCLUDED
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58 #define _XMMINTRIN_H_INCLUDED
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59
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131
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60 /* Define four value permute mask */
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61 #define _MM_SHUFFLE(w,x,y,z) (((w) << 6) | ((x) << 4) | ((y) << 2) | (z))
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62
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111
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63 #include <altivec.h>
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131
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64
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65 /* Avoid collisions between altivec.h and strict adherence to C++ and
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66 C11 standards. This should eventually be done inside altivec.h itself,
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67 but only after testing a full distro build. */
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68 #if defined(__STRICT_ANSI__) && (defined(__cplusplus) || \
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69 (defined(__STDC_VERSION__) && \
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70 __STDC_VERSION__ >= 201112L))
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71 #undef vector
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72 #undef pixel
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73 #undef bool
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74 #endif
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75
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111
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76 #include <assert.h>
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77
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78 /* We need type definitions from the MMX header file. */
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79 #include <mmintrin.h>
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80
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81 /* Get _mm_malloc () and _mm_free (). */
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82 #include <mm_malloc.h>
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83
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84 /* The Intel API is flexible enough that we must allow aliasing with other
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85 vector types, and their scalar components. */
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86 typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
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87
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131
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88 /* Unaligned version of the same type. */
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89 typedef float __m128_u __attribute__ ((__vector_size__ (16), __may_alias__,
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90 __aligned__ (1)));
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91
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111
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92 /* Internal data types for implementing the intrinsics. */
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93 typedef float __v4sf __attribute__ ((__vector_size__ (16)));
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94
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95 /* Create an undefined vector. */
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96 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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97 _mm_undefined_ps (void)
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98 {
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99 __m128 __Y = __Y;
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100 return __Y;
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101 }
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102
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103 /* Create a vector of zeros. */
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104 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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105 _mm_setzero_ps (void)
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106 {
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107 return __extension__ (__m128){ 0.0f, 0.0f, 0.0f, 0.0f };
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108 }
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109
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110 /* Load four SPFP values from P. The address must be 16-byte aligned. */
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111 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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112 _mm_load_ps (float const *__P)
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113 {
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114 assert(((unsigned long)__P & 0xfUL) == 0UL);
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115 return ((__m128)vec_ld(0, (__v4sf*)__P));
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116 }
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117
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118 /* Load four SPFP values from P. The address need not be 16-byte aligned. */
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119 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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120 _mm_loadu_ps (float const *__P)
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121 {
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122 return (vec_vsx_ld(0, __P));
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123 }
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124
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125 /* Load four SPFP values in reverse order. The address must be aligned. */
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126 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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127 _mm_loadr_ps (float const *__P)
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128 {
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129 __v4sf __tmp;
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130 __m128 result;
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131 static const __vector unsigned char permute_vector =
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132 { 0x1C, 0x1D, 0x1E, 0x1F, 0x18, 0x19, 0x1A, 0x1B, 0x14, 0x15, 0x16,
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133 0x17, 0x10, 0x11, 0x12, 0x13 };
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134
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135 __tmp = vec_ld (0, (__v4sf *) __P);
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136 result = (__m128) vec_perm (__tmp, __tmp, permute_vector);
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137 return result;
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138 }
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139
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140 /* Create a vector with all four elements equal to F. */
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141 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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142 _mm_set1_ps (float __F)
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143 {
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144 return __extension__ (__m128)(__v4sf){ __F, __F, __F, __F };
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145 }
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146
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147 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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148 _mm_set_ps1 (float __F)
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149 {
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150 return _mm_set1_ps (__F);
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151 }
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152
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153 /* Create the vector [Z Y X W]. */
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154 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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155 _mm_set_ps (const float __Z, const float __Y, const float __X, const float __W)
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156 {
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157 return __extension__ (__m128)(__v4sf){ __W, __X, __Y, __Z };
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158 }
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159
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160 /* Create the vector [W X Y Z]. */
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161 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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162 _mm_setr_ps (float __Z, float __Y, float __X, float __W)
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163 {
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164 return __extension__ (__m128)(__v4sf){ __Z, __Y, __X, __W };
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165 }
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166
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167 /* Store four SPFP values. The address must be 16-byte aligned. */
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168 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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169 _mm_store_ps (float *__P, __m128 __A)
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170 {
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171 assert(((unsigned long)__P & 0xfUL) == 0UL);
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172 vec_st((__v4sf)__A, 0, (__v4sf*)__P);
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173 }
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174
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175 /* Store four SPFP values. The address need not be 16-byte aligned. */
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176 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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177 _mm_storeu_ps (float *__P, __m128 __A)
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178 {
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131
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179 *(__m128_u *)__P = __A;
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111
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180 }
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181
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182 /* Store four SPFP values in reverse order. The address must be aligned. */
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183 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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184 _mm_storer_ps (float *__P, __m128 __A)
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185 {
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186 __v4sf __tmp;
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187 static const __vector unsigned char permute_vector =
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188 { 0x1C, 0x1D, 0x1E, 0x1F, 0x18, 0x19, 0x1A, 0x1B, 0x14, 0x15, 0x16,
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189 0x17, 0x10, 0x11, 0x12, 0x13 };
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190
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191 __tmp = (__m128) vec_perm (__A, __A, permute_vector);
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192
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193 _mm_store_ps (__P, __tmp);
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194 }
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195
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196 /* Store the lower SPFP value across four words. */
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197 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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198 _mm_store1_ps (float *__P, __m128 __A)
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199 {
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200 __v4sf __va = vec_splat((__v4sf)__A, 0);
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201 _mm_store_ps (__P, __va);
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202 }
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203
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204 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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205 _mm_store_ps1 (float *__P, __m128 __A)
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206 {
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207 _mm_store1_ps (__P, __A);
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208 }
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209
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210 /* Create a vector with element 0 as F and the rest zero. */
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211 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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212 _mm_set_ss (float __F)
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213 {
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214 return __extension__ (__m128)(__v4sf){ __F, 0.0f, 0.0f, 0.0f };
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215 }
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216
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217 /* Sets the low SPFP value of A from the low value of B. */
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218 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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219 _mm_move_ss (__m128 __A, __m128 __B)
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220 {
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221 static const __vector unsigned int mask = {0xffffffff, 0, 0, 0};
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222
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223 return (vec_sel ((__v4sf)__A, (__v4sf)__B, mask));
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224 }
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225
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226 /* Create a vector with element 0 as *P and the rest zero. */
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227 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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228 _mm_load_ss (float const *__P)
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229 {
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230 return _mm_set_ss (*__P);
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231 }
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232
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233 /* Stores the lower SPFP value. */
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234 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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235 _mm_store_ss (float *__P, __m128 __A)
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236 {
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237 *__P = ((__v4sf)__A)[0];
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238 }
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239
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240 /* Perform the respective operation on the lower SPFP (single-precision
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241 floating-point) values of A and B; the upper three SPFP values are
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242 passed through from A. */
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243
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244 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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245 _mm_add_ss (__m128 __A, __m128 __B)
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246 {
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247 #ifdef _ARCH_PWR7
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248 __m128 a, b, c;
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249 static const __vector unsigned int mask = {0xffffffff, 0, 0, 0};
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250 /* PowerISA VSX does not allow partial (for just lower double)
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251 results. So to insure we don't generate spurious exceptions
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252 (from the upper double values) we splat the lower double
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253 before we to the operation. */
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254 a = vec_splat (__A, 0);
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255 b = vec_splat (__B, 0);
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256 c = a + b;
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257 /* Then we merge the lower float result with the original upper
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258 float elements from __A. */
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259 return (vec_sel (__A, c, mask));
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260 #else
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261 __A[0] = __A[0] + __B[0];
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262 return (__A);
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263 #endif
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264 }
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265
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266 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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267 _mm_sub_ss (__m128 __A, __m128 __B)
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268 {
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269 #ifdef _ARCH_PWR7
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270 __m128 a, b, c;
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271 static const __vector unsigned int mask = {0xffffffff, 0, 0, 0};
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272 /* PowerISA VSX does not allow partial (for just lower double)
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273 results. So to insure we don't generate spurious exceptions
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274 (from the upper double values) we splat the lower double
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275 before we to the operation. */
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276 a = vec_splat (__A, 0);
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277 b = vec_splat (__B, 0);
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278 c = a - b;
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279 /* Then we merge the lower float result with the original upper
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280 float elements from __A. */
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281 return (vec_sel (__A, c, mask));
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282 #else
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283 __A[0] = __A[0] - __B[0];
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284 return (__A);
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285 #endif
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286 }
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287
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288 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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289 _mm_mul_ss (__m128 __A, __m128 __B)
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290 {
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291 #ifdef _ARCH_PWR7
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292 __m128 a, b, c;
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293 static const __vector unsigned int mask = {0xffffffff, 0, 0, 0};
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294 /* PowerISA VSX does not allow partial (for just lower double)
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295 results. So to insure we don't generate spurious exceptions
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296 (from the upper double values) we splat the lower double
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297 before we to the operation. */
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298 a = vec_splat (__A, 0);
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299 b = vec_splat (__B, 0);
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300 c = a * b;
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301 /* Then we merge the lower float result with the original upper
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302 float elements from __A. */
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303 return (vec_sel (__A, c, mask));
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304 #else
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305 __A[0] = __A[0] * __B[0];
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306 return (__A);
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307 #endif
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308 }
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309
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310 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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311 _mm_div_ss (__m128 __A, __m128 __B)
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312 {
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313 #ifdef _ARCH_PWR7
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314 __m128 a, b, c;
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315 static const __vector unsigned int mask = {0xffffffff, 0, 0, 0};
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316 /* PowerISA VSX does not allow partial (for just lower double)
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317 results. So to insure we don't generate spurious exceptions
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318 (from the upper double values) we splat the lower double
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319 before we to the operation. */
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320 a = vec_splat (__A, 0);
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321 b = vec_splat (__B, 0);
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322 c = a / b;
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323 /* Then we merge the lower float result with the original upper
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324 float elements from __A. */
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325 return (vec_sel (__A, c, mask));
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326 #else
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327 __A[0] = __A[0] / __B[0];
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328 return (__A);
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329 #endif
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330 }
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331
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332 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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333 _mm_sqrt_ss (__m128 __A)
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334 {
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335 __m128 a, c;
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336 static const __vector unsigned int mask = {0xffffffff, 0, 0, 0};
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337 /* PowerISA VSX does not allow partial (for just lower double)
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338 * results. So to insure we don't generate spurious exceptions
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339 * (from the upper double values) we splat the lower double
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340 * before we to the operation. */
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341 a = vec_splat (__A, 0);
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342 c = vec_sqrt (a);
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343 /* Then we merge the lower float result with the original upper
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344 * float elements from __A. */
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345 return (vec_sel (__A, c, mask));
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346 }
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347
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348 /* Perform the respective operation on the four SPFP values in A and B. */
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349 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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350 _mm_add_ps (__m128 __A, __m128 __B)
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351 {
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352 return (__m128) ((__v4sf)__A + (__v4sf)__B);
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353 }
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354
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355 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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356 _mm_sub_ps (__m128 __A, __m128 __B)
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357 {
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358 return (__m128) ((__v4sf)__A - (__v4sf)__B);
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359 }
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360
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361 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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362 _mm_mul_ps (__m128 __A, __m128 __B)
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363 {
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364 return (__m128) ((__v4sf)__A * (__v4sf)__B);
|
|
|
365 }
|
|
|
366
|
|
|
367 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
368 _mm_div_ps (__m128 __A, __m128 __B)
|
|
|
369 {
|
|
|
370 return (__m128) ((__v4sf)__A / (__v4sf)__B);
|
|
|
371 }
|
|
|
372
|
|
|
373 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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|
|
374 _mm_sqrt_ps (__m128 __A)
|
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375 {
|
|
|
376 return (vec_sqrt ((__v4sf)__A));
|
|
|
377 }
|
|
|
378
|
|
|
379 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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|
|
380 _mm_rcp_ps (__m128 __A)
|
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381 {
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|
|
382 return (vec_re ((__v4sf)__A));
|
|
|
383 }
|
|
|
384
|
|
|
385 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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|
|
386 _mm_rsqrt_ps (__m128 __A)
|
|
|
387 {
|
|
|
388 return (vec_rsqrte (__A));
|
|
|
389 }
|
|
|
390
|
|
|
391 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
392 _mm_rcp_ss (__m128 __A)
|
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|
393 {
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|
|
394 __m128 a, c;
|
|
|
395 static const __vector unsigned int mask = {0xffffffff, 0, 0, 0};
|
|
|
396 /* PowerISA VSX does not allow partial (for just lower double)
|
|
|
397 * results. So to insure we don't generate spurious exceptions
|
|
|
398 * (from the upper double values) we splat the lower double
|
|
|
399 * before we to the operation. */
|
|
|
400 a = vec_splat (__A, 0);
|
|
|
401 c = _mm_rcp_ps (a);
|
|
|
402 /* Then we merge the lower float result with the original upper
|
|
|
403 * float elements from __A. */
|
|
|
404 return (vec_sel (__A, c, mask));
|
|
|
405 }
|
|
|
406
|
|
|
407 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
408 _mm_rsqrt_ss (__m128 __A)
|
|
|
409 {
|
|
|
410 __m128 a, c;
|
|
|
411 static const __vector unsigned int mask = {0xffffffff, 0, 0, 0};
|
|
|
412 /* PowerISA VSX does not allow partial (for just lower double)
|
|
|
413 * results. So to insure we don't generate spurious exceptions
|
|
|
414 * (from the upper double values) we splat the lower double
|
|
|
415 * before we to the operation. */
|
|
|
416 a = vec_splat (__A, 0);
|
|
|
417 c = vec_rsqrte (a);
|
|
|
418 /* Then we merge the lower float result with the original upper
|
|
|
419 * float elements from __A. */
|
|
|
420 return (vec_sel (__A, c, mask));
|
|
|
421 }
|
|
|
422
|
|
|
423 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
424 _mm_min_ss (__m128 __A, __m128 __B)
|
|
|
425 {
|
|
|
426 __v4sf a, b, c;
|
|
|
427 static const __vector unsigned int mask = {0xffffffff, 0, 0, 0};
|
|
|
428 /* PowerISA VSX does not allow partial (for just lower float)
|
|
|
429 * results. So to insure we don't generate spurious exceptions
|
|
|
430 * (from the upper float values) we splat the lower float
|
|
|
431 * before we to the operation. */
|
|
|
432 a = vec_splat ((__v4sf)__A, 0);
|
|
|
433 b = vec_splat ((__v4sf)__B, 0);
|
|
|
434 c = vec_min (a, b);
|
|
|
435 /* Then we merge the lower float result with the original upper
|
|
|
436 * float elements from __A. */
|
|
|
437 return (vec_sel ((__v4sf)__A, c, mask));
|
|
|
438 }
|
|
|
439
|
|
|
440 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
441 _mm_max_ss (__m128 __A, __m128 __B)
|
|
|
442 {
|
|
|
443 __v4sf a, b, c;
|
|
|
444 static const __vector unsigned int mask = {0xffffffff, 0, 0, 0};
|
|
|
445 /* PowerISA VSX does not allow partial (for just lower float)
|
|
|
446 * results. So to insure we don't generate spurious exceptions
|
|
|
447 * (from the upper float values) we splat the lower float
|
|
|
448 * before we to the operation. */
|
|
|
449 a = vec_splat (__A, 0);
|
|
|
450 b = vec_splat (__B, 0);
|
|
|
451 c = vec_max (a, b);
|
|
|
452 /* Then we merge the lower float result with the original upper
|
|
|
453 * float elements from __A. */
|
|
|
454 return (vec_sel ((__v4sf)__A, c, mask));
|
|
|
455 }
|
|
|
456
|
|
|
457 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
458 _mm_min_ps (__m128 __A, __m128 __B)
|
|
|
459 {
|
|
131
|
460 __m128 m = (__m128) vec_vcmpgtfp ((__v4sf) __B, (__v4sf) __A);
|
|
|
461 return vec_sel (__B, __A, m);
|
|
111
|
462 }
|
|
|
463
|
|
|
464 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
465 _mm_max_ps (__m128 __A, __m128 __B)
|
|
|
466 {
|
|
131
|
467 __m128 m = (__m128) vec_vcmpgtfp ((__v4sf) __A, (__v4sf) __B);
|
|
|
468 return vec_sel (__B, __A, m);
|
|
111
|
469 }
|
|
|
470
|
|
|
471 /* Perform logical bit-wise operations on 128-bit values. */
|
|
|
472 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
473 _mm_and_ps (__m128 __A, __m128 __B)
|
|
|
474 {
|
|
|
475 return ((__m128)vec_and ((__v4sf)__A, (__v4sf)__B));
|
|
|
476 // return __builtin_ia32_andps (__A, __B);
|
|
|
477 }
|
|
|
478
|
|
|
479 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
480 _mm_andnot_ps (__m128 __A, __m128 __B)
|
|
|
481 {
|
|
|
482 return ((__m128)vec_andc ((__v4sf)__B, (__v4sf)__A));
|
|
|
483 }
|
|
|
484
|
|
|
485 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
486 _mm_or_ps (__m128 __A, __m128 __B)
|
|
|
487 {
|
|
|
488 return ((__m128)vec_or ((__v4sf)__A, (__v4sf)__B));
|
|
|
489 }
|
|
|
490
|
|
|
491 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
492 _mm_xor_ps (__m128 __A, __m128 __B)
|
|
|
493 {
|
|
|
494 return ((__m128)vec_xor ((__v4sf)__A, (__v4sf)__B));
|
|
|
495 }
|
|
|
496
|
|
|
497 /* Perform a comparison on the four SPFP values of A and B. For each
|
|
|
498 element, if the comparison is true, place a mask of all ones in the
|
|
|
499 result, otherwise a mask of zeros. */
|
|
|
500 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
501 _mm_cmpeq_ps (__m128 __A, __m128 __B)
|
|
|
502 {
|
|
|
503 return ((__m128)vec_cmpeq ((__v4sf)__A,(__v4sf) __B));
|
|
|
504 }
|
|
|
505
|
|
|
506 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
507 _mm_cmplt_ps (__m128 __A, __m128 __B)
|
|
|
508 {
|
|
|
509 return ((__m128)vec_cmplt ((__v4sf)__A, (__v4sf)__B));
|
|
|
510 }
|
|
|
511
|
|
|
512 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
513 _mm_cmple_ps (__m128 __A, __m128 __B)
|
|
|
514 {
|
|
|
515 return ((__m128)vec_cmple ((__v4sf)__A, (__v4sf)__B));
|
|
|
516 }
|
|
|
517
|
|
|
518 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
519 _mm_cmpgt_ps (__m128 __A, __m128 __B)
|
|
|
520 {
|
|
|
521 return ((__m128)vec_cmpgt ((__v4sf)__A, (__v4sf)__B));
|
|
|
522 }
|
|
|
523
|
|
|
524 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
525 _mm_cmpge_ps (__m128 __A, __m128 __B)
|
|
|
526 {
|
|
|
527 return ((__m128)vec_cmpge ((__v4sf)__A, (__v4sf)__B));
|
|
|
528 }
|
|
|
529
|
|
|
530 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
531 _mm_cmpneq_ps (__m128 __A, __m128 __B)
|
|
|
532 {
|
|
|
533 __v4sf temp = (__v4sf ) vec_cmpeq ((__v4sf) __A, (__v4sf)__B);
|
|
|
534 return ((__m128)vec_nor (temp, temp));
|
|
|
535 }
|
|
|
536
|
|
|
537 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
538 _mm_cmpnlt_ps (__m128 __A, __m128 __B)
|
|
|
539 {
|
|
|
540 return ((__m128)vec_cmpge ((__v4sf)__A, (__v4sf)__B));
|
|
|
541 }
|
|
|
542
|
|
|
543 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
544 _mm_cmpnle_ps (__m128 __A, __m128 __B)
|
|
|
545 {
|
|
|
546 return ((__m128)vec_cmpgt ((__v4sf)__A, (__v4sf)__B));
|
|
|
547 }
|
|
|
548
|
|
|
549 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
550 _mm_cmpngt_ps (__m128 __A, __m128 __B)
|
|
|
551 {
|
|
|
552 return ((__m128)vec_cmple ((__v4sf)__A, (__v4sf)__B));
|
|
|
553 }
|
|
|
554
|
|
|
555 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
556 _mm_cmpnge_ps (__m128 __A, __m128 __B)
|
|
|
557 {
|
|
|
558 return ((__m128)vec_cmplt ((__v4sf)__A, (__v4sf)__B));
|
|
|
559 }
|
|
|
560
|
|
|
561 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
562 _mm_cmpord_ps (__m128 __A, __m128 __B)
|
|
|
563 {
|
|
|
564 __vector unsigned int a, b;
|
|
|
565 __vector unsigned int c, d;
|
|
|
566 static const __vector unsigned int float_exp_mask =
|
|
|
567 { 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000 };
|
|
|
568
|
|
|
569 a = (__vector unsigned int) vec_abs ((__v4sf)__A);
|
|
|
570 b = (__vector unsigned int) vec_abs ((__v4sf)__B);
|
|
|
571 c = (__vector unsigned int) vec_cmpgt (float_exp_mask, a);
|
|
|
572 d = (__vector unsigned int) vec_cmpgt (float_exp_mask, b);
|
|
|
573 return ((__m128 ) vec_and (c, d));
|
|
|
574 }
|
|
|
575
|
|
|
576 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
577 _mm_cmpunord_ps (__m128 __A, __m128 __B)
|
|
|
578 {
|
|
|
579 __vector unsigned int a, b;
|
|
|
580 __vector unsigned int c, d;
|
|
|
581 static const __vector unsigned int float_exp_mask =
|
|
|
582 { 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000 };
|
|
|
583
|
|
|
584 a = (__vector unsigned int) vec_abs ((__v4sf)__A);
|
|
|
585 b = (__vector unsigned int) vec_abs ((__v4sf)__B);
|
|
|
586 c = (__vector unsigned int) vec_cmpgt (a, float_exp_mask);
|
|
|
587 d = (__vector unsigned int) vec_cmpgt (b, float_exp_mask);
|
|
|
588 return ((__m128 ) vec_or (c, d));
|
|
|
589 }
|
|
|
590
|
|
|
591 /* Perform a comparison on the lower SPFP values of A and B. If the
|
|
|
592 comparison is true, place a mask of all ones in the result, otherwise a
|
|
|
593 mask of zeros. The upper three SPFP values are passed through from A. */
|
|
|
594 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
595 _mm_cmpeq_ss (__m128 __A, __m128 __B)
|
|
|
596 {
|
|
|
597 static const __vector unsigned int mask =
|
|
|
598 { 0xffffffff, 0, 0, 0 };
|
|
|
599 __v4sf a, b, c;
|
|
|
600 /* PowerISA VMX does not allow partial (for just element 0)
|
|
|
601 * results. So to insure we don't generate spurious exceptions
|
|
|
602 * (from the upper elements) we splat the lower float
|
|
|
603 * before we to the operation. */
|
|
|
604 a = vec_splat ((__v4sf) __A, 0);
|
|
|
605 b = vec_splat ((__v4sf) __B, 0);
|
|
|
606 c = (__v4sf) vec_cmpeq(a, b);
|
|
|
607 /* Then we merge the lower float result with the original upper
|
|
|
608 * float elements from __A. */
|
|
|
609 return ((__m128)vec_sel ((__v4sf)__A, c, mask));
|
|
|
610 }
|
|
|
611
|
|
|
612 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
613 _mm_cmplt_ss (__m128 __A, __m128 __B)
|
|
|
614 {
|
|
|
615 static const __vector unsigned int mask =
|
|
|
616 { 0xffffffff, 0, 0, 0 };
|
|
|
617 __v4sf a, b, c;
|
|
|
618 /* PowerISA VMX does not allow partial (for just element 0)
|
|
|
619 * results. So to insure we don't generate spurious exceptions
|
|
|
620 * (from the upper elements) we splat the lower float
|
|
|
621 * before we to the operation. */
|
|
|
622 a = vec_splat ((__v4sf) __A, 0);
|
|
|
623 b = vec_splat ((__v4sf) __B, 0);
|
|
|
624 c = (__v4sf) vec_cmplt(a, b);
|
|
|
625 /* Then we merge the lower float result with the original upper
|
|
|
626 * float elements from __A. */
|
|
|
627 return ((__m128)vec_sel ((__v4sf)__A, c, mask));
|
|
|
628 }
|
|
|
629
|
|
|
630 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
631 _mm_cmple_ss (__m128 __A, __m128 __B)
|
|
|
632 {
|
|
|
633 static const __vector unsigned int mask =
|
|
|
634 { 0xffffffff, 0, 0, 0 };
|
|
|
635 __v4sf a, b, c;
|
|
|
636 /* PowerISA VMX does not allow partial (for just element 0)
|
|
|
637 * results. So to insure we don't generate spurious exceptions
|
|
|
638 * (from the upper elements) we splat the lower float
|
|
|
639 * before we to the operation. */
|
|
|
640 a = vec_splat ((__v4sf) __A, 0);
|
|
|
641 b = vec_splat ((__v4sf) __B, 0);
|
|
|
642 c = (__v4sf) vec_cmple(a, b);
|
|
|
643 /* Then we merge the lower float result with the original upper
|
|
|
644 * float elements from __A. */
|
|
|
645 return ((__m128)vec_sel ((__v4sf)__A, c, mask));
|
|
|
646 }
|
|
|
647
|
|
|
648 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
649 _mm_cmpgt_ss (__m128 __A, __m128 __B)
|
|
|
650 {
|
|
|
651 static const __vector unsigned int mask =
|
|
|
652 { 0xffffffff, 0, 0, 0 };
|
|
|
653 __v4sf a, b, c;
|
|
|
654 /* PowerISA VMX does not allow partial (for just element 0)
|
|
|
655 * results. So to insure we don't generate spurious exceptions
|
|
|
656 * (from the upper elements) we splat the lower float
|
|
|
657 * before we to the operation. */
|
|
|
658 a = vec_splat ((__v4sf) __A, 0);
|
|
|
659 b = vec_splat ((__v4sf) __B, 0);
|
|
|
660 c = (__v4sf) vec_cmpgt(a, b);
|
|
|
661 /* Then we merge the lower float result with the original upper
|
|
|
662 * float elements from __A. */
|
|
|
663 return ((__m128)vec_sel ((__v4sf)__A, c, mask));
|
|
|
664 }
|
|
|
665
|
|
|
666 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
667 _mm_cmpge_ss (__m128 __A, __m128 __B)
|
|
|
668 {
|
|
|
669 static const __vector unsigned int mask =
|
|
|
670 { 0xffffffff, 0, 0, 0 };
|
|
|
671 __v4sf a, b, c;
|
|
|
672 /* PowerISA VMX does not allow partial (for just element 0)
|
|
|
673 * results. So to insure we don't generate spurious exceptions
|
|
|
674 * (from the upper elements) we splat the lower float
|
|
|
675 * before we to the operation. */
|
|
|
676 a = vec_splat ((__v4sf) __A, 0);
|
|
|
677 b = vec_splat ((__v4sf) __B, 0);
|
|
|
678 c = (__v4sf) vec_cmpge(a, b);
|
|
|
679 /* Then we merge the lower float result with the original upper
|
|
|
680 * float elements from __A. */
|
|
|
681 return ((__m128)vec_sel ((__v4sf)__A, c, mask));
|
|
|
682 }
|
|
|
683
|
|
|
684 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
685 _mm_cmpneq_ss (__m128 __A, __m128 __B)
|
|
|
686 {
|
|
|
687 static const __vector unsigned int mask =
|
|
|
688 { 0xffffffff, 0, 0, 0 };
|
|
|
689 __v4sf a, b, c;
|
|
|
690 /* PowerISA VMX does not allow partial (for just element 0)
|
|
|
691 * results. So to insure we don't generate spurious exceptions
|
|
|
692 * (from the upper elements) we splat the lower float
|
|
|
693 * before we to the operation. */
|
|
|
694 a = vec_splat ((__v4sf) __A, 0);
|
|
|
695 b = vec_splat ((__v4sf) __B, 0);
|
|
|
696 c = (__v4sf) vec_cmpeq(a, b);
|
|
|
697 c = vec_nor (c, c);
|
|
|
698 /* Then we merge the lower float result with the original upper
|
|
|
699 * float elements from __A. */
|
|
|
700 return ((__m128)vec_sel ((__v4sf)__A, c, mask));
|
|
|
701 }
|
|
|
702
|
|
|
703 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
704 _mm_cmpnlt_ss (__m128 __A, __m128 __B)
|
|
|
705 {
|
|
|
706 static const __vector unsigned int mask =
|
|
|
707 { 0xffffffff, 0, 0, 0 };
|
|
|
708 __v4sf a, b, c;
|
|
|
709 /* PowerISA VMX does not allow partial (for just element 0)
|
|
|
710 * results. So to insure we don't generate spurious exceptions
|
|
|
711 * (from the upper elements) we splat the lower float
|
|
|
712 * before we to the operation. */
|
|
|
713 a = vec_splat ((__v4sf) __A, 0);
|
|
|
714 b = vec_splat ((__v4sf) __B, 0);
|
|
|
715 c = (__v4sf) vec_cmpge(a, b);
|
|
|
716 /* Then we merge the lower float result with the original upper
|
|
|
717 * float elements from __A. */
|
|
|
718 return ((__m128)vec_sel ((__v4sf)__A, c, mask));
|
|
|
719 }
|
|
|
720
|
|
|
721 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
722 _mm_cmpnle_ss (__m128 __A, __m128 __B)
|
|
|
723 {
|
|
|
724 static const __vector unsigned int mask =
|
|
|
725 { 0xffffffff, 0, 0, 0 };
|
|
|
726 __v4sf a, b, c;
|
|
|
727 /* PowerISA VMX does not allow partial (for just element 0)
|
|
|
728 * results. So to insure we don't generate spurious exceptions
|
|
|
729 * (from the upper elements) we splat the lower float
|
|
|
730 * before we to the operation. */
|
|
|
731 a = vec_splat ((__v4sf) __A, 0);
|
|
|
732 b = vec_splat ((__v4sf) __B, 0);
|
|
|
733 c = (__v4sf) vec_cmpgt(a, b);
|
|
|
734 /* Then we merge the lower float result with the original upper
|
|
|
735 * float elements from __A. */
|
|
|
736 return ((__m128)vec_sel ((__v4sf)__A, c, mask));
|
|
|
737 }
|
|
|
738
|
|
|
739 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
740 _mm_cmpngt_ss (__m128 __A, __m128 __B)
|
|
|
741 {
|
|
|
742 static const __vector unsigned int mask =
|
|
|
743 { 0xffffffff, 0, 0, 0 };
|
|
|
744 __v4sf a, b, c;
|
|
|
745 /* PowerISA VMX does not allow partial (for just element 0)
|
|
|
746 * results. So to insure we don't generate spurious exceptions
|
|
|
747 * (from the upper elements) we splat the lower float
|
|
|
748 * before we to the operation. */
|
|
|
749 a = vec_splat ((__v4sf) __A, 0);
|
|
|
750 b = vec_splat ((__v4sf) __B, 0);
|
|
|
751 c = (__v4sf) vec_cmple(a, b);
|
|
|
752 /* Then we merge the lower float result with the original upper
|
|
|
753 * float elements from __A. */
|
|
|
754 return ((__m128)vec_sel ((__v4sf)__A, c, mask));
|
|
|
755 }
|
|
|
756
|
|
|
757 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
758 _mm_cmpnge_ss (__m128 __A, __m128 __B)
|
|
|
759 {
|
|
|
760 static const __vector unsigned int mask =
|
|
|
761 { 0xffffffff, 0, 0, 0 };
|
|
|
762 __v4sf a, b, c;
|
|
|
763 /* PowerISA VMX does not allow partial (for just element 0)
|
|
|
764 * results. So to insure we don't generate spurious exceptions
|
|
|
765 * (from the upper elements) we splat the lower float
|
|
|
766 * before we do the operation. */
|
|
|
767 a = vec_splat ((__v4sf) __A, 0);
|
|
|
768 b = vec_splat ((__v4sf) __B, 0);
|
|
|
769 c = (__v4sf) vec_cmplt(a, b);
|
|
|
770 /* Then we merge the lower float result with the original upper
|
|
|
771 * float elements from __A. */
|
|
|
772 return ((__m128)vec_sel ((__v4sf)__A, c, mask));
|
|
|
773 }
|
|
|
774
|
|
|
775 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
776 _mm_cmpord_ss (__m128 __A, __m128 __B)
|
|
|
777 {
|
|
|
778 __vector unsigned int a, b;
|
|
|
779 __vector unsigned int c, d;
|
|
|
780 static const __vector unsigned int float_exp_mask =
|
|
|
781 { 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000 };
|
|
|
782 static const __vector unsigned int mask =
|
|
|
783 { 0xffffffff, 0, 0, 0 };
|
|
|
784
|
|
|
785 a = (__vector unsigned int) vec_abs ((__v4sf)__A);
|
|
|
786 b = (__vector unsigned int) vec_abs ((__v4sf)__B);
|
|
|
787 c = (__vector unsigned int) vec_cmpgt (float_exp_mask, a);
|
|
|
788 d = (__vector unsigned int) vec_cmpgt (float_exp_mask, b);
|
|
|
789 c = vec_and (c, d);
|
|
|
790 /* Then we merge the lower float result with the original upper
|
|
|
791 * float elements from __A. */
|
|
|
792 return ((__m128)vec_sel ((__v4sf)__A, (__v4sf)c, mask));
|
|
|
793 }
|
|
|
794
|
|
|
795 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
796 _mm_cmpunord_ss (__m128 __A, __m128 __B)
|
|
|
797 {
|
|
|
798 __vector unsigned int a, b;
|
|
|
799 __vector unsigned int c, d;
|
|
|
800 static const __vector unsigned int float_exp_mask =
|
|
|
801 { 0x7f800000, 0x7f800000, 0x7f800000, 0x7f800000 };
|
|
|
802 static const __vector unsigned int mask =
|
|
|
803 { 0xffffffff, 0, 0, 0 };
|
|
|
804
|
|
|
805 a = (__vector unsigned int) vec_abs ((__v4sf)__A);
|
|
|
806 b = (__vector unsigned int) vec_abs ((__v4sf)__B);
|
|
|
807 c = (__vector unsigned int) vec_cmpgt (a, float_exp_mask);
|
|
|
808 d = (__vector unsigned int) vec_cmpgt (b, float_exp_mask);
|
|
|
809 c = vec_or (c, d);
|
|
|
810 /* Then we merge the lower float result with the original upper
|
|
|
811 * float elements from __A. */
|
|
|
812 return ((__m128)vec_sel ((__v4sf)__A, (__v4sf)c, mask));
|
|
|
813 }
|
|
|
814
|
|
|
815 /* Compare the lower SPFP values of A and B and return 1 if true
|
|
|
816 and 0 if false. */
|
|
|
817 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
818 _mm_comieq_ss (__m128 __A, __m128 __B)
|
|
|
819 {
|
|
|
820 return (__A[0] == __B[0]);
|
|
|
821 }
|
|
|
822
|
|
|
823 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
824 _mm_comilt_ss (__m128 __A, __m128 __B)
|
|
|
825 {
|
|
|
826 return (__A[0] < __B[0]);
|
|
|
827 }
|
|
|
828
|
|
|
829 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
830 _mm_comile_ss (__m128 __A, __m128 __B)
|
|
|
831 {
|
|
|
832 return (__A[0] <= __B[0]);
|
|
|
833 }
|
|
|
834
|
|
|
835 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
836 _mm_comigt_ss (__m128 __A, __m128 __B)
|
|
|
837 {
|
|
|
838 return (__A[0] > __B[0]);
|
|
|
839 }
|
|
|
840
|
|
|
841 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
842 _mm_comige_ss (__m128 __A, __m128 __B)
|
|
|
843 {
|
|
|
844 return (__A[0] >= __B[0]);
|
|
|
845 }
|
|
|
846
|
|
|
847 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
848 _mm_comineq_ss (__m128 __A, __m128 __B)
|
|
|
849 {
|
|
|
850 return (__A[0] != __B[0]);
|
|
|
851 }
|
|
|
852
|
|
|
853 /* FIXME
|
|
|
854 * The __mm_ucomi??_ss implementations below are exactly the same as
|
|
|
855 * __mm_comi??_ss because GCC for PowerPC only generates unordered
|
|
|
856 * compares (scalar and vector).
|
|
|
857 * Technically __mm_comieq_ss et al should be using the ordered
|
|
|
858 * compare and signal for QNaNs.
|
|
|
859 * The __mm_ucomieq_sd et all should be OK, as is.
|
|
|
860 */
|
|
|
861 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
862 _mm_ucomieq_ss (__m128 __A, __m128 __B)
|
|
|
863 {
|
|
|
864 return (__A[0] == __B[0]);
|
|
|
865 }
|
|
|
866
|
|
|
867 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
868 _mm_ucomilt_ss (__m128 __A, __m128 __B)
|
|
|
869 {
|
|
|
870 return (__A[0] < __B[0]);
|
|
|
871 }
|
|
|
872
|
|
|
873 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
874 _mm_ucomile_ss (__m128 __A, __m128 __B)
|
|
|
875 {
|
|
|
876 return (__A[0] <= __B[0]);
|
|
|
877 }
|
|
|
878
|
|
|
879 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
880 _mm_ucomigt_ss (__m128 __A, __m128 __B)
|
|
|
881 {
|
|
|
882 return (__A[0] > __B[0]);
|
|
|
883 }
|
|
|
884
|
|
|
885 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
886 _mm_ucomige_ss (__m128 __A, __m128 __B)
|
|
|
887 {
|
|
|
888 return (__A[0] >= __B[0]);
|
|
|
889 }
|
|
|
890
|
|
|
891 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
892 _mm_ucomineq_ss (__m128 __A, __m128 __B)
|
|
|
893 {
|
|
|
894 return (__A[0] != __B[0]);
|
|
|
895 }
|
|
|
896
|
|
|
897 extern __inline float __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
898 _mm_cvtss_f32 (__m128 __A)
|
|
|
899 {
|
|
|
900 return ((__v4sf)__A)[0];
|
|
|
901 }
|
|
|
902
|
|
|
903 /* Convert the lower SPFP value to a 32-bit integer according to the current
|
|
|
904 rounding mode. */
|
|
|
905 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
906 _mm_cvtss_si32 (__m128 __A)
|
|
|
907 {
|
|
|
908 __m64 res = 0;
|
|
|
909 #ifdef _ARCH_PWR8
|
|
|
910 __m128 vtmp;
|
|
|
911 __asm__(
|
|
|
912 "xxsldwi %x1,%x2,%x2,3;\n"
|
|
|
913 "xscvspdp %x1,%x1;\n"
|
|
|
914 "fctiw %1,%1;\n"
|
|
|
915 "mfvsrd %0,%x1;\n"
|
|
|
916 : "=r" (res),
|
|
|
917 "=&wi" (vtmp)
|
|
|
918 : "wa" (__A)
|
|
|
919 : );
|
|
|
920 #else
|
|
|
921 res = __builtin_rint(__A[0]);
|
|
|
922 #endif
|
|
|
923 return (res);
|
|
|
924 }
|
|
|
925
|
|
|
926 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
927 _mm_cvt_ss2si (__m128 __A)
|
|
|
928 {
|
|
|
929 return _mm_cvtss_si32 (__A);
|
|
|
930 }
|
|
|
931
|
|
|
932 /* Convert the lower SPFP value to a 32-bit integer according to the
|
|
|
933 current rounding mode. */
|
|
|
934
|
|
|
935 /* Intel intrinsic. */
|
|
|
936 extern __inline long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
937 _mm_cvtss_si64 (__m128 __A)
|
|
|
938 {
|
|
|
939 __m64 res = 0;
|
|
|
940 #ifdef _ARCH_PWR8
|
|
|
941 __m128 vtmp;
|
|
|
942 __asm__(
|
|
|
943 "xxsldwi %x1,%x2,%x2,3;\n"
|
|
|
944 "xscvspdp %x1,%x1;\n"
|
|
|
945 "fctid %1,%1;\n"
|
|
|
946 "mfvsrd %0,%x1;\n"
|
|
|
947 : "=r" (res),
|
|
|
948 "=&wi" (vtmp)
|
|
|
949 : "wa" (__A)
|
|
|
950 : );
|
|
|
951 #else
|
|
|
952 res = __builtin_llrint(__A[0]);
|
|
|
953 #endif
|
|
|
954 return (res);
|
|
|
955 }
|
|
|
956
|
|
|
957 /* Microsoft intrinsic. */
|
|
|
958 extern __inline long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
959 _mm_cvtss_si64x (__m128 __A)
|
|
|
960 {
|
|
|
961 return _mm_cvtss_si64 ((__v4sf) __A);
|
|
|
962 }
|
|
|
963
|
|
|
964 /* Constants for use with _mm_prefetch. */
|
|
|
965 enum _mm_hint
|
|
|
966 {
|
|
|
967 /* _MM_HINT_ET is _MM_HINT_T with set 3rd bit. */
|
|
|
968 _MM_HINT_ET0 = 7,
|
|
|
969 _MM_HINT_ET1 = 6,
|
|
|
970 _MM_HINT_T0 = 3,
|
|
|
971 _MM_HINT_T1 = 2,
|
|
|
972 _MM_HINT_T2 = 1,
|
|
|
973 _MM_HINT_NTA = 0
|
|
|
974 };
|
|
|
975
|
|
|
976 /* Loads one cache line from address P to a location "closer" to the
|
|
|
977 processor. The selector I specifies the type of prefetch operation. */
|
|
|
978 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
979 _mm_prefetch (const void *__P, enum _mm_hint __I)
|
|
|
980 {
|
|
|
981 /* Current PowerPC will ignores the hint parameters. */
|
|
|
982 __builtin_prefetch (__P);
|
|
|
983 }
|
|
|
984
|
|
|
985 /* Convert the two lower SPFP values to 32-bit integers according to the
|
|
|
986 current rounding mode. Return the integers in packed form. */
|
|
|
987 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
988 _mm_cvtps_pi32 (__m128 __A)
|
|
|
989 {
|
|
|
990 /* Splat two lower SPFP values to both halves. */
|
|
|
991 __v4sf temp, rounded;
|
|
131
|
992 __vector unsigned long long result;
|
|
111
|
993
|
|
|
994 /* Splat two lower SPFP values to both halves. */
|
|
|
995 temp = (__v4sf) vec_splat ((__vector long long)__A, 0);
|
|
|
996 rounded = vec_rint(temp);
|
|
131
|
997 result = (__vector unsigned long long) vec_cts (rounded, 0);
|
|
111
|
998
|
|
|
999 return ((__m64) __builtin_unpack_vector_int128 ((__vector __int128)result, 0));
|
|
|
1000 }
|
|
|
1001
|
|
|
1002 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1003 _mm_cvt_ps2pi (__m128 __A)
|
|
|
1004 {
|
|
|
1005 return _mm_cvtps_pi32 (__A);
|
|
|
1006 }
|
|
|
1007
|
|
|
1008 /* Truncate the lower SPFP value to a 32-bit integer. */
|
|
|
1009 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1010 _mm_cvttss_si32 (__m128 __A)
|
|
|
1011 {
|
|
|
1012 /* Extract the lower float element. */
|
|
|
1013 float temp = __A[0];
|
|
|
1014 /* truncate to 32-bit integer and return. */
|
|
|
1015 return temp;
|
|
|
1016 }
|
|
|
1017
|
|
|
1018 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1019 _mm_cvtt_ss2si (__m128 __A)
|
|
|
1020 {
|
|
|
1021 return _mm_cvttss_si32 (__A);
|
|
|
1022 }
|
|
|
1023
|
|
|
1024 /* Intel intrinsic. */
|
|
|
1025 extern __inline long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1026 _mm_cvttss_si64 (__m128 __A)
|
|
|
1027 {
|
|
|
1028 /* Extract the lower float element. */
|
|
|
1029 float temp = __A[0];
|
|
|
1030 /* truncate to 32-bit integer and return. */
|
|
|
1031 return temp;
|
|
|
1032 }
|
|
|
1033
|
|
|
1034 /* Microsoft intrinsic. */
|
|
|
1035 extern __inline long long __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1036 _mm_cvttss_si64x (__m128 __A)
|
|
|
1037 {
|
|
|
1038 /* Extract the lower float element. */
|
|
|
1039 float temp = __A[0];
|
|
|
1040 /* truncate to 32-bit integer and return. */
|
|
|
1041 return temp;
|
|
|
1042 }
|
|
|
1043
|
|
|
1044 /* Truncate the two lower SPFP values to 32-bit integers. Return the
|
|
|
1045 integers in packed form. */
|
|
|
1046 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1047 _mm_cvttps_pi32 (__m128 __A)
|
|
|
1048 {
|
|
|
1049 __v4sf temp;
|
|
131
|
1050 __vector unsigned long long result;
|
|
111
|
1051
|
|
|
1052 /* Splat two lower SPFP values to both halves. */
|
|
|
1053 temp = (__v4sf) vec_splat ((__vector long long)__A, 0);
|
|
131
|
1054 result = (__vector unsigned long long) vec_cts (temp, 0);
|
|
111
|
1055
|
|
|
1056 return ((__m64) __builtin_unpack_vector_int128 ((__vector __int128)result, 0));
|
|
|
1057 }
|
|
|
1058
|
|
|
1059 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1060 _mm_cvtt_ps2pi (__m128 __A)
|
|
|
1061 {
|
|
|
1062 return _mm_cvttps_pi32 (__A);
|
|
|
1063 }
|
|
|
1064
|
|
|
1065 /* Convert B to a SPFP value and insert it as element zero in A. */
|
|
|
1066 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1067 _mm_cvtsi32_ss (__m128 __A, int __B)
|
|
|
1068 {
|
|
|
1069 float temp = __B;
|
|
|
1070 __A[0] = temp;
|
|
|
1071
|
|
|
1072 return __A;
|
|
|
1073 }
|
|
|
1074
|
|
|
1075 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1076 _mm_cvt_si2ss (__m128 __A, int __B)
|
|
|
1077 {
|
|
|
1078 return _mm_cvtsi32_ss (__A, __B);
|
|
|
1079 }
|
|
|
1080
|
|
|
1081 /* Convert B to a SPFP value and insert it as element zero in A. */
|
|
|
1082 /* Intel intrinsic. */
|
|
|
1083 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1084 _mm_cvtsi64_ss (__m128 __A, long long __B)
|
|
|
1085 {
|
|
|
1086 float temp = __B;
|
|
|
1087 __A[0] = temp;
|
|
|
1088
|
|
|
1089 return __A;
|
|
|
1090 }
|
|
|
1091
|
|
|
1092 /* Microsoft intrinsic. */
|
|
|
1093 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1094 _mm_cvtsi64x_ss (__m128 __A, long long __B)
|
|
|
1095 {
|
|
|
1096 return _mm_cvtsi64_ss (__A, __B);
|
|
|
1097 }
|
|
|
1098
|
|
|
1099 /* Convert the two 32-bit values in B to SPFP form and insert them
|
|
|
1100 as the two lower elements in A. */
|
|
|
1101 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1102 _mm_cvtpi32_ps (__m128 __A, __m64 __B)
|
|
|
1103 {
|
|
|
1104 __vector signed int vm1;
|
|
|
1105 __vector float vf1;
|
|
|
1106
|
|
|
1107 vm1 = (__vector signed int) __builtin_pack_vector_int128 (__B, __B);
|
|
|
1108 vf1 = (__vector float) vec_ctf (vm1, 0);
|
|
|
1109
|
|
131
|
1110 return ((__m128) (__vector unsigned long long)
|
|
|
1111 { ((__vector unsigned long long)vf1) [0],
|
|
|
1112 ((__vector unsigned long long)__A) [1]});
|
|
111
|
1113 }
|
|
|
1114
|
|
|
1115 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1116 _mm_cvt_pi2ps (__m128 __A, __m64 __B)
|
|
|
1117 {
|
|
|
1118 return _mm_cvtpi32_ps (__A, __B);
|
|
|
1119 }
|
|
|
1120
|
|
|
1121 /* Convert the four signed 16-bit values in A to SPFP form. */
|
|
|
1122 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1123 _mm_cvtpi16_ps (__m64 __A)
|
|
|
1124 {
|
|
|
1125 __vector signed short vs8;
|
|
|
1126 __vector signed int vi4;
|
|
|
1127 __vector float vf1;
|
|
|
1128
|
|
|
1129 vs8 = (__vector signed short) __builtin_pack_vector_int128 (__A, __A);
|
|
|
1130 vi4 = vec_vupklsh (vs8);
|
|
|
1131 vf1 = (__vector float) vec_ctf (vi4, 0);
|
|
|
1132
|
|
|
1133 return (__m128) vf1;
|
|
|
1134 }
|
|
|
1135
|
|
|
1136 /* Convert the four unsigned 16-bit values in A to SPFP form. */
|
|
|
1137 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1138 _mm_cvtpu16_ps (__m64 __A)
|
|
|
1139 {
|
|
|
1140 const __vector unsigned short zero =
|
|
|
1141 { 0, 0, 0, 0, 0, 0, 0, 0 };
|
|
|
1142 __vector unsigned short vs8;
|
|
|
1143 __vector unsigned int vi4;
|
|
|
1144 __vector float vf1;
|
|
|
1145
|
|
|
1146 vs8 = (__vector unsigned short) __builtin_pack_vector_int128 (__A, __A);
|
|
|
1147 vi4 = (__vector unsigned int) vec_vmrglh (vs8, zero);
|
|
|
1148 vf1 = (__vector float) vec_ctf (vi4, 0);
|
|
|
1149
|
|
|
1150 return (__m128) vf1;
|
|
|
1151 }
|
|
|
1152
|
|
|
1153 /* Convert the low four signed 8-bit values in A to SPFP form. */
|
|
|
1154 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1155 _mm_cvtpi8_ps (__m64 __A)
|
|
|
1156 {
|
|
|
1157 __vector signed char vc16;
|
|
|
1158 __vector signed short vs8;
|
|
|
1159 __vector signed int vi4;
|
|
|
1160 __vector float vf1;
|
|
|
1161
|
|
|
1162 vc16 = (__vector signed char) __builtin_pack_vector_int128 (__A, __A);
|
|
|
1163 vs8 = vec_vupkhsb (vc16);
|
|
|
1164 vi4 = vec_vupkhsh (vs8);
|
|
|
1165 vf1 = (__vector float) vec_ctf (vi4, 0);
|
|
|
1166
|
|
|
1167 return (__m128) vf1;
|
|
|
1168 }
|
|
|
1169
|
|
|
1170 /* Convert the low four unsigned 8-bit values in A to SPFP form. */
|
|
|
1171 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1172
|
|
|
1173 _mm_cvtpu8_ps (__m64 __A)
|
|
|
1174 {
|
|
|
1175 const __vector unsigned char zero =
|
|
|
1176 { 0, 0, 0, 0, 0, 0, 0, 0 };
|
|
|
1177 __vector unsigned char vc16;
|
|
|
1178 __vector unsigned short vs8;
|
|
|
1179 __vector unsigned int vi4;
|
|
|
1180 __vector float vf1;
|
|
|
1181
|
|
|
1182 vc16 = (__vector unsigned char) __builtin_pack_vector_int128 (__A, __A);
|
|
|
1183 vs8 = (__vector unsigned short) vec_vmrglb (vc16, zero);
|
|
|
1184 vi4 = (__vector unsigned int) vec_vmrghh (vs8,
|
|
|
1185 (__vector unsigned short) zero);
|
|
|
1186 vf1 = (__vector float) vec_ctf (vi4, 0);
|
|
|
1187
|
|
|
1188 return (__m128) vf1;
|
|
|
1189 }
|
|
|
1190
|
|
|
1191 /* Convert the four signed 32-bit values in A and B to SPFP form. */
|
|
|
1192 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1193 _mm_cvtpi32x2_ps(__m64 __A, __m64 __B)
|
|
|
1194 {
|
|
|
1195 __vector signed int vi4;
|
|
|
1196 __vector float vf4;
|
|
|
1197
|
|
|
1198 vi4 = (__vector signed int) __builtin_pack_vector_int128 (__B, __A);
|
|
|
1199 vf4 = (__vector float) vec_ctf (vi4, 0);
|
|
|
1200 return (__m128) vf4;
|
|
|
1201 }
|
|
|
1202
|
|
|
1203 /* Convert the four SPFP values in A to four signed 16-bit integers. */
|
|
|
1204 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1205 _mm_cvtps_pi16(__m128 __A)
|
|
|
1206 {
|
|
|
1207 __v4sf rounded;
|
|
|
1208 __vector signed int temp;
|
|
131
|
1209 __vector unsigned long long result;
|
|
111
|
1210
|
|
|
1211 rounded = vec_rint(__A);
|
|
|
1212 temp = vec_cts (rounded, 0);
|
|
131
|
1213 result = (__vector unsigned long long) vec_pack (temp, temp);
|
|
111
|
1214
|
|
|
1215 return ((__m64) __builtin_unpack_vector_int128 ((__vector __int128)result, 0));
|
|
|
1216 }
|
|
|
1217
|
|
|
1218 /* Convert the four SPFP values in A to four signed 8-bit integers. */
|
|
|
1219 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1220 _mm_cvtps_pi8(__m128 __A)
|
|
|
1221 {
|
|
|
1222 __v4sf rounded;
|
|
|
1223 __vector signed int tmp_i;
|
|
|
1224 static const __vector signed int zero = {0, 0, 0, 0};
|
|
|
1225 __vector signed short tmp_s;
|
|
|
1226 __vector signed char res_v;
|
|
|
1227 __m64 result;
|
|
|
1228
|
|
|
1229 rounded = vec_rint(__A);
|
|
|
1230 tmp_i = vec_cts (rounded, 0);
|
|
|
1231 tmp_s = vec_pack (tmp_i, zero);
|
|
|
1232 res_v = vec_pack (tmp_s, tmp_s);
|
|
|
1233 result = (__m64) __builtin_unpack_vector_int128 ((__vector __int128)res_v, 0);
|
|
|
1234
|
|
|
1235 return (result);
|
|
|
1236 }
|
|
|
1237
|
|
|
1238 /* Selects four specific SPFP values from A and B based on MASK. */
|
|
|
1239 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1240
|
|
|
1241 _mm_shuffle_ps (__m128 __A, __m128 __B, int const __mask)
|
|
|
1242 {
|
|
|
1243 unsigned long element_selector_10 = __mask & 0x03;
|
|
|
1244 unsigned long element_selector_32 = (__mask >> 2) & 0x03;
|
|
|
1245 unsigned long element_selector_54 = (__mask >> 4) & 0x03;
|
|
|
1246 unsigned long element_selector_76 = (__mask >> 6) & 0x03;
|
|
|
1247 static const unsigned int permute_selectors[4] =
|
|
|
1248 {
|
|
|
1249 #ifdef __LITTLE_ENDIAN__
|
|
|
1250 0x03020100, 0x07060504, 0x0B0A0908, 0x0F0E0D0C
|
|
|
1251 #elif __BIG_ENDIAN__
|
|
|
1252 0x0C0D0E0F, 0x08090A0B, 0x04050607, 0x00010203
|
|
|
1253 #endif
|
|
|
1254 };
|
|
|
1255 __vector unsigned int t;
|
|
|
1256
|
|
|
1257 #ifdef __LITTLE_ENDIAN__
|
|
|
1258 t[0] = permute_selectors[element_selector_10];
|
|
|
1259 t[1] = permute_selectors[element_selector_32];
|
|
|
1260 t[2] = permute_selectors[element_selector_54] + 0x10101010;
|
|
|
1261 t[3] = permute_selectors[element_selector_76] + 0x10101010;
|
|
|
1262 #elif __BIG_ENDIAN__
|
|
|
1263 t[3] = permute_selectors[element_selector_10] + 0x10101010;
|
|
|
1264 t[2] = permute_selectors[element_selector_32] + 0x10101010;
|
|
|
1265 t[1] = permute_selectors[element_selector_54];
|
|
|
1266 t[0] = permute_selectors[element_selector_76];
|
|
|
1267 #endif
|
|
|
1268 return vec_perm ((__v4sf) __A, (__v4sf)__B, (__vector unsigned char)t);
|
|
|
1269 }
|
|
|
1270
|
|
|
1271 /* Selects and interleaves the upper two SPFP values from A and B. */
|
|
|
1272 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1273 _mm_unpackhi_ps (__m128 __A, __m128 __B)
|
|
|
1274 {
|
|
|
1275 return (__m128) vec_vmrglw ((__v4sf) __A, (__v4sf)__B);
|
|
|
1276 }
|
|
|
1277
|
|
|
1278 /* Selects and interleaves the lower two SPFP values from A and B. */
|
|
|
1279 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1280 _mm_unpacklo_ps (__m128 __A, __m128 __B)
|
|
|
1281 {
|
|
|
1282 return (__m128) vec_vmrghw ((__v4sf) __A, (__v4sf)__B);
|
|
|
1283 }
|
|
|
1284
|
|
|
1285 /* Sets the upper two SPFP values with 64-bits of data loaded from P;
|
|
|
1286 the lower two values are passed through from A. */
|
|
|
1287 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1288 _mm_loadh_pi (__m128 __A, __m64 const *__P)
|
|
|
1289 {
|
|
131
|
1290 __vector unsigned long long __a = (__vector unsigned long long)__A;
|
|
|
1291 __vector unsigned long long __p = vec_splats(*__P);
|
|
111
|
1292 __a [1] = __p [1];
|
|
|
1293
|
|
|
1294 return (__m128)__a;
|
|
|
1295 }
|
|
|
1296
|
|
|
1297 /* Stores the upper two SPFP values of A into P. */
|
|
|
1298 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1299 _mm_storeh_pi (__m64 *__P, __m128 __A)
|
|
|
1300 {
|
|
131
|
1301 __vector unsigned long long __a = (__vector unsigned long long) __A;
|
|
111
|
1302
|
|
|
1303 *__P = __a[1];
|
|
|
1304 }
|
|
|
1305
|
|
|
1306 /* Moves the upper two values of B into the lower two values of A. */
|
|
|
1307 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1308 _mm_movehl_ps (__m128 __A, __m128 __B)
|
|
|
1309 {
|
|
131
|
1310 return (__m128) vec_mergel ((__vector unsigned long long)__B,
|
|
|
1311 (__vector unsigned long long)__A);
|
|
111
|
1312 }
|
|
|
1313
|
|
|
1314 /* Moves the lower two values of B into the upper two values of A. */
|
|
|
1315 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1316 _mm_movelh_ps (__m128 __A, __m128 __B)
|
|
|
1317 {
|
|
131
|
1318 return (__m128) vec_mergeh ((__vector unsigned long long)__A,
|
|
|
1319 (__vector unsigned long long)__B);
|
|
111
|
1320 }
|
|
|
1321
|
|
|
1322 /* Sets the lower two SPFP values with 64-bits of data loaded from P;
|
|
|
1323 the upper two values are passed through from A. */
|
|
|
1324 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1325 _mm_loadl_pi (__m128 __A, __m64 const *__P)
|
|
|
1326 {
|
|
131
|
1327 __vector unsigned long long __a = (__vector unsigned long long)__A;
|
|
|
1328 __vector unsigned long long __p = vec_splats(*__P);
|
|
111
|
1329 __a [0] = __p [0];
|
|
|
1330
|
|
|
1331 return (__m128)__a;
|
|
|
1332 }
|
|
|
1333
|
|
|
1334 /* Stores the lower two SPFP values of A into P. */
|
|
|
1335 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1336 _mm_storel_pi (__m64 *__P, __m128 __A)
|
|
|
1337 {
|
|
131
|
1338 __vector unsigned long long __a = (__vector unsigned long long) __A;
|
|
111
|
1339
|
|
|
1340 *__P = __a[0];
|
|
|
1341 }
|
|
|
1342
|
|
|
1343 #ifdef _ARCH_PWR8
|
|
|
1344 /* Intrinsic functions that require PowerISA 2.07 minimum. */
|
|
|
1345
|
|
|
1346 /* Creates a 4-bit mask from the most significant bits of the SPFP values. */
|
|
|
1347 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1348 _mm_movemask_ps (__m128 __A)
|
|
|
1349 {
|
|
131
|
1350 __vector unsigned long long result;
|
|
111
|
1351 static const __vector unsigned int perm_mask =
|
|
|
1352 {
|
|
|
1353 #ifdef __LITTLE_ENDIAN__
|
|
|
1354 0x00204060, 0x80808080, 0x80808080, 0x80808080
|
|
|
1355 #elif __BIG_ENDIAN__
|
|
|
1356 0x80808080, 0x80808080, 0x80808080, 0x00204060
|
|
|
1357 #endif
|
|
|
1358 };
|
|
|
1359
|
|
131
|
1360 result = ((__vector unsigned long long)
|
|
|
1361 vec_vbpermq ((__vector unsigned char) __A,
|
|
|
1362 (__vector unsigned char) perm_mask));
|
|
111
|
1363
|
|
|
1364 #ifdef __LITTLE_ENDIAN__
|
|
|
1365 return result[1];
|
|
|
1366 #elif __BIG_ENDIAN__
|
|
|
1367 return result[0];
|
|
|
1368 #endif
|
|
|
1369 }
|
|
|
1370 #endif /* _ARCH_PWR8 */
|
|
|
1371
|
|
|
1372 /* Create a vector with all four elements equal to *P. */
|
|
|
1373 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1374 _mm_load1_ps (float const *__P)
|
|
|
1375 {
|
|
|
1376 return _mm_set1_ps (*__P);
|
|
|
1377 }
|
|
|
1378
|
|
|
1379 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1380 _mm_load_ps1 (float const *__P)
|
|
|
1381 {
|
|
|
1382 return _mm_load1_ps (__P);
|
|
|
1383 }
|
|
|
1384
|
|
|
1385 /* Extracts one of the four words of A. The selector N must be immediate. */
|
|
|
1386 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1387 _mm_extract_pi16 (__m64 const __A, int const __N)
|
|
|
1388 {
|
|
|
1389 const int shiftr = (__N & 3) * 16;
|
|
|
1390
|
|
|
1391 return ((__A >> shiftr) & 0xffff);
|
|
|
1392 }
|
|
|
1393
|
|
|
1394 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1395 _m_pextrw (__m64 const __A, int const __N)
|
|
|
1396 {
|
|
|
1397 return _mm_extract_pi16 (__A, __N);
|
|
|
1398 }
|
|
|
1399
|
|
|
1400 /* Inserts word D into one of four words of A. The selector N must be
|
|
|
1401 immediate. */
|
|
|
1402 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1403 _mm_insert_pi16 (__m64 const __A, int const __D, int const __N)
|
|
|
1404 {
|
|
|
1405 const int shiftl = (__N & 3) * 16;
|
|
|
1406 const __m64 shiftD = (const __m64) __D << shiftl;
|
|
|
1407 const __m64 mask = 0xffffUL << shiftl;
|
|
|
1408 __m64 result = (__A & (~mask)) | (shiftD & mask);
|
|
|
1409
|
|
|
1410 return (result);
|
|
|
1411 }
|
|
|
1412
|
|
|
1413 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1414 _m_pinsrw (__m64 const __A, int const __D, int const __N)
|
|
|
1415 {
|
|
|
1416 return _mm_insert_pi16 (__A, __D, __N);
|
|
|
1417 }
|
|
|
1418
|
|
|
1419 /* Compute the element-wise maximum of signed 16-bit values. */
|
|
|
1420 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1421
|
|
|
1422 _mm_max_pi16 (__m64 __A, __m64 __B)
|
|
|
1423 {
|
|
|
1424 #if _ARCH_PWR8
|
|
|
1425 __vector signed short a, b, r;
|
|
131
|
1426 __vector __bool short c;
|
|
111
|
1427
|
|
|
1428 a = (__vector signed short)vec_splats (__A);
|
|
|
1429 b = (__vector signed short)vec_splats (__B);
|
|
131
|
1430 c = (__vector __bool short)vec_cmpgt (a, b);
|
|
111
|
1431 r = vec_sel (b, a, c);
|
|
131
|
1432 return (__builtin_unpack_vector_int128 ((__vector __int128)r, 0));
|
|
111
|
1433 #else
|
|
|
1434 __m64_union m1, m2, res;
|
|
|
1435
|
|
|
1436 m1.as_m64 = __A;
|
|
|
1437 m2.as_m64 = __B;
|
|
|
1438
|
|
|
1439 res.as_short[0] =
|
|
|
1440 (m1.as_short[0] > m2.as_short[0]) ? m1.as_short[0] : m2.as_short[0];
|
|
|
1441 res.as_short[1] =
|
|
|
1442 (m1.as_short[1] > m2.as_short[1]) ? m1.as_short[1] : m2.as_short[1];
|
|
|
1443 res.as_short[2] =
|
|
|
1444 (m1.as_short[2] > m2.as_short[2]) ? m1.as_short[2] : m2.as_short[2];
|
|
|
1445 res.as_short[3] =
|
|
|
1446 (m1.as_short[3] > m2.as_short[3]) ? m1.as_short[3] : m2.as_short[3];
|
|
|
1447
|
|
|
1448 return (__m64) res.as_m64;
|
|
|
1449 #endif
|
|
|
1450 }
|
|
|
1451
|
|
|
1452 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1453 _m_pmaxsw (__m64 __A, __m64 __B)
|
|
|
1454 {
|
|
|
1455 return _mm_max_pi16 (__A, __B);
|
|
|
1456 }
|
|
|
1457
|
|
|
1458 /* Compute the element-wise maximum of unsigned 8-bit values. */
|
|
|
1459 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1460 _mm_max_pu8 (__m64 __A, __m64 __B)
|
|
|
1461 {
|
|
|
1462 #if _ARCH_PWR8
|
|
|
1463 __vector unsigned char a, b, r;
|
|
131
|
1464 __vector __bool char c;
|
|
111
|
1465
|
|
|
1466 a = (__vector unsigned char)vec_splats (__A);
|
|
|
1467 b = (__vector unsigned char)vec_splats (__B);
|
|
131
|
1468 c = (__vector __bool char)vec_cmpgt (a, b);
|
|
111
|
1469 r = vec_sel (b, a, c);
|
|
131
|
1470 return (__builtin_unpack_vector_int128 ((__vector __int128)r, 0));
|
|
111
|
1471 #else
|
|
|
1472 __m64_union m1, m2, res;
|
|
|
1473 long i;
|
|
|
1474
|
|
|
1475 m1.as_m64 = __A;
|
|
|
1476 m2.as_m64 = __B;
|
|
|
1477
|
|
|
1478
|
|
|
1479 for (i = 0; i < 8; i++)
|
|
|
1480 res.as_char[i] =
|
|
|
1481 ((unsigned char) m1.as_char[i] > (unsigned char) m2.as_char[i]) ?
|
|
|
1482 m1.as_char[i] : m2.as_char[i];
|
|
|
1483
|
|
|
1484 return (__m64) res.as_m64;
|
|
|
1485 #endif
|
|
|
1486 }
|
|
|
1487
|
|
|
1488 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1489 _m_pmaxub (__m64 __A, __m64 __B)
|
|
|
1490 {
|
|
|
1491 return _mm_max_pu8 (__A, __B);
|
|
|
1492 }
|
|
|
1493
|
|
|
1494 /* Compute the element-wise minimum of signed 16-bit values. */
|
|
|
1495 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1496 _mm_min_pi16 (__m64 __A, __m64 __B)
|
|
|
1497 {
|
|
|
1498 #if _ARCH_PWR8
|
|
|
1499 __vector signed short a, b, r;
|
|
131
|
1500 __vector __bool short c;
|
|
111
|
1501
|
|
|
1502 a = (__vector signed short)vec_splats (__A);
|
|
|
1503 b = (__vector signed short)vec_splats (__B);
|
|
131
|
1504 c = (__vector __bool short)vec_cmplt (a, b);
|
|
111
|
1505 r = vec_sel (b, a, c);
|
|
131
|
1506 return (__builtin_unpack_vector_int128 ((__vector __int128)r, 0));
|
|
111
|
1507 #else
|
|
|
1508 __m64_union m1, m2, res;
|
|
|
1509
|
|
|
1510 m1.as_m64 = __A;
|
|
|
1511 m2.as_m64 = __B;
|
|
|
1512
|
|
|
1513 res.as_short[0] =
|
|
|
1514 (m1.as_short[0] < m2.as_short[0]) ? m1.as_short[0] : m2.as_short[0];
|
|
|
1515 res.as_short[1] =
|
|
|
1516 (m1.as_short[1] < m2.as_short[1]) ? m1.as_short[1] : m2.as_short[1];
|
|
|
1517 res.as_short[2] =
|
|
|
1518 (m1.as_short[2] < m2.as_short[2]) ? m1.as_short[2] : m2.as_short[2];
|
|
|
1519 res.as_short[3] =
|
|
|
1520 (m1.as_short[3] < m2.as_short[3]) ? m1.as_short[3] : m2.as_short[3];
|
|
|
1521
|
|
|
1522 return (__m64) res.as_m64;
|
|
|
1523 #endif
|
|
|
1524 }
|
|
|
1525
|
|
|
1526 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1527 _m_pminsw (__m64 __A, __m64 __B)
|
|
|
1528 {
|
|
|
1529 return _mm_min_pi16 (__A, __B);
|
|
|
1530 }
|
|
|
1531
|
|
|
1532 /* Compute the element-wise minimum of unsigned 8-bit values. */
|
|
|
1533 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1534 _mm_min_pu8 (__m64 __A, __m64 __B)
|
|
|
1535 {
|
|
|
1536 #if _ARCH_PWR8
|
|
|
1537 __vector unsigned char a, b, r;
|
|
131
|
1538 __vector __bool char c;
|
|
111
|
1539
|
|
|
1540 a = (__vector unsigned char)vec_splats (__A);
|
|
|
1541 b = (__vector unsigned char)vec_splats (__B);
|
|
131
|
1542 c = (__vector __bool char)vec_cmplt (a, b);
|
|
111
|
1543 r = vec_sel (b, a, c);
|
|
131
|
1544 return (__builtin_unpack_vector_int128 ((__vector __int128)r, 0));
|
|
111
|
1545 #else
|
|
|
1546 __m64_union m1, m2, res;
|
|
|
1547 long i;
|
|
|
1548
|
|
|
1549 m1.as_m64 = __A;
|
|
|
1550 m2.as_m64 = __B;
|
|
|
1551
|
|
|
1552
|
|
|
1553 for (i = 0; i < 8; i++)
|
|
|
1554 res.as_char[i] =
|
|
|
1555 ((unsigned char) m1.as_char[i] < (unsigned char) m2.as_char[i]) ?
|
|
|
1556 m1.as_char[i] : m2.as_char[i];
|
|
|
1557
|
|
|
1558 return (__m64) res.as_m64;
|
|
|
1559 #endif
|
|
|
1560 }
|
|
|
1561
|
|
|
1562 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1563 _m_pminub (__m64 __A, __m64 __B)
|
|
|
1564 {
|
|
|
1565 return _mm_min_pu8 (__A, __B);
|
|
|
1566 }
|
|
|
1567
|
|
|
1568 /* Create an 8-bit mask of the signs of 8-bit values. */
|
|
|
1569 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1570 _mm_movemask_pi8 (__m64 __A)
|
|
|
1571 {
|
|
|
1572 unsigned long p = 0x0008101820283038UL; // permute control for sign bits
|
|
|
1573
|
|
|
1574 return __builtin_bpermd (p, __A);
|
|
|
1575 }
|
|
|
1576
|
|
|
1577 extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1578 _m_pmovmskb (__m64 __A)
|
|
|
1579 {
|
|
|
1580 return _mm_movemask_pi8 (__A);
|
|
|
1581 }
|
|
|
1582
|
|
|
1583 /* Multiply four unsigned 16-bit values in A by four unsigned 16-bit values
|
|
|
1584 in B and produce the high 16 bits of the 32-bit results. */
|
|
|
1585 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1586 _mm_mulhi_pu16 (__m64 __A, __m64 __B)
|
|
|
1587 {
|
|
|
1588 __vector unsigned short a, b;
|
|
|
1589 __vector unsigned short c;
|
|
|
1590 __vector unsigned int w0, w1;
|
|
|
1591 __vector unsigned char xform1 = {
|
|
|
1592 0x02, 0x03, 0x12, 0x13, 0x06, 0x07, 0x16, 0x17,
|
|
|
1593 0x0A, 0x0B, 0x1A, 0x1B, 0x0E, 0x0F, 0x1E, 0x1F
|
|
|
1594 };
|
|
|
1595
|
|
|
1596 a = (__vector unsigned short)vec_splats (__A);
|
|
|
1597 b = (__vector unsigned short)vec_splats (__B);
|
|
|
1598
|
|
|
1599 w0 = vec_vmuleuh (a, b);
|
|
|
1600 w1 = vec_vmulouh (a, b);
|
|
|
1601 c = (__vector unsigned short)vec_perm (w0, w1, xform1);
|
|
|
1602
|
|
|
1603 return (__builtin_unpack_vector_int128 ((__vector __int128)c, 0));
|
|
|
1604 }
|
|
|
1605
|
|
|
1606 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1607 _m_pmulhuw (__m64 __A, __m64 __B)
|
|
|
1608 {
|
|
|
1609 return _mm_mulhi_pu16 (__A, __B);
|
|
|
1610 }
|
|
|
1611
|
|
|
1612 /* Return a combination of the four 16-bit values in A. The selector
|
|
|
1613 must be an immediate. */
|
|
|
1614 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1615 _mm_shuffle_pi16 (__m64 __A, int const __N)
|
|
|
1616 {
|
|
|
1617 unsigned long element_selector_10 = __N & 0x03;
|
|
|
1618 unsigned long element_selector_32 = (__N >> 2) & 0x03;
|
|
|
1619 unsigned long element_selector_54 = (__N >> 4) & 0x03;
|
|
|
1620 unsigned long element_selector_76 = (__N >> 6) & 0x03;
|
|
|
1621 static const unsigned short permute_selectors[4] =
|
|
|
1622 {
|
|
|
1623 #ifdef __LITTLE_ENDIAN__
|
|
|
1624 0x0908, 0x0B0A, 0x0D0C, 0x0F0E
|
|
|
1625 #elif __BIG_ENDIAN__
|
|
|
1626 0x0607, 0x0405, 0x0203, 0x0001
|
|
|
1627 #endif
|
|
|
1628 };
|
|
|
1629 __m64_union t;
|
|
131
|
1630 __vector unsigned long long a, p, r;
|
|
111
|
1631
|
|
|
1632 #ifdef __LITTLE_ENDIAN__
|
|
|
1633 t.as_short[0] = permute_selectors[element_selector_10];
|
|
|
1634 t.as_short[1] = permute_selectors[element_selector_32];
|
|
|
1635 t.as_short[2] = permute_selectors[element_selector_54];
|
|
|
1636 t.as_short[3] = permute_selectors[element_selector_76];
|
|
|
1637 #elif __BIG_ENDIAN__
|
|
|
1638 t.as_short[3] = permute_selectors[element_selector_10];
|
|
|
1639 t.as_short[2] = permute_selectors[element_selector_32];
|
|
|
1640 t.as_short[1] = permute_selectors[element_selector_54];
|
|
|
1641 t.as_short[0] = permute_selectors[element_selector_76];
|
|
|
1642 #endif
|
|
|
1643 p = vec_splats (t.as_m64);
|
|
|
1644 a = vec_splats (__A);
|
|
|
1645 r = vec_perm (a, a, (__vector unsigned char)p);
|
|
|
1646 return (__builtin_unpack_vector_int128 ((__vector __int128)r, 0));
|
|
|
1647 }
|
|
|
1648
|
|
|
1649 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1650 _m_pshufw (__m64 __A, int const __N)
|
|
|
1651 {
|
|
|
1652 return _mm_shuffle_pi16 (__A, __N);
|
|
|
1653 }
|
|
|
1654
|
|
|
1655 /* Conditionally store byte elements of A into P. The high bit of each
|
|
|
1656 byte in the selector N determines whether the corresponding byte from
|
|
|
1657 A is stored. */
|
|
|
1658 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1659 _mm_maskmove_si64 (__m64 __A, __m64 __N, char *__P)
|
|
|
1660 {
|
|
|
1661 __m64 hibit = 0x8080808080808080UL;
|
|
|
1662 __m64 mask, tmp;
|
|
|
1663 __m64 *p = (__m64*)__P;
|
|
|
1664
|
|
|
1665 tmp = *p;
|
|
|
1666 mask = _mm_cmpeq_pi8 ((__N & hibit), hibit);
|
|
|
1667 tmp = (tmp & (~mask)) | (__A & mask);
|
|
|
1668 *p = tmp;
|
|
|
1669 }
|
|
|
1670
|
|
|
1671 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1672 _m_maskmovq (__m64 __A, __m64 __N, char *__P)
|
|
|
1673 {
|
|
|
1674 _mm_maskmove_si64 (__A, __N, __P);
|
|
|
1675 }
|
|
|
1676
|
|
|
1677 /* Compute the rounded averages of the unsigned 8-bit values in A and B. */
|
|
|
1678 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1679 _mm_avg_pu8 (__m64 __A, __m64 __B)
|
|
|
1680 {
|
|
|
1681 __vector unsigned char a, b, c;
|
|
|
1682
|
|
|
1683 a = (__vector unsigned char)vec_splats (__A);
|
|
|
1684 b = (__vector unsigned char)vec_splats (__B);
|
|
|
1685 c = vec_avg (a, b);
|
|
|
1686 return (__builtin_unpack_vector_int128 ((__vector __int128)c, 0));
|
|
|
1687 }
|
|
|
1688
|
|
|
1689 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1690 _m_pavgb (__m64 __A, __m64 __B)
|
|
|
1691 {
|
|
|
1692 return _mm_avg_pu8 (__A, __B);
|
|
|
1693 }
|
|
|
1694
|
|
|
1695 /* Compute the rounded averages of the unsigned 16-bit values in A and B. */
|
|
|
1696 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1697 _mm_avg_pu16 (__m64 __A, __m64 __B)
|
|
|
1698 {
|
|
|
1699 __vector unsigned short a, b, c;
|
|
|
1700
|
|
|
1701 a = (__vector unsigned short)vec_splats (__A);
|
|
|
1702 b = (__vector unsigned short)vec_splats (__B);
|
|
|
1703 c = vec_avg (a, b);
|
|
|
1704 return (__builtin_unpack_vector_int128 ((__vector __int128)c, 0));
|
|
|
1705 }
|
|
|
1706
|
|
|
1707 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1708 _m_pavgw (__m64 __A, __m64 __B)
|
|
|
1709 {
|
|
|
1710 return _mm_avg_pu16 (__A, __B);
|
|
|
1711 }
|
|
|
1712
|
|
|
1713 /* Compute the sum of the absolute differences of the unsigned 8-bit
|
|
|
1714 values in A and B. Return the value in the lower 16-bit word; the
|
|
|
1715 upper words are cleared. */
|
|
|
1716 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1717 _mm_sad_pu8 (__m64 __A, __m64 __B)
|
|
|
1718 {
|
|
|
1719 __vector unsigned char a, b;
|
|
|
1720 __vector unsigned char vmin, vmax, vabsdiff;
|
|
|
1721 __vector signed int vsum;
|
|
|
1722 const __vector unsigned int zero =
|
|
|
1723 { 0, 0, 0, 0 };
|
|
|
1724 unsigned short result;
|
|
|
1725
|
|
|
1726 a = (__vector unsigned char) __builtin_pack_vector_int128 (0UL, __A);
|
|
|
1727 b = (__vector unsigned char) __builtin_pack_vector_int128 (0UL, __B);
|
|
|
1728 vmin = vec_min (a, b);
|
|
|
1729 vmax = vec_max (a, b);
|
|
|
1730 vabsdiff = vec_sub (vmax, vmin);
|
|
|
1731 /* Sum four groups of bytes into integers. */
|
|
|
1732 vsum = (__vector signed int) vec_sum4s (vabsdiff, zero);
|
|
|
1733 /* Sum across four integers with integer result. */
|
|
|
1734 vsum = vec_sums (vsum, (__vector signed int) zero);
|
|
|
1735 /* The sum is in the right most 32-bits of the vector result.
|
|
|
1736 Transfer to a GPR and truncate to 16 bits. */
|
|
|
1737 result = vsum[3];
|
|
|
1738 return (result);
|
|
|
1739 }
|
|
|
1740
|
|
|
1741 extern __inline __m64 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1742 _m_psadbw (__m64 __A, __m64 __B)
|
|
|
1743 {
|
|
|
1744 return _mm_sad_pu8 (__A, __B);
|
|
|
1745 }
|
|
|
1746
|
|
|
1747 /* Stores the data in A to the address P without polluting the caches. */
|
|
|
1748 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1749 _mm_stream_pi (__m64 *__P, __m64 __A)
|
|
|
1750 {
|
|
|
1751 /* Use the data cache block touch for store transient. */
|
|
|
1752 __asm__ (
|
|
|
1753 " dcbtstt 0,%0"
|
|
|
1754 :
|
|
|
1755 : "b" (__P)
|
|
|
1756 : "memory"
|
|
|
1757 );
|
|
|
1758 *__P = __A;
|
|
|
1759 }
|
|
|
1760
|
|
|
1761 /* Likewise. The address must be 16-byte aligned. */
|
|
|
1762 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1763 _mm_stream_ps (float *__P, __m128 __A)
|
|
|
1764 {
|
|
|
1765 /* Use the data cache block touch for store transient. */
|
|
|
1766 __asm__ (
|
|
|
1767 " dcbtstt 0,%0"
|
|
|
1768 :
|
|
|
1769 : "b" (__P)
|
|
|
1770 : "memory"
|
|
|
1771 );
|
|
|
1772 _mm_store_ps (__P, __A);
|
|
|
1773 }
|
|
|
1774
|
|
|
1775 /* Guarantees that every preceding store is globally visible before
|
|
|
1776 any subsequent store. */
|
|
|
1777 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1778 _mm_sfence (void)
|
|
|
1779 {
|
|
|
1780 /* Generate a light weight sync. */
|
|
|
1781 __atomic_thread_fence (__ATOMIC_RELEASE);
|
|
|
1782 }
|
|
|
1783
|
|
|
1784 /* The execution of the next instruction is delayed by an implementation
|
|
|
1785 specific amount of time. The instruction does not modify the
|
|
|
1786 architectural state. This is after the pop_options pragma because
|
|
|
1787 it does not require SSE support in the processor--the encoding is a
|
|
|
1788 nop on processors that do not support it. */
|
|
|
1789 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
|
|
1790 _mm_pause (void)
|
|
|
1791 {
|
|
|
1792 /* There is no exact match with this construct, but the following is
|
|
|
1793 close to the desired effect. */
|
|
|
1794 #if _ARCH_PWR8
|
|
|
1795 /* On power8 and later processors we can depend on Program Priority
|
|
|
1796 (PRI) and associated "very low" PPI setting. Since we don't know
|
|
|
1797 what PPI this thread is running at we: 1) save the current PRI
|
|
|
1798 from the PPR SPR into a local GRP, 2) set the PRI to "very low*
|
|
|
1799 via the special or 31,31,31 encoding. 3) issue an "isync" to
|
|
|
1800 insure the PRI change takes effect before we execute any more
|
|
|
1801 instructions.
|
|
|
1802 Now we can execute a lwsync (release barrier) while we execute
|
|
|
1803 this thread at "very low" PRI. Finally we restore the original
|
|
|
1804 PRI and continue execution. */
|
|
|
1805 unsigned long __PPR;
|
|
|
1806
|
|
|
1807 __asm__ volatile (
|
|
|
1808 " mfppr %0;"
|
|
|
1809 " or 31,31,31;"
|
|
|
1810 " isync;"
|
|
|
1811 " lwsync;"
|
|
|
1812 " isync;"
|
|
|
1813 " mtppr %0;"
|
|
|
1814 : "=r" (__PPR)
|
|
|
1815 :
|
|
|
1816 : "memory"
|
|
|
1817 );
|
|
|
1818 #else
|
|
|
1819 /* For older processor where we may not even have Program Priority
|
|
|
1820 controls we can only depend on Heavy Weight Sync. */
|
|
|
1821 __atomic_thread_fence (__ATOMIC_SEQ_CST);
|
|
|
1822 #endif
|
|
|
1823 }
|
|
|
1824
|
|
|
1825 /* Transpose the 4x4 matrix composed of row[0-3]. */
|
|
|
1826 #define _MM_TRANSPOSE4_PS(row0, row1, row2, row3) \
|
|
|
1827 do { \
|
|
|
1828 __v4sf __r0 = (row0), __r1 = (row1), __r2 = (row2), __r3 = (row3); \
|
|
|
1829 __v4sf __t0 = vec_vmrghw (__r0, __r1); \
|
|
|
1830 __v4sf __t1 = vec_vmrghw (__r2, __r3); \
|
|
|
1831 __v4sf __t2 = vec_vmrglw (__r0, __r1); \
|
|
|
1832 __v4sf __t3 = vec_vmrglw (__r2, __r3); \
|
|
|
1833 (row0) = (__v4sf)vec_mergeh ((__vector long long)__t0, \
|
|
|
1834 (__vector long long)__t1); \
|
|
|
1835 (row1) = (__v4sf)vec_mergel ((__vector long long)__t0, \
|
|
|
1836 (__vector long long)__t1); \
|
|
|
1837 (row2) = (__v4sf)vec_mergeh ((__vector long long)__t2, \
|
|
|
1838 (__vector long long)__t3); \
|
|
|
1839 (row3) = (__v4sf)vec_mergel ((__vector long long)__t2, \
|
|
|
1840 (__vector long long)__t3); \
|
|
|
1841 } while (0)
|
|
|
1842
|
|
|
1843 /* For backward source compatibility. */
|
|
|
1844 //# include <emmintrin.h>
|
|
|
1845
|
|
|
1846 #endif /* _XMMINTRIN_H_INCLUDED */
|
