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annotate gcc/config/rx/rx.opt @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
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1 ; Command line options for the Renesas RX port of GCC.
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84e7813d76e9 gcc-8.2
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2 ; Copyright (C) 2008-2018 Free Software Foundation, Inc.
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3 ; Contributed by Red Hat.
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4 ;
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5 ; This file is part of GCC.
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6 ;
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7 ; GCC is free software; you can redistribute it and/or modify it under
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8 ; the terms of the GNU General Public License as published by the Free
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9 ; Software Foundation; either version 3, or (at your option) any later
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10 ; version.
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11 ;
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12 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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13 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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14 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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15 ; for more details.
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16 ;
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17 ; You should have received a copy of the GNU General Public License
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18 ; along with GCC; see the file COPYING3. If not see
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19 ; <http://www.gnu.org/licenses/>.
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20 ;---------------------------------------------------
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21
111
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22 HeaderInclude
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23 config/rx/rx-opts.h
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24
63
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25 ; The default is -fpu -m32bit-doubles.
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26
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27 m64bit-doubles
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28 Target RejectNegative Mask(64BIT_DOUBLES) Report
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29 Store doubles in 64 bits.
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30
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31 m32bit-doubles
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32 Target RejectNegative InverseMask(64BIT_DOUBLES) Report
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33 Stores doubles in 32 bits. This is the default.
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34
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35 nofpu
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36 Target RejectNegative Alias(mnofpu)
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37 Disable the use of RX FPU instructions.
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38
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39 mnofpu
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40 Target RejectNegative Mask(NO_USE_FPU) Report Undocumented
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41
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42 fpu
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43 Target RejectNegative InverseMask(NO_USE_FPU) Report
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44 Enable the use of RX FPU instructions. This is the default.
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45
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46 ;---------------------------------------------------
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47
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48 mcpu=
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49 Target RejectNegative Joined Var(rx_cpu_type) Report ToLower Enum(rx_cpu_types) Init(RX600)
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50 Specify the target RX cpu type.
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51
111
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52 Enum
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53 Name(rx_cpu_types) Type(enum rx_cpu_types)
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54
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55 EnumValue
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56 Enum(rx_cpu_types) String(rx610) Value(RX610)
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57
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58 EnumValue
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59 Enum(rx_cpu_types) String(rx200) Value(RX200)
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60
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61 EnumValue
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62 Enum(rx_cpu_types) String(rx600) Value(RX600)
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63
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64 EnumValue
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65 Enum(rx_cpu_types) String(rx100) Value(RX100)
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66
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67 ;---------------------------------------------------
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68
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69 mbig-endian-data
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70 Target RejectNegative Mask(BIG_ENDIAN_DATA) Report
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71 Data is stored in big-endian format.
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72
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73 mlittle-endian-data
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74 Target RejectNegative InverseMask(BIG_ENDIAN_DATA) Report
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75 Data is stored in little-endian format. (Default).
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76
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77 ;---------------------------------------------------
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78
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79 msmall-data-limit=
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80 Target RejectNegative Joined UInteger Var(rx_small_data_limit) Init(0)
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81 Maximum size of global and static variables which can be placed into the small data area.
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82
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83 ;---------------------------------------------------
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84
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85 msim
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86 Target
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87 Use the simulator runtime.
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88
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89 ;---------------------------------------------------
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90
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91 mas100-syntax
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92 Target Mask(AS100_SYNTAX) Report
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93 Generate assembler output that is compatible with the Renesas AS100 assembler. This may restrict some of the compiler's capabilities. The default is to generate GAS compatible syntax.
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94
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95 ;---------------------------------------------------
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96
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97 mrelax
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98 Target
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99 Enable linker relaxation.
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100
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101 ;---------------------------------------------------
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102
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103 mmax-constant-size=
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104 Target RejectNegative Joined UInteger Var(rx_max_constant_size) Init(0)
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105 Maximum size in bytes of constant values allowed as operands.
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106
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107 ;---------------------------------------------------
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108
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109 mint-register=
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110 Target RejectNegative Joined UInteger Var(rx_deferred_options) Defer
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111 Specifies the number of registers to reserve for interrupt handlers.
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112
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113 ;---------------------------------------------------
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114
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115 msave-acc-in-interrupts
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116 Target Mask(SAVE_ACC_REGISTER)
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117 Specifies whether interrupt functions should save and restore the accumulator register.
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118
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119 ;---------------------------------------------------
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120
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121 mpid
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122 Target Mask(PID)
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123 Enables Position-Independent-Data (PID) mode.
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124
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125 ;---------------------------------------------------
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126
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127 mwarn-multiple-fast-interrupts
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128 Target Report Var(rx_warn_multiple_fast_interrupts) Init(1) Warning
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129 Warn when multiple, different, fast interrupt handlers are in the compilation unit.
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130
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131 ;---------------------------------------------------
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132
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133 mgcc-abi
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134 Target RejectNegative Report Mask(GCC_ABI)
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135 Enable the use of the old, broken, ABI where all stacked function arguments are aligned to 32-bits.
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136
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137 mrx-abi
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138 Target RejectNegative Report InverseMask(GCC_ABI)
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139 Enable the use the standard RX ABI where all stacked function arguments are naturally aligned. This is the default.
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140
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141 ;---------------------------------------------------
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142
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143 mlra
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144 Target Report Mask(ENABLE_LRA)
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145 Enable the use of the LRA register allocator.
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146
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147 ;---------------------------------------------------
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148
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149 mallow-string-insns
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150 Target Report Var(rx_allow_string_insns) Init(1)
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151 Enables or disables the use of the SMOVF, SMOVB, SMOVU, SUNTIL, SWHILE and RMPA instructions. Enabled by default.
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152
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153 ;---------------------------------------------------
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154
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155 mjsr
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156 Target Report Mask(JSR)
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157 Always use JSR, never BSR, for calls.