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1 ;; Scheduling description for Niagara-4
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2 ;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_automaton "niagara4_0")
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21
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22 (define_cpu_unit "n4_slot0,n4_slot1,n4_slot2" "niagara4_0")
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23 (define_reservation "n4_single_issue" "n4_slot0 + n4_slot1 + n4_slot2")
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24
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25 (define_cpu_unit "n4_load_store" "niagara4_0")
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26
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27 (define_insn_reservation "n4_single" 1
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28 (and (eq_attr "cpu" "niagara4")
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29 (eq_attr "type" "multi,savew,flushw,iflush,trap"))
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30 "n4_single_issue")
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31
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32 (define_insn_reservation "n4_integer" 1
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33 (and (eq_attr "cpu" "niagara4")
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34 (eq_attr "type" "ialu,ialuX,shift,cmove,compare"))
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35 "(n4_slot0 | n4_slot1)")
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36
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37 (define_insn_reservation "n4_imul" 12
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38 (and (eq_attr "cpu" "niagara4")
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39 (eq_attr "type" "imul"))
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40 "n4_slot1, nothing*11")
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41
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42 (define_insn_reservation "n4_idiv" 35
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43 (and (eq_attr "cpu" "niagara4")
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44 (eq_attr "type" "idiv"))
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45 "n4_slot1, nothing*34")
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46
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47 (define_insn_reservation "n4_load" 5
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48 (and (eq_attr "cpu" "niagara4")
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49 (eq_attr "type" "load,fpload,sload"))
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50 "(n4_slot0 + n4_load_store), nothing*4")
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51
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52 (define_insn_reservation "n4_store" 1
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53 (and (eq_attr "cpu" "niagara4")
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54 (eq_attr "type" "store,fpstore"))
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55 "(n4_slot0 | n4_slot2) + n4_load_store")
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56
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57 (define_insn_reservation "n4_cti" 1
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58 (and (eq_attr "cpu" "niagara4")
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59 (eq_attr "type" "cbcond,uncond_cbcond,branch,call,sibcall,call_no_delay_slot,uncond_branch,return"))
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60 "n4_slot1")
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61
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62 (define_insn_reservation "n4_fp" 11
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63 (and (eq_attr "cpu" "niagara4")
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64 (eq_attr "type" "fpmove,fpcmove,fpcrmove,fp,fpcmp,fpmul"))
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65 "n4_slot1, nothing*10")
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66
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67 (define_insn_reservation "n4_array" 12
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68 (and (eq_attr "cpu" "niagara4")
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69 (eq_attr "type" "array,bmask,edge,edgen"))
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70 "n4_slot1, nothing*11")
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71
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72 (define_insn_reservation "n4_vis_move_1cycle" 1
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73 (and (eq_attr "cpu" "niagara4")
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74 (and (eq_attr "type" "vismv")
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75 (eq_attr "fptype" "double")))
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76 "n4_slot1")
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77
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78 ;; The latency numbers for VIS instructions in the reservations below
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79 ;; reflect empirical results, and don't match with the documented
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80 ;; latency numbers in the T4 Processor Supplement. This is because
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81 ;; the HW chaps didn't feel it necessary to document the complexity in
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82 ;; the PRM, and just assigned a latency of 11 to all/most of the VIS
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83 ;; instructions.
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84
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85 (define_insn_reservation "n4_vis_move_11cycle" 11
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86 (and (eq_attr "cpu" "niagara4")
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87 (and (eq_attr "type" "vismv")
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88 (eq_attr "fptype" "single")))
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89 "n4_slot1, nothing*10")
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90
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91 (define_insn_reservation "n4_vis_logical" 3
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92 (and (eq_attr "cpu" "niagara4")
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93 (ior (and (eq_attr "type" "visl,pdistn")
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94 (eq_attr "fptype" "double"))
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95 (eq_attr "type" "viscmp")))
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96 "n4_slot1, nothing*2")
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97
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98 (define_insn_reservation "n4_vis_logical_11cycle" 11
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99 (and (eq_attr "cpu" "niagara4")
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100 (and (eq_attr "type" "visl")
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101 (eq_attr "fptype" "single")))
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102 "n4_slot1, nothing*10")
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103
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104 (define_insn_reservation "n4_vis_fga" 11
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105 (and (eq_attr "cpu" "niagara4")
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106 (eq_attr "type" "fga,gsr"))
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107 "n4_slot1, nothing*10")
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108
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109 (define_insn_reservation "n4_vis_fgm" 11
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110 (and (eq_attr "cpu" "niagara4")
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111 (eq_attr "type" "fgm_pack,fgm_mul,pdist"))
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112 "n4_slot1, nothing*10")
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113
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114 (define_insn_reservation "n4_fpdivs" 24
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115 (and (eq_attr "cpu" "niagara4")
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116 (eq_attr "type" "fpdivs,fpsqrts"))
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117 "n4_slot1, nothing*23")
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118
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119 (define_insn_reservation "n4_fpdivd" 37
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120 (and (eq_attr "cpu" "niagara4")
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121 (eq_attr "type" "fpdivd,fpsqrtd"))
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122 "n4_slot1, nothing*36")
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