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1 ;; Scheduling description for UltraSPARC-I/II.
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2 ;; Copyright (C) 2002-2018 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; UltraSPARC-I and II are quad-issue processors. Interesting features
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21 ;; to note:
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22 ;;
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23 ;; - Buffered loads, they can queue waiting for the actual data until
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24 ;; an instruction actually tries to reference the destination register
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25 ;; as an input
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26 ;; - Two integer units. Only one of them can do shifts, and the other
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27 ;; is the only one which may do condition code setting instructions.
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28 ;; Complicating things further, a shift may go only into the first
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29 ;; slot in a dispatched group. And if you have a non-condition code
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30 ;; setting instruction and one that does set the condition codes. The
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31 ;; former must be issued first in order for both of them to issue.
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32 ;; - Stores can issue before the value being stored is available. As long
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33 ;; as the input data becomes ready before the store is to move out of the
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34 ;; store buffer, it will not cause a stall.
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35 ;; - Branches may issue in the same cycle as an instruction setting the
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36 ;; condition codes being tested by that branch. This does not apply
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37 ;; to floating point, only integer.
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38
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39 (define_automaton "ultrasparc_0,ultrasparc_1")
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40
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41 (define_cpu_unit "us1_fdivider,us1_fpm" "ultrasparc_0");
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42 (define_cpu_unit "us1_fpa,us1_load_writeback" "ultrasparc_1")
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43 (define_cpu_unit "us1_fps_0,us1_fps_1,us1_fpd_0,us1_fpd_1" "ultrasparc_1")
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44 (define_cpu_unit "us1_slot0,us1_slot1,us1_slot2,us1_slot3" "ultrasparc_1")
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45 (define_cpu_unit "us1_ieu0,us1_ieu1,us1_cti,us1_lsu" "ultrasparc_1")
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46
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47 (define_reservation "us1_slot012" "(us1_slot0 | us1_slot1 | us1_slot2)")
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48 (define_reservation "us1_slotany" "(us1_slot0 | us1_slot1 | us1_slot2 | us1_slot3)")
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49 (define_reservation "us1_single_issue" "us1_slot0 + us1_slot1 + us1_slot2 + us1_slot3")
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50
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51 (define_reservation "us1_fp_single" "(us1_fps_0 | us1_fps_1)")
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52 (define_reservation "us1_fp_double" "(us1_fpd_0 | us1_fpd_1)")
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53
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54 ;; This is a simplified representation of the issue at hand.
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55 ;; For most cases, going from one FP precision type insn to another
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56 ;; just breaks up the insn group. However for some cases, such
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57 ;; a situation causes the second insn to stall 2 more cycles.
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58 (exclusion_set "us1_fps_0,us1_fps_1" "us1_fpd_0,us1_fpd_1")
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59
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60 ;; If we have to schedule an ieu1 specific instruction and we want
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61 ;; to reserve the ieu0 unit as well, we must reserve it first. So for
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62 ;; example we could not schedule this sequence:
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63 ;; COMPARE IEU1
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64 ;; IALU IEU0
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65 ;; but we could schedule them together like this:
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66 ;; IALU IEU0
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67 ;; COMPARE IEU1
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68 ;; This basically requires that ieu0 is reserved before ieu1 when
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69 ;; it is required that both be reserved.
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70 (absence_set "us1_ieu0" "us1_ieu1")
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71
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72 ;; This defines the slotting order. Most IEU instructions can only
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73 ;; execute in the first three slots, FPU and branches can go into
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74 ;; any slot. We represent instructions which "break the group"
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75 ;; as requiring reservation of us1_slot0.
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76 (absence_set "us1_slot0" "us1_slot1,us1_slot2,us1_slot3")
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77 (absence_set "us1_slot1" "us1_slot2,us1_slot3")
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78 (absence_set "us1_slot2" "us1_slot3")
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79
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80 (define_insn_reservation "us1_single" 1
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81 (and (eq_attr "cpu" "ultrasparc")
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82 (eq_attr "type" "multi,savew,flushw,iflush,trap,gsr"))
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83 "us1_single_issue")
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84
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85 (define_insn_reservation "us1_simple_ieuN" 1
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86 (and (eq_attr "cpu" "ultrasparc")
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87 (eq_attr "type" "ialu"))
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88 "(us1_ieu0 | us1_ieu1) + us1_slot012")
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89
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90 (define_insn_reservation "us1_simple_ieu0" 1
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91 (and (eq_attr "cpu" "ultrasparc")
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92 (eq_attr "type" "shift"))
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93 "us1_ieu0 + us1_slot012")
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94
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95 (define_insn_reservation "us1_simple_ieu1" 1
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96 (and (eq_attr "cpu" "ultrasparc")
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111
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97 (eq_attr "type" "compare,edge,edgen,array"))
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98 "us1_ieu1 + us1_slot012")
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99
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100 (define_insn_reservation "us1_ialuX" 1
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101 (and (eq_attr "cpu" "ultrasparc")
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102 (eq_attr "type" "ialuX"))
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103 "us1_single_issue")
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104
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105 (define_insn_reservation "us1_cmove" 2
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106 (and (eq_attr "cpu" "ultrasparc")
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107 (eq_attr "type" "cmove"))
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108 "us1_single_issue, nothing")
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109
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110 (define_insn_reservation "us1_imul" 1
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111 (and (eq_attr "cpu" "ultrasparc")
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112 (eq_attr "type" "imul"))
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113 "us1_single_issue")
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114
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115 (define_insn_reservation "us1_idiv" 1
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116 (and (eq_attr "cpu" "ultrasparc")
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117 (eq_attr "type" "idiv"))
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118 "us1_single_issue")
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119
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120 ;; For loads, the "delayed return mode" behavior of the chip
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121 ;; is represented using the us1_load_writeback resource.
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122 (define_insn_reservation "us1_load" 2
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123 (and (eq_attr "cpu" "ultrasparc")
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124 (eq_attr "type" "load,fpload"))
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125 "us1_lsu + us1_slot012, us1_load_writeback")
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126
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127 (define_insn_reservation "us1_load_signed" 3
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128 (and (eq_attr "cpu" "ultrasparc")
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129 (eq_attr "type" "sload"))
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130 "us1_lsu + us1_slot012, nothing, us1_load_writeback")
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131
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132 (define_insn_reservation "us1_store" 1
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133 (and (eq_attr "cpu" "ultrasparc")
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134 (eq_attr "type" "store,fpstore"))
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135 "us1_lsu + us1_slot012")
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136
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137 (define_insn_reservation "us1_branch" 1
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138 (and (eq_attr "cpu" "ultrasparc")
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139 (eq_attr "type" "branch"))
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140 "us1_cti + us1_slotany")
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141
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142 (define_insn_reservation "us1_call_jmpl" 1
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143 (and (eq_attr "cpu" "ultrasparc")
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144 (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch"))
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145 "us1_cti + us1_ieu1 + us1_slot0")
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146
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147 (define_insn_reservation "us1_fmov_single" 1
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148 (and (and (eq_attr "cpu" "ultrasparc")
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149 (eq_attr "type" "fpmove"))
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150 (eq_attr "fptype" "single"))
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151 "us1_fpa + us1_fp_single + us1_slotany")
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152
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153 (define_insn_reservation "us1_fmov_double" 1
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154 (and (and (eq_attr "cpu" "ultrasparc")
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155 (eq_attr "type" "fpmove"))
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156 (eq_attr "fptype" "double"))
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157 "us1_fpa + us1_fp_double + us1_slotany")
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158
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159 (define_insn_reservation "us1_fcmov_single" 2
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160 (and (and (eq_attr "cpu" "ultrasparc")
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161 (eq_attr "type" "fpcmove,fpcrmove"))
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162 (eq_attr "fptype" "single"))
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163 "us1_fpa + us1_fp_single + us1_slotany, nothing")
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164
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165 (define_insn_reservation "us1_fcmov_double" 2
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166 (and (and (eq_attr "cpu" "ultrasparc")
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167 (eq_attr "type" "fpcmove,fpcrmove"))
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168 (eq_attr "fptype" "double"))
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169 "us1_fpa + us1_fp_double + us1_slotany, nothing")
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170
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171 (define_insn_reservation "us1_faddsub_single" 4
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172 (and (and (eq_attr "cpu" "ultrasparc")
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173 (eq_attr "type" "fp"))
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174 (eq_attr "fptype" "single"))
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175 "us1_fpa + us1_fp_single + us1_slotany, nothing*3")
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176
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177 (define_insn_reservation "us1_faddsub_double" 4
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178 (and (and (eq_attr "cpu" "ultrasparc")
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179 (eq_attr "type" "fp"))
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180 (eq_attr "fptype" "double"))
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181 "us1_fpa + us1_fp_double + us1_slotany, nothing*3")
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182
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183 (define_insn_reservation "us1_fpcmp_single" 1
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184 (and (and (eq_attr "cpu" "ultrasparc")
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185 (eq_attr "type" "fpcmp"))
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186 (eq_attr "fptype" "single"))
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187 "us1_fpa + us1_fp_single + us1_slotany")
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188
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189 (define_insn_reservation "us1_fpcmp_double" 1
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190 (and (and (eq_attr "cpu" "ultrasparc")
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191 (eq_attr "type" "fpcmp"))
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192 (eq_attr "fptype" "double"))
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193 "us1_fpa + us1_fp_double + us1_slotany")
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194
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195 (define_insn_reservation "us1_fmult_single" 4
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196 (and (and (eq_attr "cpu" "ultrasparc")
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197 (eq_attr "type" "fpmul"))
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198 (eq_attr "fptype" "single"))
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199 "us1_fpm + us1_fp_single + us1_slotany, nothing*3")
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200
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201 (define_insn_reservation "us1_fmult_double" 4
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202 (and (and (eq_attr "cpu" "ultrasparc")
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203 (eq_attr "type" "fpmul"))
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204 (eq_attr "fptype" "double"))
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205 "us1_fpm + us1_fp_double + us1_slotany, nothing*3")
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206
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207 ;; This is actually in theory dangerous, because it is possible
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208 ;; for the chip to prematurely dispatch the dependent instruction
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209 ;; in the G stage, resulting in a 9 cycle stall. However I have never
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210 ;; been able to trigger this case myself even with hand written code,
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211 ;; so it must require some rare complicated pipeline state.
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212 (define_bypass 3
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213 "us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double"
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214 "us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double")
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215
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216 ;; Floating point divide and square root use the multiplier unit
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217 ;; for final rounding 3 cycles before the divide/sqrt is complete.
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218
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219 (define_insn_reservation "us1_fdivs"
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220 13
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221 (and (eq_attr "cpu" "ultrasparc")
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222 (eq_attr "type" "fpdivs,fpsqrts"))
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223 "(us1_fpm + us1_fdivider + us1_slot0), us1_fdivider*8, (us1_fpm + us1_fdivider), us1_fdivider*2"
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224 )
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225
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226 (define_bypass
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227 12
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228 "us1_fdivs"
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229 "us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double")
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230
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231 (define_insn_reservation "us1_fdivd"
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232 23
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233 (and (eq_attr "cpu" "ultrasparc")
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234 (eq_attr "type" "fpdivd,fpsqrtd"))
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235 "(us1_fpm + us1_fdivider + us1_slot0), us1_fdivider*18, (us1_fpm + us1_fdivider), us1_fdivider*2"
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236 )
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237 (define_bypass
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238 22
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239 "us1_fdivd"
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240 "us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double")
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241
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242 ;; Any store may multi issue with the insn creating the source
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243 ;; data as long as that creating insn is not an FPU div/sqrt.
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244 ;; We need a special guard function because this bypass does
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245 ;; not apply to the address inputs of the store.
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246 (define_bypass 0 "us1_simple_ieuN,us1_simple_ieu1,us1_simple_ieu0,us1_faddsub_single,us1_faddsub_double,us1_fmov_single,us1_fmov_double,us1_fcmov_single,us1_fcmov_double,us1_fmult_single,us1_fmult_double" "us1_store"
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247 "store_data_bypass_p")
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248
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249 ;; An integer branch may execute in the same cycle as the compare
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250 ;; creating the condition codes.
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251 (define_bypass 0 "us1_simple_ieu1" "us1_branch")
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252
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253 ;; VIS scheduling
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254 (define_insn_reservation "us1_fga_single"
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255 2
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256 (and (and
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257 (eq_attr "cpu" "ultrasparc")
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111
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258 (eq_attr "type" "fga,visl,vismv"))
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0
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259 (eq_attr "fptype" "single"))
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260 "us1_fpa + us1_fp_single + us1_slotany, nothing")
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261
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262 (define_bypass 1 "us1_fga_single" "us1_fga_single")
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263
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264 (define_insn_reservation "us1_fga_double"
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265 2
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111
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266 (and (eq_attr "cpu" "ultrasparc")
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267 (ior (and (eq_attr "type" "fga,visl,vismv")
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268 (eq_attr "fptype" "double"))
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269 (eq_attr "type" "viscmp")))
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0
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270 "us1_fpa + us1_fp_double + us1_slotany, nothing")
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271
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272 (define_bypass 1 "us1_fga_double" "us1_fga_double")
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273
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274 (define_insn_reservation "us1_fgm_single"
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275 4
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276 (and (and
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277 (eq_attr "cpu" "ultrasparc")
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111
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278 (eq_attr "type" "fgm_pack,fgm_mul"))
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279 (eq_attr "fptype" "single"))
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280 "us1_fpm + us1_fp_single + us1_slotany, nothing*3")
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281
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282 (define_bypass 3 "us1_fgm_single" "us1_fga_single")
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283
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284 (define_insn_reservation "us1_fgm_double"
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285 4
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286 (and (and
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287 (eq_attr "cpu" "ultrasparc")
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111
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288 (eq_attr "type" "fgm_pack,fgm_mul"))
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289 (eq_attr "fptype" "double"))
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290 "us1_fpm + us1_fp_double + us1_slotany, nothing*3")
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291
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292 (define_bypass 3 "us1_fgm_double" "us1_fga_double")
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293
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294 (define_insn_reservation "us1_pdist"
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295 4
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296 (and (eq_attr "cpu" "ultrasparc")
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111
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297 (eq_attr "type" "pdist"))
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0
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298 "us1_fpm + us1_fp_double + us1_slotany, nothing*3")
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299
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300 (define_bypass 3 "us1_pdist" "us1_fga_double,us1_fga_single")
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301 (define_bypass 1 "us1_pdist" "us1_pdist")
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