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annotate gcc/config/tilegx/tilegx-generic.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
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1 ;; Scheduling description for Tilera TILE-Gx chip.
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84e7813d76e9 gcc-8.2
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2 ;; Copyright (C) 2011-2018 Free Software Foundation, Inc.
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3 ;; Contributed by Walter Lee (walt@tilera.com)
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_automaton "tile")
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22
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23 ; Make the scheduling automaton an ndfa.
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24 (automata_option "ndfa")
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25
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26 ; Name the three pipes.
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27 (define_cpu_unit "X0" "tile")
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28 (define_cpu_unit "X1" "tile")
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29 (define_cpu_unit "Y0" "tile")
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30 (define_cpu_unit "Y1" "tile")
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31 (define_cpu_unit "Y2" "tile")
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32
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33 (define_insn_reservation "X0" 1
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34 (eq_attr "type" "X0")
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35 "X0")
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36
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37 (define_insn_reservation "X0_2cycle" 2
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38 (eq_attr "type" "X0_2cycle")
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39 "X0,nothing")
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40
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41 (define_insn_reservation "X1" 1
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42 (eq_attr "type" "X1,X1_branch")
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43 "X1")
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44
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45 (define_insn_reservation "X1_2cycle" 2
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46 (eq_attr "type" "X1_2cycle")
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47 "X1,nothing")
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48
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49 (define_insn_reservation "X1_L2" 11
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50 (eq_attr "type" "X1_L2")
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51 "X1")
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52
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53 (define_insn_reservation "X1_remote" 50
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54 (eq_attr "type" "X1_remote")
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55 "X1")
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56
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57 (define_insn_reservation "X1_miss" 80
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58 (eq_attr "type" "X1_miss")
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59 "X1")
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60
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61 (define_insn_reservation "X01" 1
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62 (eq_attr "type" "X01")
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63 "X0|X1")
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64
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65 (define_insn_reservation "Y0" 1
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66 (eq_attr "type" "Y0")
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67 "Y0|X0")
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68
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69 (define_insn_reservation "Y0_2cycle" 2
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70 (eq_attr "type" "Y0_2cycle")
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71 "Y0|X0,nothing")
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72
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73 (define_insn_reservation "Y1" 1
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74 (eq_attr "type" "Y1")
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75 "Y1|X1")
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76
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77 (define_insn_reservation "Y2" 1
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78 (eq_attr "type" "Y2")
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79 "Y2|X1")
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80
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81 (define_insn_reservation "Y2_2cycle" 2
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82 (eq_attr "type" "Y2_2cycle")
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83 "Y2|X1,nothing")
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84
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85 (define_insn_reservation "Y2_L2" 11
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86 (eq_attr "type" "Y2_L2")
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87 "Y2|X1")
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88
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89 (define_insn_reservation "Y2_miss" 80
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90 (eq_attr "type" "Y2_miss")
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91 "Y2|X1")
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92
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93 (define_insn_reservation "Y01" 1
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94 (eq_attr "type" "Y01")
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95 "Y0|Y1|X0|X1")
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96
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97 (define_insn_reservation "nothing" 0
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98 (eq_attr "type" "nothing")
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99 "nothing")
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100
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101 (define_insn_reservation "cannot_bundle" 1
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102 (eq_attr "type" "cannot_bundle")
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103 "X0+X1")
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104
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105 (define_insn_reservation "cannot_bundle_3cycle" 3
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106 (eq_attr "type" "cannot_bundle_3cycle")
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107 "X0+X1")
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108
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109 (define_insn_reservation "cannot_bundle_4cycle" 4
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110 (eq_attr "type" "cannot_bundle_4cycle")
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111 "X0+X1")
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112
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113
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114 ; A bundle must be in either X format or Y format.
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115 (exclusion_set "X0,X1" "Y0,Y1,Y2")