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1 /* PR target/27861 */
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2 /* The following code used to cause an ICE during RTL expansion, as
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3 expand shift was stripping the SUBREG of a rotate shift count, and
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4 later producing a VAR_DECL tree whose DECL_RTL's mode didn't match
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5 the VAR_DECL's type's mode. */
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6 /* { dg-do compile } */
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7 /* { dg-options "-O2" } */
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8
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9 typedef struct sim_state *SIM_DESC;
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10 typedef enum
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11 {
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12 SIM_OPEN_STANDALONE, SIM_OPEN_DEBUG
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13 }
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14 SIM_RC;
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15 typedef unsigned int unsigned32 __attribute__ ((__mode__ (__SI__)));
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16 typedef unsigned int unsigned64 __attribute__ ((__mode__ (__DI__)));
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17 typedef unsigned32 unsigned_address;
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18 typedef unsigned_address address_word;
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19 static __inline__ unsigned64
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20 __attribute__ ((__unused__)) ROTR64 (unsigned64 val, int shift)
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21 {
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22 unsigned64 result;
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23 result = (((val) >> (shift)) | ((val) << ((64) - (shift))));
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24 return result;
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25 }
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26 typedef struct _sim_cpu sim_cpu;
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27 enum
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28 {
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29 TRACE_MEMORY_IDX, TRACE_MODEL_IDX, TRACE_ALU_IDX, TRACE_CORE_IDX,
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30 };
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31 typedef struct _trace_data
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32 {
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33 char trace_flags[32];
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34 }
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35 TRACE_DATA;
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36 typedef enum
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37 {
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38 nr_watchpoint_types,
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39 }
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40 watchpoint_type;
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41 typedef struct _sim_watchpoints
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42 {
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43 TRACE_DATA trace_data;
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44 }
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45 sim_cpu_base;
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46 struct _sim_cpu
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47 {
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48 sim_cpu_base base;
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49 };
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50 struct sim_state
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51 {
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52 sim_cpu cpu[1];
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53 };
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54 typedef address_word instruction_address;
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55 void trace_result_word1 ();
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56 int
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57 do_dror (SIM_DESC sd, instruction_address cia, int MY_INDEX, unsigned64 x,
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58 unsigned64 y)
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59 {
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60 unsigned64 result;
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61 result = ROTR64 (x, y);
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62 {
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63 if ((((-1) & (1 << (TRACE_ALU_IDX))) != 0
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64 && (((&(((&(sd)->cpu[0])))->base.trace_data))->
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65 trace_flags)[TRACE_ALU_IDX] != 0))
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66 trace_result_word1 (sd, ((&(sd)->cpu[0])), TRACE_ALU_IDX, (result));
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67 }
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68 }
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69
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